fix(CSR): fix shadow writing for custom PMA CSRs not in `csrRwMap` (#3966)

timing(csr): add 1 cycle to csr read/write and select highest interrupt priority (#3946)

This PR adds 1 cycle for csr read/write and selects highest interrupt
priority to fix timing.

fix(dbltrp): fix sdt/dte interaction logic

* menvcfg.DTE only control Smode dbltrp. Thus mstatus.sdt will not
control by DTE.
* as sstatus is alias of mstatus, when menvcfg.DTE close write

fix(dbltrp): fix sdt/dte interaction logic

* menvcfg.DTE only control Smode dbltrp. Thus mstatus.sdt will not
control by DTE.
* as sstatus is alias of mstatus, when menvcfg.DTE close write
sstatus.sdt cannot lead to shadow write of mstatus.sdt. As a result,
we add wmask of sdt, when write source is from alias write.
While vsstatus is not alias of any other CSR fields, so origin logic
is correct.

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fix(intr): fix stopi is not zero

fix(intr): fix interrupt select for VS-level

fix(aia): fix hviprio bundle

fix(aia): fix iprios bundle

feat(CSR): add No.14,15 interrupts

fix(intr): fix minSelect method

fix(csr): add AIA xtopei event diff and remove AIA csr skip

fix(intr): fix interrupt trap to which mode to handle

fix(csr): fix interrupt code use xtopi.IID replace instread of xip & xie

fix(CSR): correct the width of PC pgaddr for inst fetch exception (#3795)

We found that the CSR mtval2 truncates the high bits of gpaddr when GPF
occurs in instruction fetching. Actually, there is

fix(CSR): correct the width of PC pgaddr for inst fetch exception (#3795)

We found that the CSR mtval2 truncates the high bits of gpaddr when GPF
occurs in instruction fetching. Actually, there is an GPAMem which
storages the whole 64-bit gpaddr, but it does not pass to CSR correctly,
due to incorrect width of trapPCGPA in module NewCSR and bundle
TrapEntryEventInput. This patch fixes this.

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Co-authored-by: ngc7331 <[email protected]>

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fix(dret): fix update of privstate in dretevent (#3898)

ref: When an MRET instruction is executed, the virtualization mode V
is set to MPV, unless MPP=3, in which case V remains 0

fix(critical-error): critical-error pass early then trap (#3885)

* critical-error diff REF as xiangshan pass criticial-error too early
* bump difftest to make critical_error more prominent

docs: add acknowledgements (#3861)

fix(xtval): fix selection of tval for trap

fix(vstval): update vstval when trigger generate breakpoint exception

fix(dcsr): debug support critical error state

* support nmip, cetrig, extcause fileds in dcsr.
* critical error state enter dmode when dcsr.cetrig assert.

fix(CSR): fix dcsr to support stopcount & stoptime

fix(CSR,RVC): c.fp instrs should be illegal when fs is off (#3859)

* fix RVC floating-point inst raise EX_II in predecode when xstatus.fs
is off

Fix #3864

Update: https://github.com/OpenXiang

fix(CSR,RVC): c.fp instrs should be illegal when fs is off (#3859)

* fix RVC floating-point inst raise EX_II in predecode when xstatus.fs
is off

Fix #3864

Update: https://github.com/OpenXiangShan/rocket-chip/pull/20 is merged
and this PR is rebased, ready to review.

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Co-authored-by: sinceforYy <[email protected]>

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feat(zvfh,zfh): add F16 support

fix(mip): mip.seip is alias of mvip.seip when mvien.seie = 0

fix(mip): add otherwise when wen mip

fix(intr): set the sequence of interrupt in different mode

* Debug > NMI> M > HS > VS