1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import coupledL2.tl2chi._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.{max, min, pow} 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBitsSv39: Int = 39, 72 GPAddrBitsSv39x4: Int = 41, 73 VAddrBitsSv48: Int = 48, 74 GPAddrBitsSv48x4: Int = 50, 75 HasFPU: Boolean = true, 76 HasVPU: Boolean = true, 77 HasCustomCSRCacheOp: Boolean = true, 78 FetchWidth: Int = 8, 79 AsidLength: Int = 16, 80 VmidLength: Int = 14, 81 EnableBPU: Boolean = true, 82 EnableBPD: Boolean = true, 83 EnableRAS: Boolean = true, 84 EnableLB: Boolean = false, 85 EnableLoop: Boolean = true, 86 EnableSC: Boolean = true, 87 EnbaleTlbDebug: Boolean = false, 88 EnableClockGate: Boolean = true, 89 EnableJal: Boolean = false, 90 EnableFauFTB: Boolean = true, 91 EnableSv48: Boolean = true, 92 UbtbGHRLength: Int = 4, 93 // HistoryLength: Int = 512, 94 EnableGHistDiff: Boolean = true, 95 EnableCommitGHistDiff: Boolean = true, 96 UbtbSize: Int = 256, 97 FtbSize: Int = 2048, 98 FtbWays: Int = 4, 99 FtbTagLength: Int = 20, 100 RasSize: Int = 16, 101 RasSpecSize: Int = 32, 102 RasCtrSize: Int = 3, 103 CacheLineSize: Int = 512, 104 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 105 // Sets Hist Tag 106 Seq(( 4096, 8, 8), 107 ( 4096, 13, 8), 108 ( 4096, 32, 8), 109 ( 4096, 119, 8)), 110 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 111 // Sets Hist Tag 112 Seq(( 256, 4, 9), 113 ( 256, 8, 9), 114 ( 512, 13, 9), 115 ( 512, 16, 9), 116 ( 512, 32, 9)), 117 SCNRows: Int = 512, 118 SCNTables: Int = 4, 119 SCCtrBits: Int = 6, 120 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 121 numBr: Int = 2, 122 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 123 (resp_in: BranchPredictionResp, p: Parameters) => { 124 val ftb = Module(new FTB()(p)) 125 val uftb = Module(new FauFTB()(p)) 126 val tage = Module(new Tage_SC()(p)) 127 val ras = Module(new RAS()(p)) 128 val ittage = Module(new ITTage()(p)) 129 val preds = Seq(uftb, tage, ftb, ittage, ras) 130 preds.map(_.io := DontCare) 131 132 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 133 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 134 135 uftb.io.in.bits.resp_in(0) := resp_in 136 tage.io.in.bits.resp_in(0) := uftb.io.out 137 ftb.io.in.bits.resp_in(0) := tage.io.out 138 ittage.io.in.bits.resp_in(0) := ftb.io.out 139 ras.io.in.bits.resp_in(0) := ittage.io.out 140 141 (preds, ras.io.out) 142 }, 143 ICacheForceMetaECCError: Boolean = false, 144 ICacheForceDataECCError: Boolean = false, 145 IBufSize: Int = 48, 146 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 147 DecodeWidth: Int = 6, 148 RenameWidth: Int = 6, 149 CommitWidth: Int = 8, 150 RobCommitWidth: Int = 8, 151 RabCommitWidth: Int = 6, 152 MaxUopSize: Int = 65, 153 EnableRenameSnapshot: Boolean = true, 154 RenameSnapshotNum: Int = 4, 155 FtqSize: Int = 64, 156 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 157 IntLogicRegs: Int = 32, 158 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 159 VecLogicRegs: Int = 32 + 15, // 15: tmp 160 V0LogicRegs: Int = 1, // V0 161 VlLogicRegs: Int = 1, // Vl 162 V0_IDX: Int = 0, 163 Vl_IDX: Int = 0, 164 NRPhyRegs: Int = 192, 165 VirtualLoadQueueSize: Int = 72, 166 LoadQueueRARSize: Int = 72, 167 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 168 RollbackGroupSize: Int = 8, 169 LoadQueueReplaySize: Int = 72, 170 LoadUncacheBufferSize: Int = 20, 171 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 172 StoreQueueSize: Int = 64, 173 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 174 StoreQueueForwardWithMask: Boolean = true, 175 VlsQueueSize: Int = 8, 176 RobSize: Int = 160, 177 RabSize: Int = 256, 178 VTypeBufferSize: Int = 64, // used to reorder vtype 179 IssueQueueSize: Int = 24, 180 IssueQueueCompEntrySize: Int = 16, 181 dpParams: DispatchParameters = DispatchParameters( 182 IntDqSize = 16, 183 FpDqSize = 16, 184 LsDqSize = 18, 185 IntDqDeqWidth = 8, 186 FpDqDeqWidth = 6, 187 VecDqDeqWidth = 6, 188 LsDqDeqWidth = 6, 189 ), 190 intPreg: PregParams = IntPregParams( 191 numEntries = 224, 192 numRead = None, 193 numWrite = None, 194 ), 195 fpPreg: PregParams = FpPregParams( 196 numEntries = 192, 197 numRead = None, 198 numWrite = None, 199 ), 200 vfPreg: VfPregParams = VfPregParams( 201 numEntries = 128, 202 numRead = None, 203 numWrite = None, 204 ), 205 v0Preg: V0PregParams = V0PregParams( 206 numEntries = 22, 207 numRead = None, 208 numWrite = None, 209 ), 210 vlPreg: VlPregParams = VlPregParams( 211 numEntries = 32, 212 numRead = None, 213 numWrite = None, 214 ), 215 IntRegCacheSize: Int = 16, 216 MemRegCacheSize: Int = 12, 217 intSchdVlWbPort: Int = 0, 218 vfSchdVlWbPort: Int = 1, 219 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 220 IfuRedirectNum: Int = 1, 221 LoadPipelineWidth: Int = 3, 222 StorePipelineWidth: Int = 2, 223 VecLoadPipelineWidth: Int = 2, 224 VecStorePipelineWidth: Int = 2, 225 VecMemSrcInWidth: Int = 2, 226 VecMemInstWbWidth: Int = 1, 227 VecMemDispatchWidth: Int = 1, 228 VecMemDispatchMaxNumber: Int = 16, 229 VecMemUnitStrideMaxFlowNum: Int = 2, 230 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 2, 2, 2, 2, 2), 231 StoreBufferSize: Int = 16, 232 StoreBufferThreshold: Int = 7, 233 EnsbufferWidth: Int = 2, 234 LoadDependencyWidth: Int = 2, 235 // ============ VLSU ============ 236 VlMergeBufferSize: Int = 16, 237 VsMergeBufferSize: Int = 16, 238 UopWritebackWidth: Int = 2, 239 VLUopWritebackWidth: Int = 2, 240 VSUopWritebackWidth: Int = 1, 241 VSegmentBufferSize: Int = 8, 242 VFOFBufferSize: Int = 8, 243 VLFOFWritebackWidth: Int = 1, 244 // ============================== 245 UncacheBufferSize: Int = 4, 246 EnableLoadToLoadForward: Boolean = false, 247 EnableFastForward: Boolean = true, 248 EnableLdVioCheckAfterReset: Boolean = true, 249 EnableSoftPrefetchAfterReset: Boolean = true, 250 EnableCacheErrorAfterReset: Boolean = true, 251 EnableAccurateLoadError: Boolean = false, 252 EnableUncacheWriteOutstanding: Boolean = false, 253 EnableHardwareStoreMisalign: Boolean = true, 254 EnableHardwareLoadMisalign: Boolean = true, 255 EnableStorePrefetchAtIssue: Boolean = false, 256 EnableStorePrefetchAtCommit: Boolean = false, 257 EnableAtCommitMissTrigger: Boolean = true, 258 EnableStorePrefetchSMS: Boolean = false, 259 EnableStorePrefetchSPB: Boolean = false, 260 HasCMO: Boolean = true, 261 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 262 MMUVmidLen: Int = 14, 263 ReSelectLen: Int = 7, // load replay queue replay select counter len 264 iwpuParameters: WPUParameters = WPUParameters( 265 enWPU = false, 266 algoName = "mmru", 267 isICache = true, 268 ), 269 dwpuParameters: WPUParameters = WPUParameters( 270 enWPU = false, 271 algoName = "mmru", 272 enCfPred = false, 273 isICache = false, 274 ), 275 itlbParameters: TLBParameters = TLBParameters( 276 name = "itlb", 277 fetchi = true, 278 useDmode = false, 279 NWays = 48, 280 ), 281 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 282 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 283 ldtlbParameters: TLBParameters = TLBParameters( 284 name = "ldtlb", 285 NWays = 48, 286 outReplace = false, 287 partialStaticPMP = true, 288 outsideRecvFlush = true, 289 saveLevel = false, 290 lgMaxSize = 4 291 ), 292 sttlbParameters: TLBParameters = TLBParameters( 293 name = "sttlb", 294 NWays = 48, 295 outReplace = false, 296 partialStaticPMP = true, 297 outsideRecvFlush = true, 298 saveLevel = false, 299 lgMaxSize = 4 300 ), 301 hytlbParameters: TLBParameters = TLBParameters( 302 name = "hytlb", 303 NWays = 48, 304 outReplace = false, 305 partialStaticPMP = true, 306 outsideRecvFlush = true, 307 saveLevel = false, 308 lgMaxSize = 4 309 ), 310 pftlbParameters: TLBParameters = TLBParameters( 311 name = "pftlb", 312 NWays = 48, 313 outReplace = false, 314 partialStaticPMP = true, 315 outsideRecvFlush = true, 316 saveLevel = false, 317 lgMaxSize = 4 318 ), 319 l2ToL1tlbParameters: TLBParameters = TLBParameters( 320 name = "l2tlb", 321 NWays = 48, 322 outReplace = false, 323 partialStaticPMP = true, 324 outsideRecvFlush = true, 325 saveLevel = false 326 ), 327 refillBothTlb: Boolean = false, 328 btlbParameters: TLBParameters = TLBParameters( 329 name = "btlb", 330 NWays = 48, 331 ), 332 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 333 NumPerfCounters: Int = 16, 334 icacheParameters: ICacheParameters = ICacheParameters( 335 tagECC = Some("parity"), 336 dataECC = Some("parity"), 337 replacer = Some("setplru"), 338 ), 339 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 340 tagECC = Some("secded"), 341 dataECC = Some("secded"), 342 replacer = Some("setplru"), 343 nMissEntries = 16, 344 nProbeEntries = 8, 345 nReleaseEntries = 18, 346 nMaxPrefetchEntry = 6, 347 )), 348 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 349 name = "l2", 350 ways = 8, 351 sets = 1024, // default 512KB L2 352 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 353 coupledL2.prefetch.TPParameters()), 354 )), 355 L2NBanks: Int = 1, 356 usePTWRepeater: Boolean = false, 357 softTLB: Boolean = false, // dpi-c l1tlb debug only 358 softPTW: Boolean = false, // dpi-c l2tlb debug only 359 softPTWDelay: Int = 1 360){ 361 def vlWidth = log2Up(VLEN) + 1 362 363 /** 364 * the minimum element length of vector elements 365 */ 366 val minVecElen: Int = 8 367 368 /** 369 * the maximum number of elements in vector register 370 */ 371 val maxElemPerVreg: Int = VLEN / minVecElen 372 373 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 374 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 375 376 val RegCacheSize = IntRegCacheSize + MemRegCacheSize 377 val RegCacheIdxWidth = log2Up(RegCacheSize) 378 379 val intSchdParams = { 380 implicit val schdType: SchedulerType = IntScheduler() 381 SchdBlockParams(Seq( 382 IssueBlockParams(Seq( 383 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 384 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1))), true, 2), 385 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 386 IssueBlockParams(Seq( 387 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 388 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1))), true, 2), 389 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 390 IssueBlockParams(Seq( 391 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 392 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = intSchdVlWbPort, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 393 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 394 IssueBlockParams(Seq( 395 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 396 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 397 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 398 ), 399 numPregs = intPreg.numEntries, 400 numDeqOutside = 0, 401 schdType = schdType, 402 rfDataWidth = intPreg.dataCfg.dataWidth, 403 numUopIn = dpParams.IntDqDeqWidth, 404 ) 405 } 406 407 val fpSchdParams = { 408 implicit val schdType: SchedulerType = FpScheduler() 409 SchdBlockParams(Seq( 410 IssueBlockParams(Seq( 411 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 412 ), numEntries = 18, numEnq = 2, numComp = 16), 413 IssueBlockParams(Seq( 414 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 415 ), numEntries = 18, numEnq = 2, numComp = 16), 416 IssueBlockParams(Seq( 417 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 418 ), numEntries = 18, numEnq = 2, numComp = 16), 419 IssueBlockParams(Seq( 420 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 421 ), numEntries = 18, numEnq = 2, numComp = 16), 422 IssueBlockParams(Seq( 423 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 424 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 425 ), numEntries = 18, numEnq = 2, numComp = 16), 426 ), 427 numPregs = fpPreg.numEntries, 428 numDeqOutside = 0, 429 schdType = schdType, 430 rfDataWidth = fpPreg.dataCfg.dataWidth, 431 numUopIn = dpParams.FpDqDeqWidth, 432 ) 433 } 434 435 val vfSchdParams = { 436 implicit val schdType: SchedulerType = VfScheduler() 437 SchdBlockParams(Seq( 438 IssueBlockParams(Seq( 439 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 440 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = vfSchdVlWbPort, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 441 ), numEntries = 16, numEnq = 2, numComp = 14), 442 IssueBlockParams(Seq( 443 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 444 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 445 ), numEntries = 16, numEnq = 2, numComp = 14), 446 IssueBlockParams(Seq( 447 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 448 ), numEntries = 10, numEnq = 2, numComp = 8), 449 ), 450 numPregs = vfPreg.numEntries, 451 numDeqOutside = 0, 452 schdType = schdType, 453 rfDataWidth = vfPreg.dataCfg.dataWidth, 454 numUopIn = dpParams.VecDqDeqWidth, 455 ) 456 } 457 458 val memSchdParams = { 459 implicit val schdType: SchedulerType = MemScheduler() 460 val rfDataWidth = 64 461 462 SchdBlockParams(Seq( 463 IssueBlockParams(Seq( 464 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))), 465 ), numEntries = 16, numEnq = 1, numComp = 15), 466 IssueBlockParams(Seq( 467 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))), 468 ), numEntries = 16, numEnq = 1, numComp = 15), 469 IssueBlockParams(Seq( 470 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(8, 0))), true, 2), 471 ), numEntries = 16, numEnq = 1, numComp = 15), 472 IssueBlockParams(Seq( 473 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(9, 0))), true, 2), 474 ), numEntries = 16, numEnq = 1, numComp = 15), 475 IssueBlockParams(Seq( 476 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(10, 0))), true, 2), 477 ), numEntries = 16, numEnq = 1, numComp = 15), 478 IssueBlockParams(Seq( 479 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0), VlWB(port = 2, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 480 ), numEntries = 16, numEnq = 1, numComp = 15), 481 IssueBlockParams(Seq( 482 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0), VlWB(port = 3, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 483 ), numEntries = 16, numEnq = 1, numComp = 15), 484 IssueBlockParams(Seq( 485 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(12, 0)))), 486 ), numEntries = 16, numEnq = 1, numComp = 15), 487 IssueBlockParams(Seq( 488 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(13, 0)))), 489 ), numEntries = 16, numEnq = 1, numComp = 15), 490 ), 491 numPregs = intPreg.numEntries max vfPreg.numEntries, 492 numDeqOutside = 0, 493 schdType = schdType, 494 rfDataWidth = rfDataWidth, 495 numUopIn = dpParams.LsDqDeqWidth, 496 ) 497 } 498 499 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 500 501 def iqWakeUpParams = { 502 Seq( 503 WakeUpConfig( 504 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 505 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 506 ), 507 // TODO: add load -> fp slow wakeup 508 WakeUpConfig( 509 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 510 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 511 ), 512 WakeUpConfig( 513 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 514 Seq("STD0", "STD1") 515 ), 516// WakeUpConfig( 517// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 518// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") 519// ), 520 ).flatten 521 } 522 523 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 524 525 val backendParams: BackendParams = backend.BackendParams( 526 Map( 527 IntScheduler() -> intSchdParams, 528 FpScheduler() -> fpSchdParams, 529 VfScheduler() -> vfSchdParams, 530 MemScheduler() -> memSchdParams, 531 ), 532 Seq( 533 intPreg, 534 fpPreg, 535 vfPreg, 536 v0Preg, 537 vlPreg, 538 fakeIntPreg 539 ), 540 iqWakeUpParams, 541 ) 542 543 // Parameters for trace extension. 544 // Trace parameters is useful for XSTOP. 545 val TraceGroupNum = 3 // Width to Encoder 546} 547 548case object DebugOptionsKey extends Field[DebugOptions] 549 550case class DebugOptions 551( 552 FPGAPlatform: Boolean = false, 553 ResetGen: Boolean = false, 554 EnableDifftest: Boolean = false, 555 AlwaysBasicDiff: Boolean = true, 556 EnableDebug: Boolean = false, 557 EnablePerfDebug: Boolean = true, 558 UseDRAMSim: Boolean = false, 559 EnableConstantin: Boolean = false, 560 EnableChiselDB: Boolean = false, 561 AlwaysBasicDB: Boolean = true, 562 EnableRollingDB: Boolean = false 563) 564 565trait HasXSParameter { 566 567 implicit val p: Parameters 568 569 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 570 def PmemRanges = p(SoCParamsKey).PmemRanges 571 def PmemLowBounds = PmemRanges.unzip._1 572 def PmemHighBounds = PmemRanges.unzip._2 573 final val PageOffsetWidth = 12 574 def NodeIDWidth = p(SoCParamsKey).NodeIDWidthList(p(CHIIssue)) // NodeID width among NoC 575 576 def coreParams = p(XSCoreParamsKey) 577 def env = p(DebugOptionsKey) 578 579 def XLEN = coreParams.XLEN 580 def VLEN = coreParams.VLEN 581 def ELEN = coreParams.ELEN 582 def HSXLEN = coreParams.HSXLEN 583 val minFLen = 32 584 val fLen = 64 585 def hartIdLen = p(MaxHartIdBits) 586 val xLen = XLEN 587 588 def HasMExtension = coreParams.HasMExtension 589 def HasCExtension = coreParams.HasCExtension 590 def HasHExtension = coreParams.HasHExtension 591 def EnableSv48 = coreParams.EnableSv48 592 def HasDiv = coreParams.HasDiv 593 def HasIcache = coreParams.HasICache 594 def HasDcache = coreParams.HasDCache 595 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 596 def GPAddrBitsSv39x4 = coreParams.GPAddrBitsSv39x4 597 def GPAddrBitsSv48x4 = coreParams.GPAddrBitsSv48x4 598 def GPAddrBits = { 599 if (EnableSv48) 600 coreParams.GPAddrBitsSv48x4 601 else 602 coreParams.GPAddrBitsSv39x4 603 } 604 def VAddrBits = { 605 if (HasHExtension) { 606 if (EnableSv48) 607 coreParams.GPAddrBitsSv48x4 608 else 609 coreParams.GPAddrBitsSv39x4 610 } else { 611 if (EnableSv48) 612 coreParams.VAddrBitsSv48 613 else 614 coreParams.VAddrBitsSv39 615 } 616 } // VAddrBits is Virtual Memory addr bits 617 618 def VAddrMaxBits = { 619 if(EnableSv48) { 620 coreParams.VAddrBitsSv48 max coreParams.GPAddrBitsSv48x4 621 } else { 622 coreParams.VAddrBitsSv39 max coreParams.GPAddrBitsSv39x4 623 } 624 } 625 626 def AsidLength = coreParams.AsidLength 627 def VmidLength = coreParams.VmidLength 628 def ReSelectLen = coreParams.ReSelectLen 629 def AddrBytes = AddrBits / 8 // unused 630 def DataBits = XLEN 631 def DataBytes = DataBits / 8 632 def VDataBytes = VLEN / 8 633 def HasFPU = coreParams.HasFPU 634 def HasVPU = coreParams.HasVPU 635 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 636 def FetchWidth = coreParams.FetchWidth 637 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 638 def EnableBPU = coreParams.EnableBPU 639 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 640 def EnableRAS = coreParams.EnableRAS 641 def EnableLB = coreParams.EnableLB 642 def EnableLoop = coreParams.EnableLoop 643 def EnableSC = coreParams.EnableSC 644 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 645 def HistoryLength = coreParams.HistoryLength 646 def EnableGHistDiff = coreParams.EnableGHistDiff 647 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 648 def EnableClockGate = coreParams.EnableClockGate 649 def UbtbGHRLength = coreParams.UbtbGHRLength 650 def UbtbSize = coreParams.UbtbSize 651 def EnableFauFTB = coreParams.EnableFauFTB 652 def FtbSize = coreParams.FtbSize 653 def FtbWays = coreParams.FtbWays 654 def FtbTagLength = coreParams.FtbTagLength 655 def RasSize = coreParams.RasSize 656 def RasSpecSize = coreParams.RasSpecSize 657 def RasCtrSize = coreParams.RasCtrSize 658 659 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 660 coreParams.branchPredictor(resp_in, p) 661 } 662 def numBr = coreParams.numBr 663 def TageTableInfos = coreParams.TageTableInfos 664 def TageBanks = coreParams.numBr 665 def SCNRows = coreParams.SCNRows 666 def SCCtrBits = coreParams.SCCtrBits 667 def SCHistLens = coreParams.SCHistLens 668 def SCNTables = coreParams.SCNTables 669 670 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 671 case ((n, cb), h) => (n, cb, h) 672 } 673 def ITTageTableInfos = coreParams.ITTageTableInfos 674 type FoldedHistoryInfo = Tuple2[Int, Int] 675 def foldedGHistInfos = 676 (TageTableInfos.map{ case (nRows, h, t) => 677 if (h > 0) 678 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 679 else 680 Set[FoldedHistoryInfo]() 681 }.reduce(_++_).toSet ++ 682 SCTableInfos.map{ case (nRows, _, h) => 683 if (h > 0) 684 Set((h, min(log2Ceil(nRows/TageBanks), h))) 685 else 686 Set[FoldedHistoryInfo]() 687 }.reduce(_++_).toSet ++ 688 ITTageTableInfos.map{ case (nRows, h, t) => 689 if (h > 0) 690 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 691 else 692 Set[FoldedHistoryInfo]() 693 }.reduce(_++_) ++ 694 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 695 ).toList 696 697 698 699 def CacheLineSize = coreParams.CacheLineSize 700 def CacheLineHalfWord = CacheLineSize / 16 701 def ExtHistoryLength = HistoryLength + 64 702 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 703 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 704 def IBufSize = coreParams.IBufSize 705 def IBufNBank = coreParams.IBufNBank 706 def backendParams: BackendParams = coreParams.backendParams 707 def DecodeWidth = coreParams.DecodeWidth 708 def RenameWidth = coreParams.RenameWidth 709 def CommitWidth = coreParams.CommitWidth 710 def RobCommitWidth = coreParams.RobCommitWidth 711 def RabCommitWidth = coreParams.RabCommitWidth 712 def MaxUopSize = coreParams.MaxUopSize 713 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 714 def RenameSnapshotNum = coreParams.RenameSnapshotNum 715 def FtqSize = coreParams.FtqSize 716 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 717 def IntLogicRegs = coreParams.IntLogicRegs 718 def FpLogicRegs = coreParams.FpLogicRegs 719 def VecLogicRegs = coreParams.VecLogicRegs 720 def V0LogicRegs = coreParams.V0LogicRegs 721 def VlLogicRegs = coreParams.VlLogicRegs 722 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 723 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 724 def V0_IDX = coreParams.V0_IDX 725 def Vl_IDX = coreParams.Vl_IDX 726 def IntPhyRegs = coreParams.intPreg.numEntries 727 def FpPhyRegs = coreParams.fpPreg.numEntries 728 def VfPhyRegs = coreParams.vfPreg.numEntries 729 def V0PhyRegs = coreParams.v0Preg.numEntries 730 def VlPhyRegs = coreParams.vlPreg.numEntries 731 def MaxPhyRegs = Seq(IntPhyRegs, FpPhyRegs, VfPhyRegs, V0PhyRegs, VlPhyRegs).max 732 def IntPhyRegIdxWidth = log2Up(IntPhyRegs) 733 def FpPhyRegIdxWidth = log2Up(FpPhyRegs) 734 def VfPhyRegIdxWidth = log2Up(VfPhyRegs) 735 def V0PhyRegIdxWidth = log2Up(V0PhyRegs) 736 def VlPhyRegIdxWidth = log2Up(VlPhyRegs) 737 def PhyRegIdxWidth = Seq(IntPhyRegIdxWidth, FpPhyRegIdxWidth, VfPhyRegIdxWidth, V0PhyRegIdxWidth, VlPhyRegIdxWidth).max 738 def RobSize = coreParams.RobSize 739 def RabSize = coreParams.RabSize 740 def VTypeBufferSize = coreParams.VTypeBufferSize 741 def IntRegCacheSize = coreParams.IntRegCacheSize 742 def MemRegCacheSize = coreParams.MemRegCacheSize 743 def RegCacheSize = coreParams.RegCacheSize 744 def RegCacheIdxWidth = coreParams.RegCacheIdxWidth 745 /** 746 * the minimum element length of vector elements 747 */ 748 def minVecElen: Int = coreParams.minVecElen 749 750 /** 751 * the maximum number of elements in vector register 752 */ 753 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 754 755 def IntRefCounterWidth = log2Ceil(RobSize) 756 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 757 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 758 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 759 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 760 def LoadQueueRARSize = coreParams.LoadQueueRARSize 761 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 762 def RollbackGroupSize = coreParams.RollbackGroupSize 763 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 764 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 765 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 766 def StoreQueueSize = coreParams.StoreQueueSize 767 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 768 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 769 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 770 def VlsQueueSize = coreParams.VlsQueueSize 771 def dpParams = coreParams.dpParams 772 773 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 774 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 775 776 def NumRedirect = backendParams.numRedirect 777 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 778 def FtqRedirectAheadNum = NumRedirect 779 def IfuRedirectNum = coreParams.IfuRedirectNum 780 def LoadPipelineWidth = coreParams.LoadPipelineWidth 781 def StorePipelineWidth = coreParams.StorePipelineWidth 782 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 783 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 784 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 785 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 786 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 787 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 788 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 789 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 790 def StoreBufferSize = coreParams.StoreBufferSize 791 def StoreBufferThreshold = coreParams.StoreBufferThreshold 792 def EnsbufferWidth = coreParams.EnsbufferWidth 793 def LoadDependencyWidth = coreParams.LoadDependencyWidth 794 def VlMergeBufferSize = coreParams.VlMergeBufferSize 795 def VsMergeBufferSize = coreParams.VsMergeBufferSize 796 def UopWritebackWidth = coreParams.UopWritebackWidth 797 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 798 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 799 def VSegmentBufferSize = coreParams.VSegmentBufferSize 800 def VFOFBufferSize = coreParams.VFOFBufferSize 801 def UncacheBufferSize = coreParams.UncacheBufferSize 802 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 803 def EnableFastForward = coreParams.EnableFastForward 804 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 805 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 806 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 807 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 808 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 809 def EnableHardwareStoreMisalign = coreParams.EnableHardwareStoreMisalign 810 def EnableHardwareLoadMisalign = coreParams.EnableHardwareLoadMisalign 811 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 812 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 813 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 814 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 815 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 816 def HasCMO = coreParams.HasCMO && p(EnableCHI) 817 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 818 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 819 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 820 def asidLen = coreParams.MMUAsidLen 821 def vmidLen = coreParams.MMUVmidLen 822 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 823 def refillBothTlb = coreParams.refillBothTlb 824 def iwpuParam = coreParams.iwpuParameters 825 def dwpuParam = coreParams.dwpuParameters 826 def itlbParams = coreParams.itlbParameters 827 def ldtlbParams = coreParams.ldtlbParameters 828 def sttlbParams = coreParams.sttlbParameters 829 def hytlbParams = coreParams.hytlbParameters 830 def pftlbParams = coreParams.pftlbParameters 831 def l2ToL1Params = coreParams.l2ToL1tlbParameters 832 def btlbParams = coreParams.btlbParameters 833 def l2tlbParams = coreParams.l2tlbParameters 834 def NumPerfCounters = coreParams.NumPerfCounters 835 836 def instBytes = if (HasCExtension) 2 else 4 837 def instOffsetBits = log2Ceil(instBytes) 838 839 def icacheParameters = coreParams.icacheParameters 840 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 841 842 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 843 // for constrained LR/SC loop 844 def LRSCCycles = 64 845 // for lr storm 846 def LRSCBackOff = 8 847 848 // cache hierarchy configurations 849 def l1BusDataWidth = 256 850 851 // load violation predict 852 def ResetTimeMax2Pow = 20 //1078576 853 def ResetTimeMin2Pow = 10 //1024 854 // wait table parameters 855 def WaitTableSize = 1024 856 def MemPredPCWidth = log2Up(WaitTableSize) 857 def LWTUse2BitCounter = true 858 // store set parameters 859 def SSITSize = WaitTableSize 860 def LFSTSize = 32 861 def SSIDWidth = log2Up(LFSTSize) 862 def LFSTWidth = 4 863 def StoreSetEnable = true // LWT will be disabled if SS is enabled 864 def LFSTEnable = true 865 866 def PCntIncrStep: Int = 6 867 def numPCntHc: Int = 12 868 def numPCntPtw: Int = 19 869 870 def numCSRPCntFrontend = 8 871 def numCSRPCntCtrl = 8 872 def numCSRPCntLsu = 8 873 def numCSRPCntHc = 5 874 def printEventCoding = true 875 def printCriticalError = false 876 def maxCommitStuck = pow(2, 21).toInt 877 878 // Vector load exception 879 def maxMergeNumPerCycle = 4 880 881 // Parameters for Sdtrig extension 882 protected def TriggerNum = 4 883 protected def TriggerChainMaxLength = 2 884 885 // Parameters for Trace extension 886 def TraceGroupNum = coreParams.TraceGroupNum 887} 888