1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.ExceptionNO._ 14import xiangshan.backend.Bundles.TrapInstInfo 15import xiangshan.backend.decode.Imm_Z 16import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 17import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 18import xiangshan.frontend.FtqPtr 19 20class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 21 with HasCircularQueuePtrHelper with HasCriticalErrors 22{ 23 val csrIn = io.csrio.get 24 val csrOut = io.csrio.get 25 val csrToDecode = io.csrToDecode.get 26 27 val setFsDirty = csrIn.fpu.dirty_fs 28 val setFflags = csrIn.fpu.fflags 29 30 val setVsDirty = csrIn.vpu.dirty_vs 31 val setVstart = csrIn.vpu.set_vstart 32 val setVtype = csrIn.vpu.set_vtype 33 val setVxsat = csrIn.vpu.set_vxsat 34 val vlFromPreg = csrIn.vpu.vl 35 36 val flushPipe = Wire(Bool()) 37 val flush = io.flush.valid 38 39 /** Alias of input signals */ 40 val (valid, src1, imm, func) = ( 41 io.in.valid, 42 io.in.bits.data.src(0), 43 io.in.bits.data.imm(Imm_Z().len - 1, 0), 44 io.in.bits.ctrl.fuOpType 45 ) 46 47 // split imm/src1/rd from IMM_Z: src1/rd for tval 48 val addr = Imm_Z().getCSRAddr(imm) 49 val rd = Imm_Z().getRD(imm) 50 val rs1 = Imm_Z().getRS1(imm) 51 val imm5 = Imm_Z().getImm5(imm) 52 val csri = ZeroExt(imm5, XLEN) 53 54 import CSRConst._ 55 56 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 57 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 58 private val isMNret = CSROpType.isSystemOp(func) && addr === privMNret 59 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 60 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 61 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 62 private val isWfi = CSROpType.isWfi(func) 63 private val isCSRAcc = CSROpType.isCsrAccess(func) 64 65 val csrMod = Module(new NewCSR) 66 val trapInstMod = Module(new TrapInstMod) 67 val trapTvalMod = Module(new TrapTvalMod) 68 69 private val privState = csrMod.io.status.privState 70 // The real reg value in CSR, with no read mask 71 private val regOut = csrMod.io.out.bits.regOut 72 private val src = Mux(CSROpType.needImm(func), csri, src1) 73 private val wdata = LookupTree(func, Seq( 74 CSROpType.wrt -> src1, 75 CSROpType.set -> (regOut | src1), 76 CSROpType.clr -> (regOut & (~src1).asUInt), 77 CSROpType.wrti -> csri, 78 CSROpType.seti -> (regOut | csri), 79 CSROpType.clri -> (regOut & (~csri).asUInt), 80 )) 81 82 private val csrAccess = valid && CSROpType.isCsrAccess(func) 83 private val csrWen = valid && ( 84 CSROpType.isCSRRW(func) || 85 CSROpType.isCSRRSorRC(func) && rs1 =/= 0.U 86 ) 87 private val csrRen = valid && ( 88 CSROpType.isCSRRW(func) && rd =/= 0.U || 89 CSROpType.isCSRRSorRC(func) 90 ) 91 92 csrMod.io.in match { 93 case in => 94 in.valid := valid 95 in.bits.wen := csrWen 96 in.bits.ren := csrRen 97 in.bits.op := CSROpType.getCSROp(func) 98 in.bits.addr := addr 99 in.bits.src := src 100 in.bits.wdata := wdata 101 in.bits.mret := isMret 102 in.bits.mnret := isMNret 103 in.bits.sret := isSret 104 in.bits.dret := isDret 105 } 106 csrMod.io.trapInst := trapInstMod.io.currentTrapInst 107 csrMod.io.fetchMalTval := trapTvalMod.io.tval 108 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 109 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 110 csrMod.io.fromMem.excpIsForVSnonLeafPTE := csrIn.memExceptionIsForVSnonLeafPTE 111 112 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 113 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 114 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 115 csrMod.io.fromRob.trap.bits.pcGPA := csrIn.exception.bits.gpaddr 116 // Todo: shrink the width of trap vector. 117 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 118 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 119 csrMod.io.fromRob.trap.bits.isFetchBkpt := csrIn.exception.bits.isPcBkpt 120 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 121 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 122 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 123 csrMod.io.fromRob.trap.bits.trigger := csrIn.exception.bits.trigger 124 csrMod.io.fromRob.trap.bits.isHls := csrIn.exception.bits.isHls 125 csrMod.io.fromRob.trap.bits.isFetchMalAddr := csrIn.exception.bits.isFetchMalAddr 126 csrMod.io.fromRob.trap.bits.isForVSnonLeafPTE := csrIn.exception.bits.isForVSnonLeafPTE 127 128 csrMod.io.fromRob.commit.fflags := setFflags 129 csrMod.io.fromRob.commit.fsDirty := setFsDirty 130 csrMod.io.fromRob.commit.vxsat.valid := setVxsat.valid 131 csrMod.io.fromRob.commit.vxsat.bits := setVxsat.bits 132 csrMod.io.fromRob.commit.vsDirty := setVsDirty 133 csrMod.io.fromRob.commit.vstart := setVstart 134 csrMod.io.fromRob.commit.vl := vlFromPreg 135 // Todo: correct vtype 136 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 137 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 138 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 139 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 140 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 141 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 142 143 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 144 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 145 146 csrMod.io.fromRob.robDeqPtr := csrIn.robDeqPtr 147 148 csrMod.io.fromVecExcpMod.busy := io.csrin.get.fromVecExcpMod.busy 149 150 csrMod.io.perf := csrIn.perf 151 152 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 153 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 154 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 155 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 156 csrMod.platformIRP.STIP := false.B 157 csrMod.platformIRP.VSEIP := false.B // Todo 158 csrMod.platformIRP.VSTIP := false.B // Todo 159 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 160 csrMod.nonMaskableIRP.NMI_43 := csrIn.externalInterrupt.nmi.nmi_43 161 csrMod.nonMaskableIRP.NMI_31 := csrIn.externalInterrupt.nmi.nmi_31 162 163 csrMod.io.fromTop.hartId := io.csrin.get.hartId 164 csrMod.io.fromTop.clintTime := io.csrin.get.clintTime 165 csrMod.io.fromTop.criticalErrorState := io.csrin.get.criticalErrorState 166 private val csrModOutValid = csrMod.io.out.valid 167 private val csrModOut = csrMod.io.out.bits 168 169 trapInstMod.io.fromDecode.trapInstInfo := RegNextWithEnable(io.csrin.get.trapInstInfo, hasInit = true) 170 trapInstMod.io.fromRob.flush.valid := io.flush.valid 171 trapInstMod.io.fromRob.flush.bits.ftqPtr := io.flush.bits.ftqIdx 172 trapInstMod.io.fromRob.flush.bits.ftqOffset := io.flush.bits.ftqOffset 173 trapInstMod.io.faultCsrUop.valid := csrMod.io.out.valid && (csrMod.io.out.bits.EX_II || csrMod.io.out.bits.EX_VI) 174 trapInstMod.io.faultCsrUop.bits.fuOpType := DataHoldBypass(io.in.bits.ctrl.fuOpType, io.in.fire) 175 trapInstMod.io.faultCsrUop.bits.imm := DataHoldBypass(io.in.bits.data.imm, io.in.fire) 176 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqPtr := DataHoldBypass(io.in.bits.ctrl.ftqIdx.get, io.in.fire) 177 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqOffset := DataHoldBypass(io.in.bits.ctrl.ftqOffset.get, io.in.fire) 178 // Clear trap instruction when instruction fault trap(EX_II, EX_VI) occurs. 179 trapInstMod.io.readClear := (csrMod.io.fromRob.trap match { 180 case t => 181 t.valid && !t.bits.isInterrupt && (t.bits.trapVec(EX_II) || t.bits.trapVec(EX_VI)) 182 }) 183 184 trapTvalMod.io.targetPc.valid := csrMod.io.out.bits.targetPcUpdate 185 trapTvalMod.io.targetPc.bits := csrMod.io.out.bits.targetPc 186 trapTvalMod.io.clear := csrIn.exception.valid && csrIn.exception.bits.isFetchMalAddr 187 trapTvalMod.io.fromCtrlBlock.flush := io.flush 188 trapTvalMod.io.fromCtrlBlock.robDeqPtr := io.csrio.get.robDeqPtr 189 190 private val imsic = Module(new IMSIC(NumVSIRFiles = 5, NumHart = 1, XLEN = 64, NumIRSrc = 256)) 191 imsic.i.hartId := io.csrin.get.hartId 192 imsic.i.msiInfo := io.csrin.get.msiInfo 193 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 194 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 195 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 196 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 197 imsic.i.csr.vgein := csrMod.toAIA.vgein 198 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 199 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 200 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 201 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 202 imsic.i.csr.wdata.bits.op := csrMod.toAIA.wdata.bits.op 203 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 204 205 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 206 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 207 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 208 csrMod.fromAIA.meip := imsic.o.meip 209 csrMod.fromAIA.seip := imsic.o.seip 210 csrMod.fromAIA.vseip := imsic.o.vseip 211 csrMod.fromAIA.mtopei := imsic.o.mtopei 212 csrMod.fromAIA.stopei := imsic.o.stopei 213 csrMod.fromAIA.vstopei := imsic.o.vstopei 214 215 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 216 217 exceptionVec(EX_BP ) := DataHoldBypass(isEbreak, false.B, io.in.fire) 218 exceptionVec(EX_MCALL ) := DataHoldBypass(isEcall && privState.isModeM, false.B, io.in.fire) 219 exceptionVec(EX_HSCALL) := DataHoldBypass(isEcall && privState.isModeHS, false.B, io.in.fire) 220 exceptionVec(EX_VSCALL) := DataHoldBypass(isEcall && privState.isModeVS, false.B, io.in.fire) 221 exceptionVec(EX_UCALL ) := DataHoldBypass(isEcall && privState.isModeHUorVU, false.B, io.in.fire) 222 exceptionVec(EX_II ) := csrMod.io.out.bits.EX_II 223 exceptionVec(EX_VI ) := csrMod.io.out.bits.EX_VI 224 225 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 226 227 // ctrl block will use theses later for flush // Todo: optimize isXRetFlag's DelayN 228 val isXRetFlag = RegInit(false.B) 229 isXRetFlag := Mux1H(Seq( 230 DelayN(flush, 5) -> false.B, 231 isXRet -> true.B, 232 )) 233 234 flushPipe := csrMod.io.out.bits.flushPipe 235 236 // tlb 237 val tlb = Wire(new TlbCsrBundle) 238 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 239 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 240 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 241 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 242 tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged 243 tlb.vsatp.mode := csrMod.io.tlb.vsatp.MODE.asUInt 244 tlb.vsatp.asid := csrMod.io.tlb.vsatp.ASID.asUInt 245 tlb.vsatp.ppn := csrMod.io.tlb.vsatp.PPN.asUInt 246 tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged 247 tlb.hgatp.mode := csrMod.io.tlb.hgatp.MODE.asUInt 248 tlb.hgatp.vmid := csrMod.io.tlb.hgatp.VMID.asUInt 249 tlb.hgatp.ppn := csrMod.io.tlb.hgatp.PPN.asUInt 250 251 // expose several csr bits for tlb 252 tlb.priv.mxr := csrMod.io.tlb.mxr 253 tlb.priv.sum := csrMod.io.tlb.sum 254 tlb.priv.vmxr := csrMod.io.tlb.vmxr 255 tlb.priv.vsum := csrMod.io.tlb.vsum 256 tlb.priv.spvp := csrMod.io.tlb.spvp 257 tlb.priv.virt := csrMod.io.tlb.dvirt 258 tlb.priv.imode := csrMod.io.tlb.imode 259 tlb.priv.dmode := csrMod.io.tlb.dmode 260 261 // Svpbmt extension enable 262 tlb.mPBMTE := csrMod.io.tlb.mPBMTE 263 tlb.hPBMTE := csrMod.io.tlb.hPBMTE 264 265 /** Since some CSR read instructions are allowed to be pipelined, ready/valid signals should be modified */ 266 io.in.ready := csrMod.io.in.ready // Todo: Async read imsic may block CSR 267 io.out.valid := csrModOutValid 268 io.out.bits.ctrl.exceptionVec.get := exceptionVec 269 io.out.bits.ctrl.flushPipe.get := flushPipe 270 io.out.bits.res.data := csrMod.io.out.bits.rData 271 272 /** initialize NewCSR's io_out_ready from wrapper's io */ 273 csrMod.io.out.ready := io.out.ready 274 275 io.out.bits.res.redirect.get.valid := io.out.valid && DataHoldBypass(isXRet, false.B, io.in.fire) 276 val redirect = io.out.bits.res.redirect.get.bits 277 redirect := 0.U.asTypeOf(redirect) 278 redirect.level := RedirectLevel.flushAfter 279 redirect.robIdx := io.in.bits.ctrl.robIdx 280 redirect.ftqIdx := io.in.bits.ctrl.ftqIdx.get 281 redirect.ftqOffset := io.in.bits.ctrl.ftqOffset.get 282 redirect.cfiUpdate.predTaken := true.B 283 redirect.cfiUpdate.taken := true.B 284 redirect.cfiUpdate.target := csrMod.io.out.bits.targetPc.pc 285 redirect.cfiUpdate.backendIPF := csrMod.io.out.bits.targetPc.raiseIPF 286 redirect.cfiUpdate.backendIAF := csrMod.io.out.bits.targetPc.raiseIAF 287 redirect.cfiUpdate.backendIGPF := csrMod.io.out.bits.targetPc.raiseIGPF 288 // Only mispred will send redirect to frontend 289 redirect.cfiUpdate.isMisPred := true.B 290 291 connectNonPipedCtrlSingalForCSR 292 293 override val criticalErrors = csrMod.getCriticalErrors 294 generateCriticalErrors() 295 296 // Todo: summerize all difftest skip condition 297 csrOut.isPerfCnt := io.out.valid && csrMod.io.out.bits.isPerfCnt && DataHoldBypass(func =/= CSROpType.jmp, false.B, io.in.fire) 298 csrOut.fpu.frm := csrMod.io.status.fpState.frm.asUInt 299 csrOut.vpu.vstart := csrMod.io.status.vecState.vstart.asUInt 300 csrOut.vpu.vxrm := csrMod.io.status.vecState.vxrm.asUInt 301 302 csrOut.isXRet := isXRetFlag 303 304 csrOut.trapTarget := csrMod.io.out.bits.targetPc 305 csrOut.interrupt := csrMod.io.status.interrupt 306 csrOut.wfi_event := csrMod.io.status.wfiEvent 307 308 csrOut.tlb := tlb 309 310 csrOut.debugMode := csrMod.io.status.debugMode 311 312 csrOut.customCtrl match { 313 case custom => 314 custom.l1I_pf_enable := csrMod.io.status.custom.l1I_pf_enable 315 custom.l2_pf_enable := csrMod.io.status.custom.l2_pf_enable 316 custom.l1D_pf_enable := csrMod.io.status.custom.l1D_pf_enable 317 custom.l1D_pf_train_on_hit := csrMod.io.status.custom.l1D_pf_train_on_hit 318 custom.l1D_pf_enable_agt := csrMod.io.status.custom.l1D_pf_enable_agt 319 custom.l1D_pf_enable_pht := csrMod.io.status.custom.l1D_pf_enable_pht 320 custom.l1D_pf_active_threshold := csrMod.io.status.custom.l1D_pf_active_threshold 321 custom.l1D_pf_active_stride := csrMod.io.status.custom.l1D_pf_active_stride 322 custom.l1D_pf_enable_stride := csrMod.io.status.custom.l1D_pf_enable_stride 323 custom.l2_pf_store_only := csrMod.io.status.custom.l2_pf_store_only 324 // ICache 325 custom.icache_parity_enable := csrMod.io.status.custom.icache_parity_enable 326 // Load violation predictor 327 custom.lvpred_disable := csrMod.io.status.custom.lvpred_disable 328 custom.no_spec_load := csrMod.io.status.custom.no_spec_load 329 custom.storeset_wait_store := csrMod.io.status.custom.storeset_wait_store 330 custom.storeset_no_fast_wakeup := csrMod.io.status.custom.storeset_no_fast_wakeup 331 custom.lvpred_timeout := csrMod.io.status.custom.lvpred_timeout 332 // Branch predictor 333 custom.bp_ctrl := csrMod.io.status.custom.bp_ctrl 334 // Memory Block 335 custom.sbuffer_threshold := csrMod.io.status.custom.sbuffer_threshold 336 custom.ldld_vio_check_enable := csrMod.io.status.custom.ldld_vio_check_enable 337 custom.soft_prefetch_enable := csrMod.io.status.custom.soft_prefetch_enable 338 custom.cache_error_enable := csrMod.io.status.custom.cache_error_enable 339 custom.uncache_write_outstanding_enable := csrMod.io.status.custom.uncache_write_outstanding_enable 340 custom.hd_misalign_st_enable := csrMod.io.status.custom.hd_misalign_st_enable 341 custom.hd_misalign_ld_enable := csrMod.io.status.custom.hd_misalign_ld_enable 342 // Rename 343 custom.fusion_enable := csrMod.io.status.custom.fusion_enable 344 custom.wfi_enable := csrMod.io.status.custom.wfi_enable 345 // distribute csr write signal 346 // write to frontend and memory 347 custom.distribute_csr.w.valid := csrMod.io.distributedWenLegal 348 custom.distribute_csr.w.bits.addr := addr 349 custom.distribute_csr.w.bits.data := wdata 350 // rename single step 351 custom.singlestep := csrMod.io.status.singleStepFlag 352 // trigger 353 custom.frontend_trigger := csrMod.io.status.frontendTrigger 354 custom.mem_trigger := csrMod.io.status.memTrigger 355 // virtual mode 356 custom.virtMode := csrMod.io.status.privState.V.asBool 357 // xstatus.fs field is off 358 custom.fsIsOff := csrMod.io.toDecode.illegalInst.fsIsOff 359 } 360 361 csrOut.instrAddrTransType := csrMod.io.status.instrAddrTransType 362 csrOut.criticalErrorState := csrMod.io.status.criticalErrorState 363 364 csrToDecode := csrMod.io.toDecode 365} 366 367class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 368 val hartId = Input(UInt(8.W)) 369 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 370 val criticalErrorState = Input(Bool()) 371 val clintTime = Input(ValidIO(UInt(64.W))) 372 val trapInstInfo = Input(ValidIO(new TrapInstInfo)) 373 val fromVecExcpMod = Input(new Bundle { 374 val busy = Bool() 375 }) 376} 377 378class CSRToDecode(implicit p: Parameters) extends XSBundle { 379 val illegalInst = new Bundle { 380 /** 381 * illegal sfence.vma, sinval.vma 382 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 383 */ 384 val sfenceVMA = Bool() 385 386 /** 387 * illegal sfence.w.inval sfence.inval.ir 388 * raise EX_II when isModeHU 389 */ 390 val sfencePart = Bool() 391 392 /** 393 * illegal hfence.gvma, hinval.gvma 394 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 395 * the condition is the same as sfenceVMA 396 */ 397 val hfenceGVMA = Bool() 398 399 /** 400 * illegal hfence.vvma, hinval.vvma 401 * raise EX_II when isModeHU 402 */ 403 val hfenceVVMA = Bool() 404 405 /** 406 * illegal hlv, hlvx, and hsv 407 * raise EX_II when isModeHU && hstatus.HU=0 408 */ 409 val hlsv = Bool() 410 411 /** 412 * decode all fp inst or all vecfp inst 413 * raise EX_II when FS=Off 414 */ 415 val fsIsOff = Bool() 416 417 /** 418 * decode all vec inst 419 * raise EX_II when VS=Off 420 */ 421 val vsIsOff = Bool() 422 423 /** 424 * illegal wfi 425 * raise EX_II when isModeHU || !isModeM && mstatus.TW=1 426 */ 427 val wfi = Bool() 428 429 /** 430 * frm reserved 431 * raise EX_II when frm.data > 4 432 */ 433 val frm = Bool() 434 435 /** 436 * illegal CBO.ZERO 437 * raise [[EX_II]] when !isModeM && !MEnvCfg.CBZE || isModeHU && !SEnvCfg.CBZE 438 */ 439 val cboZ = Bool() 440 441 /** 442 * illegal CBO.CLEAN/FLUSH 443 * raise [[EX_II]] when !isModeM && !MEnvCfg.CBCFE || isModeHU && !SEnvCfg.CBCFE 444 */ 445 val cboCF = Bool() 446 447 /** 448 * illegal CBO.INVAL 449 * raise [[EX_II]] when !isModeM && MEnvCfg.CBIE = EnvCBIE.Off || isModeHU && SEnvCfg.CBIE = EnvCBIE.Off 450 */ 451 val cboI = Bool() 452 } 453 454 val virtualInst = new Bundle { 455 /** 456 * illegal sfence.vma, svinval.vma 457 * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU 458 */ 459 val sfenceVMA = Bool() 460 461 /** 462 * illegal sfence.w.inval sfence.inval.ir 463 * raise EX_VI when isModeVU 464 */ 465 val sfencePart = Bool() 466 467 /** 468 * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma 469 * raise EX_VI when isModeVS || isModeVU 470 */ 471 val hfence = Bool() 472 473 /** 474 * illegal hlv, hlvx, and hsv 475 * raise EX_VI when isModeVS || isModeVU 476 */ 477 val hlsv = Bool() 478 479 /** 480 * illegal wfi 481 * raise EX_VI when isModeVU && mstatus.TW=0 || isModeVS && mstatus.TW=0 && hstatus.VTW=1 482 */ 483 val wfi = Bool() 484 485 /** 486 * illegal CBO.ZERO 487 * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBZE || isModeVU && (!HEnvCfg.CBZE || !SEnvCfg.CBZE)) 488 */ 489 val cboZ = Bool() 490 491 /** 492 * illegal CBO.CLEAN/FLUSH 493 * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBCFE || isModeVU && (!HEnvCfg.CBCFE || !SEnvCfg.CBCFE)) 494 */ 495 val cboCF = Bool() 496 497 /** 498 * illegal CBO.INVAL <br/> 499 * raise [[EX_VI]] when MEnvCfg.CBIE =/= EnvCBIE.Off && ( <br/> 500 * isModeVS && HEnvCfg.CBIE === EnvCBIE.Off || <br/> 501 * isModeVU && (HEnvCfg.CBIE === EnvCBIE.Off || SEnvCfg.CBIE === EnvCBIE.Off) <br/> 502 * ) <br/> 503 */ 504 val cboI = Bool() 505 } 506 507 val special = new Bundle { 508 /** 509 * execute CBO.INVAL and perform flush operation when <br/> 510 * isModeHS && MEnvCfg.CBIE === EnvCBIE.Flush || <br/> 511 * isModeHU && (MEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/> 512 * isModeVS && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush) <br/> 513 * isModeVU && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/> 514 */ 515 val cboI2F = Bool() 516 } 517}