1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import device.MsiInfoBundle 23import difftest._ 24import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 25import system.HasSoCParameter 26import utility._ 27import xiangshan._ 28import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 29import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 30import xiangshan.backend.datapath.DataConfig.{IntData, VecData, FpData} 31import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 32import xiangshan.backend.datapath.WbConfig._ 33import xiangshan.backend.datapath.DataConfig._ 34import xiangshan.backend.datapath._ 35import xiangshan.backend.dispatch.CoreDispatchTopDownIO 36import xiangshan.backend.exu.ExuBlock 37import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 38import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PFEvent, PerfCounterIO} 39import xiangshan.backend.issue.EntryBundles._ 40import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerArithImp, SchedulerImpBase, SchedulerMemImp} 41import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 42import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 43import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 44 45import scala.collection.mutable 46 47class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 48 with HasXSParameter { 49 override def shouldBeInlined: Boolean = false 50 val inner = LazyModule(new BackendInlined(params)) 51 lazy val module = new BackendImp(this) 52} 53 54class BackendImp(wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) { 55 val io = IO(new BackendIO()(p, wrapper.params)) 56 io <> wrapper.inner.module.io 57 if (p(DebugOptionsKey).ResetGen) { 58 ResetGen(ResetGenNode(Seq(ModuleNode(wrapper.inner.module))), reset, sim = false) 59 } 60} 61 62class BackendInlined(val params: BackendParams)(implicit p: Parameters) extends LazyModule 63 with HasXSParameter { 64 65 override def shouldBeInlined: Boolean = true 66 67 // check read & write port config 68 params.configChecks 69 70 /* Only update the idx in mem-scheduler here 71 * Idx in other schedulers can be updated the same way if needed 72 * 73 * Also note that we filter out the 'stData issue-queues' when counting 74 */ 75 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 76 ibp.updateIdx(idx) 77 } 78 79 println(params.iqWakeUpParams) 80 81 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 82 schdCfg.bindBackendParam(params) 83 } 84 85 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 86 iqCfg.bindBackendParam(params) 87 } 88 89 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 90 exuCfg.bindBackendParam(params) 91 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 92 exuCfg.updateExuIdx(i) 93 } 94 95 println("[Backend] ExuConfigs:") 96 for (exuCfg <- params.allExuParams) { 97 val fuConfigs = exuCfg.fuConfigs 98 val wbPortConfigs = exuCfg.wbPortConfigs 99 val immType = exuCfg.immType 100 101 println("[Backend] " + 102 s"${exuCfg.name}: " + 103 (if (exuCfg.fakeUnit) "fake, " else "") + 104 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 105 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 106 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 107 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 108 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 109 s"srcReg(${exuCfg.numRegSrc})" 110 ) 111 require( 112 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 113 fuConfigs.map(_.writeIntRf).reduce(_ || _), 114 s"${exuCfg.name} int wb port has no priority" 115 ) 116 require( 117 wbPortConfigs.collectFirst { case x: FpWB => x }.nonEmpty == 118 fuConfigs.map(x => x.writeFpRf).reduce(_ || _), 119 s"${exuCfg.name} fp wb port has no priority" 120 ) 121 require( 122 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 123 fuConfigs.map(x => x.writeVecRf).reduce(_ || _), 124 s"${exuCfg.name} vec wb port has no priority" 125 ) 126 } 127 128 println(s"[Backend] all fu configs") 129 for (cfg <- FuConfig.allConfigs) { 130 println(s"[Backend] $cfg") 131 } 132 133 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 134 for ((port, seq) <- params.getRdPortParams(IntData())) { 135 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 136 } 137 138 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 139 for ((port, seq) <- params.getWbPortParams(IntData())) { 140 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 141 } 142 143 println(s"[Backend] Fp RdConfigs: ExuName(Priority)") 144 for ((port, seq) <- params.getRdPortParams(FpData())) { 145 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 146 } 147 148 println(s"[Backend] Fp WbConfigs: ExuName(Priority)") 149 for ((port, seq) <- params.getWbPortParams(FpData())) { 150 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 151 } 152 153 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 154 for ((port, seq) <- params.getRdPortParams(VecData())) { 155 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 156 } 157 158 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 159 for ((port, seq) <- params.getWbPortParams(VecData())) { 160 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 161 } 162 163 println(s"[Backend] Dispatch Configs:") 164 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 165 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 166 167 params.updateCopyPdestInfo 168 println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}") 169 params.allExuParams.map(_.copyNum) 170 val ctrlBlock = LazyModule(new CtrlBlock(params)) 171 val pcTargetMem = LazyModule(new PcTargetMem(params)) 172 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 173 val fpScheduler = params.fpSchdParams.map(x => LazyModule(new Scheduler(x))) 174 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 175 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 176 val dataPath = LazyModule(new DataPath(params)) 177 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 178 val fpExuBlock = params.fpSchdParams.map(x => LazyModule(new ExuBlock(x))) 179 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 180 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 181 182 lazy val module = new BackendInlinedImp(this) 183} 184 185class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parameters) extends LazyModuleImp(wrapper) 186 with HasXSParameter 187 with HasPerfEvents 188 with HasCriticalErrors { 189 implicit private val params: BackendParams = wrapper.params 190 191 val io = IO(new BackendIO()(p, wrapper.params)) 192 193 private val ctrlBlock = wrapper.ctrlBlock.module 194 private val pcTargetMem = wrapper.pcTargetMem.module 195 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 196 private val fpScheduler = wrapper.fpScheduler.get.module 197 private val vfScheduler = wrapper.vfScheduler.get.module 198 private val memScheduler = wrapper.memScheduler.get.module 199 private val dataPath = wrapper.dataPath.module 200 private val intExuBlock = wrapper.intExuBlock.get.module 201 private val fpExuBlock = wrapper.fpExuBlock.get.module 202 private val vfExuBlock = wrapper.vfExuBlock.get.module 203 private val og2ForVector = Module(new Og2ForVector(params)) 204 private val bypassNetwork = Module(new BypassNetwork) 205 private val wbDataPath = Module(new WbDataPath(params)) 206 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 207 private val vecExcpMod = Module(new VecExcpDataMergeModule) 208 209 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 210 intScheduler.io.toSchedulers.wakeupVec ++ 211 fpScheduler.io.toSchedulers.wakeupVec ++ 212 vfScheduler.io.toSchedulers.wakeupVec ++ 213 memScheduler.io.toSchedulers.wakeupVec 214 ).map(x => (x.bits.exuIdx, x)).toMap 215 216 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 217 218 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 219 wbFuBusyTable.io.in.fpSchdBusyTable := fpScheduler.io.wbFuBusyTable 220 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 221 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 222 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 223 fpScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.fpRespRead 224 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 225 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 226 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 227 228 private val og1Cancel = dataPath.io.og1Cancel 229 private val og0Cancel = dataPath.io.og0Cancel 230 private val vlFromIntIsZero = intExuBlock.io.vlIsZero.get 231 private val vlFromIntIsVlmax = intExuBlock.io.vlIsVlmax.get 232 private val vlFromVfIsZero = vfExuBlock.io.vlIsZero.get 233 private val vlFromVfIsVlmax = vfExuBlock.io.vlIsVlmax.get 234 235 private val backendCriticalError = Wire(Bool()) 236 237 ctrlBlock.io.intIQValidNumVec := intScheduler.io.intIQValidNumVec 238 ctrlBlock.io.fpIQValidNumVec := fpScheduler.io.fpIQValidNumVec 239 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 240 ctrlBlock.io.frontend <> io.frontend 241 ctrlBlock.io.fromCSR.toDecode := intExuBlock.io.csrToDecode.get 242 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 243 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 244 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 245 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 246 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 247 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 248 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 249 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 250 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 251 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 252 ctrlBlock.io.robio.csr.criticalErrorState := intExuBlock.io.csrio.get.criticalErrorState 253 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 254 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 255 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 256 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 257 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 258 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 259 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 260 ctrlBlock.io.debugEnqLsq.iqAccept := memScheduler.io.memIO.get.lsqEnqIO.iqAccept 261 ctrlBlock.io.fromVecExcpMod.busy := vecExcpMod.o.status.busy 262 263 intScheduler.io.fromTop.hartId := io.fromTop.hartId 264 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 265 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 266 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 267 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 268 intScheduler.io.fpWriteBack := 0.U.asTypeOf(intScheduler.io.fpWriteBack) 269 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 270 intScheduler.io.v0WriteBack := 0.U.asTypeOf(intScheduler.io.v0WriteBack) 271 intScheduler.io.vlWriteBack := 0.U.asTypeOf(intScheduler.io.vlWriteBack) 272 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 273 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 274 intScheduler.io.fromDataPath.og0Cancel := og0Cancel 275 intScheduler.io.fromDataPath.og1Cancel := og1Cancel 276 intScheduler.io.ldCancel := io.mem.ldCancel 277 intScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.take(params.getIntExuRCWriteSize) 278 intScheduler.io.vlWriteBackInfo.vlFromIntIsZero := false.B 279 intScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := false.B 280 intScheduler.io.vlWriteBackInfo.vlFromVfIsZero := false.B 281 intScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := false.B 282 283 fpScheduler.io.fromTop.hartId := io.fromTop.hartId 284 fpScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 285 fpScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 286 fpScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.fpUops 287 fpScheduler.io.intWriteBack := 0.U.asTypeOf(fpScheduler.io.intWriteBack) 288 fpScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 289 fpScheduler.io.vfWriteBack := 0.U.asTypeOf(fpScheduler.io.vfWriteBack) 290 fpScheduler.io.v0WriteBack := 0.U.asTypeOf(fpScheduler.io.v0WriteBack) 291 fpScheduler.io.vlWriteBack := 0.U.asTypeOf(fpScheduler.io.vlWriteBack) 292 fpScheduler.io.fromDataPath.resp := dataPath.io.toFpIQ 293 fpScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 294 fpScheduler.io.fromDataPath.og0Cancel := og0Cancel 295 fpScheduler.io.fromDataPath.og1Cancel := og1Cancel 296 fpScheduler.io.ldCancel := io.mem.ldCancel 297 fpScheduler.io.vlWriteBackInfo.vlFromIntIsZero := false.B 298 fpScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := false.B 299 fpScheduler.io.vlWriteBackInfo.vlFromVfIsZero := false.B 300 fpScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := false.B 301 302 memScheduler.io.fromTop.hartId := io.fromTop.hartId 303 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 304 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 305 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 306 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 307 memScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 308 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 309 memScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 310 memScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 311 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 312 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 313 memScheduler.io.fromMem.get.wakeup := io.mem.wakeup 314 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 315 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 316 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 317 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 318 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 319 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 320 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 321 sink.valid := source.valid 322 sink.bits := source.bits.robIdx 323 } 324 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 325 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 326 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 327 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 328 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 329 memScheduler.io.fromMem.get.vstuFeedback := io.mem.vstuIqFeedback 330 memScheduler.io.fromMem.get.vlduFeedback := io.mem.vlduIqFeedback 331 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 332 memScheduler.io.fromDataPath.og0Cancel := og0Cancel 333 memScheduler.io.fromDataPath.og1Cancel := og1Cancel 334 memScheduler.io.ldCancel := io.mem.ldCancel 335 memScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.takeRight(params.getMemExuRCWriteSize) 336 memScheduler.io.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero 337 memScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax 338 memScheduler.io.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero 339 memScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax 340 memScheduler.io.fromOg2Resp.get := og2ForVector.io.toMemIQOg2Resp 341 342 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 343 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 344 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 345 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 346 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 347 vfScheduler.io.fpWriteBack := 0.U.asTypeOf(vfScheduler.io.fpWriteBack) 348 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 349 vfScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 350 vfScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 351 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 352 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 353 vfScheduler.io.fromDataPath.og0Cancel := og0Cancel 354 vfScheduler.io.fromDataPath.og1Cancel := og1Cancel 355 vfScheduler.io.ldCancel := io.mem.ldCancel 356 vfScheduler.io.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero 357 vfScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax 358 vfScheduler.io.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero 359 vfScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax 360 vfScheduler.io.fromOg2Resp.get := og2ForVector.io.toVfIQOg2Resp 361 362 dataPath.io.hartId := io.fromTop.hartId 363 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 364 365 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 366 dataPath.io.fromFpIQ <> fpScheduler.io.toDataPathAfterDelay 367 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 368 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 369 370 dataPath.io.ldCancel := io.mem.ldCancel 371 372 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 373 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 374 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 375 dataPath.io.fromFpWb := wbDataPath.io.toFpPreg 376 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 377 dataPath.io.fromV0Wb := wbDataPath.io.toV0Preg 378 dataPath.io.fromVlWb := wbDataPath.io.toVlPreg 379 dataPath.io.diffIntRat.foreach(_ := ctrlBlock.io.diff_int_rat.get) 380 dataPath.io.diffFpRat .foreach(_ := ctrlBlock.io.diff_fp_rat.get) 381 dataPath.io.diffVecRat.foreach(_ := ctrlBlock.io.diff_vec_rat.get) 382 dataPath.io.diffV0Rat .foreach(_ := ctrlBlock.io.diff_v0_rat.get) 383 dataPath.io.diffVlRat .foreach(_ := ctrlBlock.io.diff_vl_rat.get) 384 dataPath.io.fromBypassNetwork := bypassNetwork.io.toDataPath 385 dataPath.io.fromVecExcpMod.r := vecExcpMod.o.toVPRF.r 386 dataPath.io.fromVecExcpMod.w := vecExcpMod.o.toVPRF.w 387 388 og2ForVector.io.flush := ctrlBlock.io.toDataPath.flush 389 og2ForVector.io.ldCancel := io.mem.ldCancel 390 og2ForVector.io.fromOg1VfArith <> dataPath.io.toVecExu 391 og2ForVector.io.fromOg1VecMem.zip(dataPath.io.toMemExu.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1)) 392 .foreach { 393 case (og1Mem, datapathMem) => og1Mem <> datapathMem 394 } 395 og2ForVector.io.fromOg1ImmInfo := dataPath.io.og1ImmInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1) 396 397 println(s"[Backend] BypassNetwork OG1 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filterNot(_._2.needOg2Resp).size}") 398 println(s"[Backend] BypassNetwork OG2 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).size}") 399 println(s"[Backend] bypassNetwork.io.fromDataPath.mem: ${bypassNetwork.io.fromDataPath.mem.size}, dataPath.io.toMemExu: ${dataPath.io.toMemExu.size}") 400 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 401 bypassNetwork.io.fromDataPath.fp <> dataPath.io.toFpExu 402 bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfArithExu 403 bypassNetwork.io.fromDataPath.mem.lazyZip(params.memSchdParams.get.issueBlockParams).lazyZip(dataPath.io.toMemExu).filterNot(_._2.needOg2Resp) 404 .map(x => (x._1, x._3)).foreach { 405 case (bypassMem, datapathMem) => bypassMem <> datapathMem 406 } 407 bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1) 408 .zip(og2ForVector.io.toVecMemExu).foreach { 409 case (bypassMem, og2Mem) => bypassMem <> og2Mem 410 } 411 bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo 412 bypassNetwork.io.fromDataPath.immInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1) 413 .zip(og2ForVector.io.toBypassNetworkImmInfo).foreach { 414 case (immInfo, og2ImmInfo) => immInfo := og2ImmInfo 415 } 416 bypassNetwork.io.fromDataPath.rcData := dataPath.io.toBypassNetworkRCData 417 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 418 bypassNetwork.io.fromExus.connectExuOutput(_.fp)(fpExuBlock.io.out) 419 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 420 421 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 422 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 423 s"io.mem.writeback(${io.mem.writeBack.size})" 424 ) 425 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 426 sink.valid := source.valid 427 sink.bits.intWen := source.bits.uop.rfWen && source.bits.isFromLoadUnit 428 sink.bits.pdest := source.bits.uop.pdest 429 sink.bits.data := source.bits.data 430 } 431 432 433 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 434 for (i <- 0 until intExuBlock.io.in.length) { 435 for (j <- 0 until intExuBlock.io.in(i).length) { 436 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 437 NewPipelineConnect( 438 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 439 Mux( 440 bypassNetwork.io.toExus.int(i)(j).fire, 441 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 442 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 443 ), 444 Option("bypassNetwork2intExuBlock") 445 ) 446 } 447 } 448 449 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 450 pcTargetMem.io.toDataPath <> dataPath.io.fromPcTargetMem 451 452 private val csrin = intExuBlock.io.csrin.get 453 csrin.hartId := io.fromTop.hartId 454 csrin.msiInfo.valid := RegNext(io.fromTop.msiInfo.valid) 455 csrin.msiInfo.bits := RegEnable(io.fromTop.msiInfo.bits, io.fromTop.msiInfo.valid) 456 csrin.clintTime.valid := RegNext(io.fromTop.clintTime.valid) 457 csrin.clintTime.bits := RegEnable(io.fromTop.clintTime.bits, io.fromTop.clintTime.valid) 458 csrin.trapInstInfo := ctrlBlock.io.toCSR.trapInstInfo 459 csrin.fromVecExcpMod.busy := vecExcpMod.o.status.busy 460 csrin.criticalErrorState := backendCriticalError 461 462 private val csrio = intExuBlock.io.csrio.get 463 csrio.hartId := io.fromTop.hartId 464 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 465 csrio.fpu.isIllegal := false.B // Todo: remove it 466 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 467 csrio.vpu <> WireDefault(0.U.asTypeOf(csrio.vpu)) // Todo 468 469 val fromIntExuVsetVType = intExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 470 val fromVfExuVsetVType = vfExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 471 val fromVsetVType = Mux(fromIntExuVsetVType.valid, fromIntExuVsetVType.bits, fromVfExuVsetVType.bits) 472 val vsetvlVType = RegEnable(fromVsetVType, 0.U.asTypeOf(new VType), fromIntExuVsetVType.valid || fromVfExuVsetVType.valid) 473 ctrlBlock.io.toDecode.vsetvlVType := vsetvlVType 474 475 val commitVType = ctrlBlock.io.robio.commitVType.vtype 476 val hasVsetvl = ctrlBlock.io.robio.commitVType.hasVsetvl 477 val vtype = VType.toVtypeStruct(Mux(hasVsetvl, vsetvlVType, commitVType.bits)).asUInt 478 479 // csr not store the value of vl, so when using difftest we assign the value of vl to debugVl 480 val debugVl_s0 = WireInit(UInt(VlData().dataWidth.W), 0.U) 481 val debugVl_s1 = WireInit(UInt(VlData().dataWidth.W), 0.U) 482 debugVl_s0 := dataPath.io.diffVl.getOrElse(0.U.asTypeOf(UInt(VlData().dataWidth.W))) 483 debugVl_s1 := RegNext(debugVl_s0) 484 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 485 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 486 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 487 ctrlBlock.io.toDecode.vstart := csrio.vpu.vstart 488 //Todo here need change design 489 csrio.vpu.set_vtype.valid := commitVType.valid 490 csrio.vpu.set_vtype.bits := ZeroExt(vtype, XLEN) 491 csrio.vpu.vl := ZeroExt(debugVl_s1, XLEN) 492 csrio.vpu.dirty_vs := ctrlBlock.io.robio.csr.dirty_vs 493 csrio.exception := ctrlBlock.io.robio.exception 494 csrio.robDeqPtr := ctrlBlock.io.robio.robDeqPtr 495 csrio.memExceptionVAddr := io.mem.exceptionAddr.vaddr 496 csrio.memExceptionGPAddr := io.mem.exceptionAddr.gpaddr 497 csrio.memExceptionIsForVSnonLeafPTE := io.mem.exceptionAddr.isForVSnonLeafPTE 498 csrio.externalInterrupt := RegNext(io.fromTop.externalInterrupt) 499 csrio.perf <> io.perf 500 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 501 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 502 private val fenceio = intExuBlock.io.fenceio.get 503 io.fenceio <> fenceio 504 505 // to fpExuBlock 506 fpExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 507 for (i <- 0 until fpExuBlock.io.in.length) { 508 for (j <- 0 until fpExuBlock.io.in(i).length) { 509 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.fp(i)(j).bits.loadDependency, io.mem.ldCancel) 510 NewPipelineConnect( 511 bypassNetwork.io.toExus.fp(i)(j), fpExuBlock.io.in(i)(j), fpExuBlock.io.in(i)(j).fire, 512 Mux( 513 bypassNetwork.io.toExus.fp(i)(j).fire, 514 bypassNetwork.io.toExus.fp(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 515 fpExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 516 ), 517 Option("bypassNetwork2fpExuBlock") 518 ) 519 } 520 } 521 522 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 523 for (i <- 0 until vfExuBlock.io.in.size) { 524 for (j <- 0 until vfExuBlock.io.in(i).size) { 525 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 526 NewPipelineConnect( 527 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 528 Mux( 529 bypassNetwork.io.toExus.vf(i)(j).fire, 530 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 531 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 532 ), 533 Option("bypassNetwork2vfExuBlock") 534 ) 535 536 } 537 } 538 539 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 540 fpExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 541 fpExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 542 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 543 vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 544 545 wbDataPath.io.flush := ctrlBlock.io.redirect 546 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 547 wbDataPath.io.fromIntExu <> intExuBlock.io.out 548 wbDataPath.io.fromFpExu <> fpExuBlock.io.out 549 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 550 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 551 sink.valid := source.valid 552 source.ready := sink.ready 553 sink.bits.data := VecInit(Seq.fill(sink.bits.params.wbPathNum)(source.bits.data)) 554 sink.bits.pdest := source.bits.uop.pdest 555 sink.bits.robIdx := source.bits.uop.robIdx 556 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 557 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 558 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 559 sink.bits.v0Wen.foreach(_ := source.bits.uop.v0Wen) 560 sink.bits.vlWen.foreach(_ := source.bits.uop.vlWen) 561 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 562 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 563 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 564 sink.bits.debug := source.bits.debug 565 sink.bits.debugInfo := source.bits.uop.debugInfo 566 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 567 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 568 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 569 sink.bits.vls.foreach(x => { 570 x.vdIdx := source.bits.vdIdx.get 571 x.vdIdxInField := source.bits.vdIdxInField.get 572 x.vpu := source.bits.uop.vpu 573 x.oldVdPsrc := source.bits.uop.psrc(2) 574 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 575 x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType) 576 x.isStrided := VlduType.isStrided(source.bits.uop.fuOpType) 577 x.isWhole := VlduType.isWhole(source.bits.uop.fuOpType) 578 x.isVecLoad := VlduType.isVecLd(source.bits.uop.fuOpType) 579 x.isVlm := VlduType.isMasked(source.bits.uop.fuOpType) && VlduType.isVecLd(source.bits.uop.fuOpType) 580 }) 581 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 582 } 583 wbDataPath.io.fromCSR.vstart := csrio.vpu.vstart 584 585 vecExcpMod.i.fromExceptionGen := ctrlBlock.io.toVecExcpMod.excpInfo 586 vecExcpMod.i.fromRab.logicPhyRegMap := ctrlBlock.io.toVecExcpMod.logicPhyRegMap 587 vecExcpMod.i.fromRat := ctrlBlock.io.toVecExcpMod.ratOldPest 588 vecExcpMod.i.fromVprf := dataPath.io.toVecExcpMod 589 590 // to mem 591 private val memIssueParams = params.memSchdParams.get.issueBlockParams 592 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 593 private val memExuBlocksHasVecLoad = memIssueParams.map(_.exuBlockParams.map(x => x.hasVLoadFu)) 594 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 595 println(s"[Backend] memExuBlocksHasVecLoad: $memExuBlocksHasVecLoad") 596 597 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 598 for (i <- toMem.indices) { 599 for (j <- toMem(i).indices) { 600 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 601 val needIssueTimeout = memExuBlocksHasLDU(i)(j) || memExuBlocksHasVecLoad(i)(j) 602 val issueTimeout = 603 if (needIssueTimeout) 604 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 605 else 606 false.B 607 608 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 609 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 610 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 611 memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block 612 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 613 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 614 memScheduler.io.loadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 615 memScheduler.io.loadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 616 } 617 618 if (memScheduler.io.vecLoadFinalIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 619 memScheduler.io.vecLoadFinalIssueResp(i)(j).valid := issueTimeout 620 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 621 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.resp := RespType.block 622 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 623 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 624 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 625 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 626 } 627 628 NewPipelineConnect( 629 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 630 Mux( 631 bypassNetwork.io.toExus.mem(i)(j).fire, 632 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 633 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 634 ), 635 Option("bypassNetwork2toMemExus") 636 ) 637 638 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 639 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 640 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 641 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 642 memScheduler.io.memAddrIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 643 memScheduler.io.memAddrIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 644 memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully 645 } 646 647 if (memScheduler.io.vecLoadIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 648 memScheduler.io.vecLoadIssueResp(i)(j) match { 649 case resp => 650 resp.valid := toMem(i)(j).fire && VlduType.isVecLd(toMem(i)(j).bits.fuOpType) 651 resp.bits.fuType := toMem(i)(j).bits.fuType 652 resp.bits.robIdx := toMem(i)(j).bits.robIdx 653 resp.bits.uopIdx.get := toMem(i)(j).bits.vpu.get.vuopIdx 654 resp.bits.sqIdx.get := toMem(i)(j).bits.sqIdx.get 655 resp.bits.lqIdx.get := toMem(i)(j).bits.lqIdx.get 656 resp.bits.resp := RespType.success 657 } 658 if (backendParams.debugEn){ 659 dontTouch(memScheduler.io.vecLoadIssueResp(i)(j)) 660 } 661 } 662 } 663 } 664 665 io.mem.redirect := ctrlBlock.io.redirect 666 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 667 val enableMdp = Constantin.createRecord("EnableMdp", true) 668 sink.valid := source.valid 669 source.ready := sink.ready 670 sink.bits.iqIdx := source.bits.iqIdx 671 sink.bits.isFirstIssue := source.bits.isFirstIssue 672 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 673 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 674 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 675 sink.bits.uop.fuType := source.bits.fuType 676 sink.bits.uop.fuOpType := source.bits.fuOpType 677 sink.bits.uop.imm := source.bits.imm 678 sink.bits.uop.robIdx := source.bits.robIdx 679 sink.bits.uop.pdest := source.bits.pdest 680 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 681 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 682 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 683 sink.bits.uop.v0Wen := source.bits.v0Wen.getOrElse(false.B) 684 sink.bits.uop.vlWen := source.bits.vlWen.getOrElse(false.B) 685 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 686 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 687 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 688 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 689 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 690 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 691 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 692 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 693 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 694 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 695 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 696 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 697 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 698 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 699 sink.bits.uop.numLsElem := source.bits.numLsElem.getOrElse(0.U) // Todo: remove this bundle, keep only the one below 700 sink.bits.flowNum.foreach(_ := source.bits.numLsElem.get) 701 } 702 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 703 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 704 io.mem.tlbCsr := csrio.tlb 705 io.mem.csrCtrl := csrio.customCtrl 706 io.mem.sfence := fenceio.sfence 707 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 708 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 709 require(io.mem.loadPcRead.size == params.LduCnt) 710 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 711 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 712 ctrlBlock.io.memLdPcRead(i).valid := io.mem.issueLda(i).valid 713 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 714 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 715 } 716 717 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 718 storePcRead := ctrlBlock.io.memStPcRead(i).data 719 ctrlBlock.io.memStPcRead(i).valid := io.mem.issueSta(i).valid 720 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 721 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 722 } 723 724 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 725 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 726 ctrlBlock.io.memHyPcRead(i).valid := io.mem.issueHylda(i).valid 727 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 728 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 729 }) 730 731 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 732 733 // mem io 734 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 735 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 736 io.mem.storeDebugInfo <> ctrlBlock.io.robio.storeDebugInfo 737 738 io.frontendSfence := fenceio.sfence 739 io.frontendTlbCsr := csrio.tlb 740 io.frontendCsrCtrl := csrio.customCtrl 741 742 io.tlb <> csrio.tlb 743 744 io.csrCustomCtrl := csrio.customCtrl 745 746 io.toTop.cpuHalted := ctrlBlock.io.toTop.cpuHalt 747 748 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 749 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 750 751 io.debugRolling := ctrlBlock.io.debugRolling 752 753 if(backendParams.debugEn) { 754 dontTouch(memScheduler.io) 755 dontTouch(dataPath.io.toMemExu) 756 dontTouch(wbDataPath.io.fromMemExu) 757 } 758 759 // reset tree 760 if (p(DebugOptionsKey).ResetGen) { 761 val rightResetTree = ResetGenNode(Seq( 762 ModuleNode(dataPath), 763 ModuleNode(intExuBlock), 764 ModuleNode(fpExuBlock), 765 ModuleNode(vfExuBlock), 766 ModuleNode(bypassNetwork), 767 ModuleNode(wbDataPath) 768 )) 769 val leftResetTree = ResetGenNode(Seq( 770 ModuleNode(pcTargetMem), 771 ModuleNode(intScheduler), 772 ModuleNode(fpScheduler), 773 ModuleNode(vfScheduler), 774 ModuleNode(memScheduler), 775 ModuleNode(og2ForVector), 776 ModuleNode(wbFuBusyTable), 777 ResetGenNode(Seq( 778 ModuleNode(ctrlBlock), 779 // ResetGenNode(Seq( 780 CellNode(io.frontendReset) 781 // )) 782 )) 783 )) 784 ResetGen(leftResetTree, reset, sim = false) 785 ResetGen(rightResetTree, reset, sim = false) 786 } else { 787 io.frontendReset := DontCare 788 } 789 790 // perf events 791 val pfevent = Module(new PFEvent) 792 pfevent.io.distribute_csr := RegNext(csrio.customCtrl.distribute_csr) 793 val csrevents = pfevent.io.hpmevent.slice(8,16) 794 795 val ctrlBlockPerf = ctrlBlock.getPerfEvents 796 val intSchedulerPerf = intScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 797 val fpSchedulerPerf = fpScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 798 val vecSchedulerPerf = vfScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 799 val memSchedulerPerf = memScheduler.asInstanceOf[SchedulerMemImp].getPerfEvents 800 801 val perfBackend = Seq() 802 // let index = 0 be no event 803 val allPerfEvents = Seq(("noEvent", 0.U)) ++ ctrlBlockPerf ++ intSchedulerPerf ++ fpSchedulerPerf ++ vecSchedulerPerf ++ memSchedulerPerf ++ perfBackend 804 805 806 if (printEventCoding) { 807 for (((name, inc), i) <- allPerfEvents.zipWithIndex) { 808 println("backend perfEvents Set", name, inc, i) 809 } 810 } 811 812 val allPerfInc = allPerfEvents.map(_._2.asTypeOf(new PerfEvent)) 813 val perfEvents = HPerfMonitor(csrevents, allPerfInc).getPerfEvents 814 csrio.perf.perfEventsBackend := VecInit(perfEvents.map(_._2.asTypeOf(new PerfEvent))) 815 816 val ctrlBlockError = ctrlBlock.getCriticalErrors 817 val intExuBlockError = intExuBlock.getCriticalErrors 818 val criticalErrors = ctrlBlockError ++ intExuBlockError 819 820 if (printCriticalError) { 821 for (((name, error), _) <- criticalErrors.zipWithIndex) { 822 XSError(error, s"critical error: $name \n") 823 } 824 } 825 826 // expand to collect frontend/memblock/L2 critical errors 827 backendCriticalError := criticalErrors.map(_._2).reduce(_ || _) 828 829 io.toTop.cpuCriticalError := csrio.criticalErrorState 830} 831 832class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 833 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 834 val flippedLda = true 835 // params alias 836 private val LoadQueueSize = VirtualLoadQueueSize 837 // In/Out // Todo: split it into one-direction bundle 838 val lsqEnqIO = Flipped(new LsqEnqIO) 839 val robLsqIO = new RobLsqIO 840 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 841 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 842 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 843 val vstuIqFeedback = Flipped(Vec(params.VstuCnt, new MemRSFeedbackIO(isVector = true))) 844 val vlduIqFeedback = Flipped(Vec(params.VlduCnt, new MemRSFeedbackIO(isVector = true))) 845 val ldCancel = Vec(params.LdExuCnt, Input(new LoadCancelIO)) 846 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 847 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 848 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 849 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 850 // Input 851 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 852 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 853 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 854 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 855 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 856 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 857 858 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 859 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 860 val memoryViolation = Flipped(ValidIO(new Redirect)) 861 val exceptionAddr = Input(new Bundle { 862 val vaddr = UInt(XLEN.W) 863 val gpaddr = UInt(XLEN.W) 864 val isForVSnonLeafPTE = Bool() 865 }) 866 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 867 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 868 val sqDeqPtr = Input(new SqPtr) 869 val lqDeqPtr = Input(new LqPtr) 870 871 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 872 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 873 874 val lqCanAccept = Input(Bool()) 875 val sqCanAccept = Input(Bool()) 876 877 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 878 val stIssuePtr = Input(new SqPtr()) 879 880 val debugLS = Flipped(Output(new DebugLSIO)) 881 882 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 883 // Output 884 val redirect = ValidIO(new Redirect) // rob flush MemBlock 885 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 886 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 887 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 888 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 889 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 890 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 891 892 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 893 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 894 895 val tlbCsr = Output(new TlbCsrBundle) 896 val csrCtrl = Output(new CustomCSRCtrlIO) 897 val sfence = Output(new SfenceBundle) 898 val isStoreException = Output(Bool()) 899 val isVlsException = Output(Bool()) 900 901 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 902 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 903 issueSta ++ 904 issueHylda ++ issueHysta ++ 905 issueLda ++ 906 issueVldu ++ 907 issueStd 908 }.toSeq 909 910 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 911 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 912 writebackSta ++ 913 writebackHyuLda ++ writebackHyuSta ++ 914 writebackLda ++ 915 writebackVldu ++ 916 writebackStd 917 } 918 919 // store event difftest information 920 val storeDebugInfo = Vec(EnsbufferWidth, new Bundle { 921 val robidx = Input(new RobPtr) 922 val pc = Output(UInt(VAddrBits.W)) 923 }) 924} 925 926class TopToBackendBundle(implicit p: Parameters) extends XSBundle { 927 val hartId = Output(UInt(hartIdLen.W)) 928 val externalInterrupt = Output(new ExternalInterruptIO) 929 val msiInfo = Output(ValidIO(new MsiInfoBundle)) 930 val clintTime = Output(ValidIO(UInt(64.W))) 931} 932 933class BackendToTopBundle extends Bundle { 934 val cpuHalted = Output(Bool()) 935 val cpuCriticalError = Output(Bool()) 936} 937 938class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle with HasSoCParameter { 939 val fromTop = Flipped(new TopToBackendBundle) 940 941 val toTop = new BackendToTopBundle 942 943 val fenceio = new FenceIO 944 // Todo: merge these bundles into BackendFrontendIO 945 val frontend = Flipped(new FrontendToCtrlIO) 946 val frontendSfence = Output(new SfenceBundle) 947 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 948 val frontendTlbCsr = Output(new TlbCsrBundle) 949 val frontendReset = Output(Reset()) 950 951 val mem = new BackendMemIO 952 953 val perf = Input(new PerfCounterIO) 954 955 val tlb = Output(new TlbCsrBundle) 956 957 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 958 959 val debugTopDown = new Bundle { 960 val fromRob = new RobCoreTopDownIO 961 val fromCore = new CoreDispatchTopDownIO 962 } 963 val debugRolling = new RobDebugRollingIO 964} 965