| #
d6059658 |
| 07-Nov-2023 |
Ziyue Zhang <[email protected]> |
rv64v: support all opivi instructions use i2v
|
| #
0bfd9349 |
| 01-Nov-2023 |
Ziyue Zhang <[email protected]> |
rv64v: fix both use vec and fp read port
|
| #
7a96cc7f |
| 01-Nov-2023 |
Haojin Tang <[email protected]> |
ExuOH: use UInt instead of Vec[Bool] to reduce generating time
|
| #
6ce10964 |
| 12-Oct-2023 |
Xuan Hu <[email protected]> |
fix merge errors
|
| #
83ba63b3 |
| 11-Oct-2023 |
Xuan Hu <[email protected]> |
fix merge error
|
| #
f1ba628b |
| 26-Sep-2023 |
Haojin Tang <[email protected]> |
Rob: fix FP CSR issue when rob compressing
|
| #
9b8ed6d6 |
| 06-Oct-2023 |
Haojin Tang <[email protected]> |
Backend: remove unused `ftqIdx` and `ftqOffset` from ExuOutput
|
| #
427cfec3 |
| 06-Oct-2023 |
Haojin Tang <[email protected]> |
IssueQueue: pass pc together with dynInst bundles
|
| #
96e858ba |
| 24-Sep-2023 |
Xuan Hu <[email protected]> |
backend: add perfDebugInfo
|
| #
73b1b2e4 |
| 20-Sep-2023 |
zhanglyGit <[email protected]> |
Backend: fix bug of BusyTable's wakeup and cancel(~rfWen != fpWen || vecWen)
|
| #
d8a24b06 |
| 20-Sep-2023 |
zhanglyGit <[email protected]> |
Backend: refactor jump targetMem in CtrlBlock
|
| #
bc7d6943 |
| 08-Sep-2023 |
zhanglyGit <[email protected]> |
Backend: implement speculative busytable supporting fastWakeUp and cancel
|
| #
0f55a0d3 |
| 05-Sep-2023 |
Haojin Tang <[email protected]> |
Scheduler: implement load speculative wakeup and cancel
|
| #
582849ff |
| 02-Sep-2023 |
xiaofeibao-xjtu <[email protected]> |
backend: support unordered vfreduction
|
| #
765e58c6 |
| 31-Aug-2023 |
sinsanction <[email protected]> |
Backend, Fusion: another implementation for instruction fusion case 'lui + addi(w)' without widening imm bits
|
| #
30fcc710 |
| 31-Aug-2023 |
Ziyue Zhang <[email protected]> |
rv64v: fix vmask instructions' tail elements
*pass: vmand.mm, vmnand.mm, vmandn.mm, vmxor.mm, vmor.mm, vmnor.mm, vmorn.mm, vmxnor.mm
|
| #
fe528fd6 |
| 25-Aug-2023 |
sinsanction <[email protected]> |
Backend, Fusion: support instruction fusion case 'lui + addi'
|
| #
bdda74fd |
| 17-Aug-2023 |
xiaofeibao-xjtu <[email protected]> |
exu: vector float units(vfalu,vfma,vfdivsqrt) execute scalar float instructions
|
| #
3bc74e23 |
| 14-Aug-2023 |
zhanglyGit <[email protected]> |
Backend: fix bug of fflags because of ROB Compress
|
| #
5db4956b |
| 10-Aug-2023 |
zhanglyGit <[email protected]> |
Backend: refactor issueQueue to entry form
|
| #
89cc69c1 |
| 11-Aug-2023 |
Tang Haojin <[email protected]> |
Rob: support ROB compression (#2192)
For consecutive instructions that do not raise exceptions,
they can share a same rob entry and reduce rob consumption.
Only scalar instructions are supported no
Rob: support ROB compression (#2192)
For consecutive instructions that do not raise exceptions,
they can share a same rob entry and reduce rob consumption.
Only scalar instructions are supported now.
---------
Co-authored-by: fdy <[email protected]>
show more ...
|
| #
870f462d |
| 11-Aug-2023 |
Xuan Hu <[email protected]> |
fix errors in merge master into new-backend
|
| #
39c59369 |
| 03-Aug-2023 |
Xuan Hu <[email protected]> |
params,backend: refactor RegFile parameters
|
| #
10fe9778 |
| 20-Jul-2023 |
Xuan Hu <[email protected]> |
backend: remove IssueQueueCancelBundle
|
| #
10434c39 |
| 20-Jul-2023 |
Xuan Hu <[email protected]> |
iq: remove useless l2ExuVec
* Since all exu used as source of wake-up must be ready at OG1 stage, there is no need to take the cancel signal of indirect source of wake-up into consideration.
|