1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, IssueQueueJumpBundle, SchedulerType, EntryDeqRespBundle} 19import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 20import xiangshan.backend.rob.RobPtr 21import xiangshan.frontend._ 22import xiangshan.mem.{LqPtr, SqPtr} 23 24object Bundles { 25 26 // frontend -> backend 27 class StaticInst(implicit p: Parameters) extends XSBundle { 28 val instr = UInt(32.W) 29 val pc = UInt(VAddrBits.W) 30 val foldpc = UInt(MemPredPCWidth.W) 31 val exceptionVec = ExceptionVec() 32 val trigger = new TriggerCf 33 val preDecodeInfo = new PreDecodeInfo 34 val pred_taken = Bool() 35 val crossPageIPFFix = Bool() 36 val ftqPtr = new FtqPtr 37 val ftqOffset = UInt(log2Up(PredictWidth).W) 38 39 def connectCtrlFlow(source: CtrlFlow): Unit = { 40 this.instr := source.instr 41 this.pc := source.pc 42 this.foldpc := source.foldpc 43 this.exceptionVec := source.exceptionVec 44 this.trigger := source.trigger 45 this.preDecodeInfo := source.pd 46 this.pred_taken := source.pred_taken 47 this.crossPageIPFFix := source.crossPageIPFFix 48 this.ftqPtr := source.ftqPtr 49 this.ftqOffset := source.ftqOffset 50 } 51 } 52 53 // StaticInst --[Decode]--> DecodedInst 54 class DecodedInst(implicit p: Parameters) extends XSBundle { 55 def numSrc = backendParams.numSrc 56 // passed from StaticInst 57 val instr = UInt(32.W) 58 val pc = UInt(VAddrBits.W) 59 val foldpc = UInt(MemPredPCWidth.W) 60 val exceptionVec = ExceptionVec() 61 val trigger = new TriggerCf 62 val preDecodeInfo = new PreDecodeInfo 63 val pred_taken = Bool() 64 val crossPageIPFFix = Bool() 65 val ftqPtr = new FtqPtr 66 val ftqOffset = UInt(log2Up(PredictWidth).W) 67 // decoded 68 val srcType = Vec(numSrc, SrcType()) 69 val lsrc = Vec(numSrc, UInt(6.W)) 70 val ldest = UInt(6.W) 71 val fuType = FuType() 72 val fuOpType = FuOpType() 73 val rfWen = Bool() 74 val fpWen = Bool() 75 val vecWen = Bool() 76 val isXSTrap = Bool() 77 val waitForward = Bool() // no speculate execution 78 val blockBackward = Bool() 79 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 80 val canRobCompress = Bool() 81 val selImm = SelImm() 82 val imm = UInt(ImmUnion.maxLen.W) 83 val fpu = new FPUCtrlSignals 84 val vpu = new VPUCtrlSignals 85 val isMove = Bool() 86 val uopIdx = UInt(5.W) 87 val uopSplitType = UopSplitType() 88 val isVset = Bool() 89 val firstUop = Bool() 90 val lastUop = Bool() 91 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 92 val commitType = CommitType() // Todo: remove it 93 94 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 95 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 96 97 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 98 val decoder: Seq[UInt] = ListLookup( 99 inst, XDecode.decodeDefault.map(bitPatToUInt), 100 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 101 ) 102 allSignals zip decoder foreach { case (s, d) => s := d } 103 this 104 } 105 106 def isSoftPrefetch: Bool = { 107 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 108 } 109 110 def connectStaticInst(source: StaticInst): Unit = { 111 for ((name, data) <- this.elements) { 112 if (source.elements.contains(name)) { 113 data := source.elements(name) 114 } 115 } 116 } 117 } 118 119 // DecodedInst --[Rename]--> DynInst 120 class DynInst(implicit p: Parameters) extends XSBundle { 121 def numSrc = backendParams.numSrc 122 // passed from StaticInst 123 val instr = UInt(32.W) 124 val pc = UInt(VAddrBits.W) 125 val foldpc = UInt(MemPredPCWidth.W) 126 val exceptionVec = ExceptionVec() 127 val trigger = new TriggerCf 128 val preDecodeInfo = new PreDecodeInfo 129 val pred_taken = Bool() 130 val crossPageIPFFix = Bool() 131 val ftqPtr = new FtqPtr 132 val ftqOffset = UInt(log2Up(PredictWidth).W) 133 // passed from DecodedInst 134 val srcType = Vec(numSrc, SrcType()) 135 val lsrc = Vec(numSrc, UInt(6.W)) 136 val ldest = UInt(6.W) 137 val fuType = FuType() 138 val fuOpType = FuOpType() 139 val rfWen = Bool() 140 val fpWen = Bool() 141 val vecWen = Bool() 142 val isXSTrap = Bool() 143 val waitForward = Bool() // no speculate execution 144 val blockBackward = Bool() 145 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 146 val canRobCompress = Bool() 147 val selImm = SelImm() 148 val imm = UInt(XLEN.W) // Todo: check if it need minimized 149 val fpu = new FPUCtrlSignals 150 val vpu = new VPUCtrlSignals 151 val isMove = Bool() 152 val uopIdx = UInt(5.W) 153 val isVset = Bool() 154 val firstUop = Bool() 155 val lastUop = Bool() 156 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 157 val commitType = CommitType() 158 // rename 159 val srcState = Vec(numSrc, SrcState()) 160 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 161 val pdest = UInt(PhyRegIdxWidth.W) 162 val robIdx = new RobPtr 163 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 164 165 val eliminatedMove = Bool() 166 // Take snapshot at this CFI inst 167 val snapshot = Bool() 168 val debugInfo = new PerfDebugInfo 169 val storeSetHit = Bool() // inst has been allocated an store set 170 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 171 // Load wait is needed 172 // load inst will not be executed until former store (predicted by mdp) addr calcuated 173 val loadWaitBit = Bool() 174 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 175 // load inst will not be executed until ALL former store addr calcuated 176 val loadWaitStrict = Bool() 177 val ssid = UInt(SSIDWidth.W) 178 // Todo 179 val lqIdx = new LqPtr 180 val sqIdx = new SqPtr 181 // debug module 182 val singleStep = Bool() 183 // schedule 184 val replayInst = Bool() 185 186 def isLUI: Bool = this.fuType === FuType.alu.U && this.selImm === SelImm.IMM_U 187 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 188 189 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 190 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 191 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 192 193 def srcIsReady: Vec[Bool] = { 194 VecInit(this.srcType.zip(this.srcState).map { 195 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 196 }) 197 } 198 199 def clearExceptions( 200 exceptionBits: Seq[Int] = Seq(), 201 flushPipe : Boolean = false, 202 replayInst : Boolean = false 203 ): DynInst = { 204 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 205 if (!flushPipe) { this.flushPipe := false.B } 206 if (!replayInst) { this.replayInst := false.B } 207 this 208 } 209 210 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen 211 } 212 213 trait BundleSource { 214 var wakeupSource = "undefined" 215 var idx = 0 216 } 217 218 /** 219 * 220 * @param pregIdxWidth index width of preg 221 * @param exuIndices exu indices of wakeup bundle 222 */ 223 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int]) extends Bundle { 224 val rfWen = Bool() 225 val fpWen = Bool() 226 val vecWen = Bool() 227 val pdest = UInt(pregIdxWidth.W) 228 229 /** 230 * @param successor Seq[(psrc, srcType)] 231 * @return Seq[if wakeup psrc] 232 */ 233 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 234 successor.map { case (thatPsrc, srcType) => 235 val pdestMatch = pdest === thatPsrc 236 pdestMatch && ( 237 SrcType.isFp(srcType) && this.fpWen || 238 SrcType.isXp(srcType) && this.rfWen || 239 SrcType.isVp(srcType) && this.vecWen 240 ) && valid 241 } 242 } 243 244 def hasOnlyOneSource: Boolean = exuIndices.size == 1 245 246 def hasMultiSources: Boolean = exuIndices.size > 1 247 248 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 249 250 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 251 252 def exuIdx: Int = { 253 require(hasOnlyOneSource) 254 this.exuIndices.head 255 } 256 } 257 258 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 259 260 } 261 262 class IssueQueueIQWakeUpBundle(exuIdx: Int, backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 263 def fromExuInput(exuInput: ExuInput, l2ExuVecs: Vec[Vec[Bool]]): Unit = { 264 this.rfWen := exuInput.rfWen.getOrElse(false.B) 265 this.fpWen := exuInput.fpWen.getOrElse(false.B) 266 this.vecWen := exuInput.vecWen.getOrElse(false.B) 267 this.pdest := exuInput.pdest 268 } 269 270 def fromExuInput(exuInput: ExuInput): Unit = { 271 this.rfWen := exuInput.rfWen.getOrElse(false.B) 272 this.fpWen := exuInput.fpWen.getOrElse(false.B) 273 this.vecWen := exuInput.vecWen.getOrElse(false.B) 274 this.pdest := exuInput.pdest 275 } 276 } 277 278 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 279 // vtype 280 val vill = Bool() 281 val vma = Bool() // 1: agnostic, 0: undisturbed 282 val vta = Bool() // 1: agnostic, 0: undisturbed 283 val vsew = VSew() 284 val vlmul = VLmul() // 1/8~8 --> -3~3 285 286 val vm = Bool() // 0: need v0.t 287 val vstart = Vl() 288 289 // float rounding mode 290 val frm = Frm() 291 // vector fix int rounding mode 292 val vxrm = Vxrm() 293 // vector uop index, exclude other non-vector uop 294 val vuopIdx = UopIdx() 295 // maybe used if data dependancy 296 val vmask = UInt(MaskSrcData().dataWidth.W) 297 val vl = Vl() 298 299 // vector load/store 300 val nf = Nf() 301 302 val needScalaSrc = Bool() 303 val permImmTruncate = Bool() // opivi 304 305 val isReverse = Bool() // vrsub, vrdiv 306 val isExt = Bool() 307 val isNarrow = Bool() 308 val isDstMask = Bool() // vvm, vvvm, mmm 309 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 310 311 def vtype: VType = { 312 val res = Wire(VType()) 313 res.illegal := this.vill 314 res.vma := this.vma 315 res.vta := this.vta 316 res.vsew := this.vsew 317 res.vlmul := this.vlmul 318 res 319 } 320 321 def vconfig: VConfig = { 322 val res = Wire(VConfig()) 323 res.vtype := this.vtype 324 res.vl := this.vl 325 res 326 } 327 } 328 329 // DynInst --[IssueQueue]--> DataPath 330 class IssueQueueIssueBundle( 331 iqParams: IssueBlockParams, 332 val exuParams: ExeUnitParams, 333 )(implicit 334 p: Parameters 335 ) extends Bundle { 336 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 337 338 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 339 rfReadDataCfgSet.map((set: Set[DataConfig]) => 340 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 341 ) 342 )) 343 344 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 345 val immType = SelImm() // used to select imm extractor 346 val common = new ExuInput(exuParams) 347 val jmp = if (exuParams.needPc) Some(Flipped(new IssueQueueJumpBundle)) else None 348 val addrOH = UInt(iqParams.numEntries.W) 349 350 def exuIdx = exuParams.exuIdx 351 def getSource: SchedulerType = exuParams.getWBSource 352 def getIntWbBusyBundle = common.rfWen.toSeq 353 def getVfWbBusyBundle = common.getVfWen.toSeq 354 def getIntRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readInt) 355 def getVfRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readVf) 356 357 def getIntRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 358 getIntRfReadBundle.zip(srcType).map { 359 case (rfRd: RfReadPortWithConfig, t: UInt) => 360 makeValid(issueValid && SrcType.isXp(t), rfRd) 361 } 362 } 363 364 def getVfRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 365 getVfRfReadBundle.zip(srcType).map { 366 case (rfRd: RfReadPortWithConfig, t: UInt) => 367 makeValid(issueValid && SrcType.isVfp(t), rfRd) 368 } 369 } 370 371 def getIntRfWriteValidBundle(issueValid: Bool) = { 372 373 } 374 } 375 376 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 377 val issueQueueParams = this.params 378 val og0resp = Valid(new EntryDeqRespBundle) 379 val og1resp = Valid(new EntryDeqRespBundle) 380 } 381 382 class fuBusyRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 383 val respType = RSFeedbackType() // update credit if needs replay 384 val rfWen = Bool() // TODO: use params to identify IntWB/VfWB 385 val fuType = FuType() 386 } 387 388 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 389 private val intCertainLat = params.intLatencyCertain 390 private val vfCertainLat = params.vfLatencyCertain 391 private val intLat = params.intLatencyValMax 392 private val vfLat = params.vfLatencyValMax 393 394 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 395 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 396 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 397 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 398 } 399 400 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 401 private val intCertainLat = params.intLatencyCertain 402 private val vfCertainLat = params.vfLatencyCertain 403 private val intLat = params.intLatencyValMax 404 private val vfLat = params.vfLatencyValMax 405 406 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 407 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 408 } 409 410 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 411 private val intCertainLat = params.intLatencyCertain 412 private val vfCertainLat = params.vfLatencyCertain 413 414 val intConflict = OptionWrapper(intCertainLat, Bool()) 415 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 416 } 417 418 // DataPath --[ExuInput]--> Exu 419 class ExuInput(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 420 val fuType = FuType() 421 val fuOpType = FuOpType() 422 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 423 val imm = UInt(XLEN.W) 424 val robIdx = new RobPtr 425 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 426 val isFirstIssue = Bool() // Only used by store yet 427 val pdest = UInt(params.wbPregIdxWidth.W) 428 val rfWen = if (params.writeIntRf) Some(Bool()) else None 429 val fpWen = if (params.writeFpRf) Some(Bool()) else None 430 val vecWen = if (params.writeVecRf) Some(Bool()) else None 431 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 432 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 433 val flushPipe = if (params.flushPipe) Some(Bool()) else None 434 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 435 val jalrTarget = if (params.hasJmpFu) Some(UInt(VAddrData().dataWidth.W)) else None 436 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 437 val ftqIdx = if (params.needPc || params.replayInst) 438 Some(new FtqPtr) else None 439 val ftqOffset = if (params.needPc || params.replayInst) 440 Some(UInt(log2Up(PredictWidth).W)) else None 441 val predictInfo = if (params.hasPredecode) Some(new Bundle { 442 val target = UInt(VAddrData().dataWidth.W) 443 val taken = Bool() 444 }) else None 445 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 446 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 447 val dataSources = Vec(params.numRegSrc, DataSource()) 448 val l1ExuVec = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuVec())) 449 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 450 451 def exuIdx = this.params.exuIdx 452 453 def needCancel(og0CancelVec: Vec[Bool], og1CancelVec: Vec[Bool]) : Bool = { 454 if (params.isIQWakeUpSink) { 455 require( 456 og0CancelVec.size == l1ExuVec.get.head.size, 457 s"cancelVecSize: {og0: ${og0CancelVec.size}, og1: ${og1CancelVec.size}}" 458 ) 459 val l1Cancel: Bool = l1ExuVec.get.zip(srcTimer.get).map { 460 case(exuOH: Vec[Bool], srcTimer: UInt) => 461 (exuOH.asUInt & og0CancelVec.asUInt).orR && srcTimer === 1.U 462 }.reduce(_ | _) 463 l1Cancel 464 } else { 465 false.B 466 } 467 } 468 469 def getVfWen = { 470 if (params.writeFpRf) this.fpWen 471 else if(params.writeVecRf) this.vecWen 472 else None 473 } 474 475 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 476 // src is assigned to rfReadData 477 this.fuType := source.common.fuType 478 this.fuOpType := source.common.fuOpType 479 this.imm := source.common.imm 480 this.robIdx := source.common.robIdx 481 this.pdest := source.common.pdest 482 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 483 this.iqIdx := source.common.iqIdx // Only used by mem feedback 484 this.dataSources := source.common.dataSources 485 this.rfWen .foreach(_ := source.common.rfWen.get) 486 this.fpWen .foreach(_ := source.common.fpWen.get) 487 this.vecWen .foreach(_ := source.common.vecWen.get) 488 this.fpu .foreach(_ := source.common.fpu.get) 489 this.vpu .foreach(_ := source.common.vpu.get) 490 this.flushPipe .foreach(_ := source.common.flushPipe.get) 491 this.pc .foreach(_ := source.jmp.get.pc) 492 this.jalrTarget .foreach(_ := source.jmp.get.target) 493 this.preDecode .foreach(_ := source.common.preDecode.get) 494 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 495 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 496 this.predictInfo .foreach(_ := source.common.predictInfo.get) 497 this.lqIdx .foreach(_ := source.common.lqIdx.get) 498 this.sqIdx .foreach(_ := source.common.sqIdx.get) 499 this.l1ExuVec .foreach(_ := source.common.l1ExuVec.get) 500 this.srcTimer .foreach(_ := source.common.srcTimer.get) 501 } 502 } 503 504 // ExuInput --[FuncUnit]--> ExuOutput 505 class ExuOutput( 506 val params: ExeUnitParams, 507 )(implicit 508 val p: Parameters 509 ) extends Bundle with BundleSource with HasXSParameter { 510 val data = UInt(params.dataBitsMax.W) 511 val pdest = UInt(params.wbPregIdxWidth.W) 512 val robIdx = new RobPtr 513 val intWen = if (params.writeIntRf) Some(Bool()) else None 514 val fpWen = if (params.writeFpRf) Some(Bool()) else None 515 val vecWen = if (params.writeVecRf) Some(Bool()) else None 516 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 517 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 518 val wflags = if (params.writeFflags) Some(Bool()) else None 519 val vxsat = if (params.writeVxsat) Some(Bool()) else None 520 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 521 val flushPipe = if (params.flushPipe) Some(Bool()) else None 522 val replay = if (params.replayInst) Some(Bool()) else None 523 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 524 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 525 Some(new SqPtr()) else None 526 val ftqIdx = if (params.needPc || params.replayInst) 527 Some(new FtqPtr) else None 528 val ftqOffset = if (params.needPc || params.replayInst) 529 Some(UInt(log2Up(PredictWidth).W)) else None 530 // uop info 531 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 532 val debug = new DebugBundle 533 val debugInfo = new PerfDebugInfo 534 } 535 536 // ExuOutput + DynInst --> WriteBackBundle 537 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 538 val rfWen = Bool() 539 val fpWen = Bool() 540 val vecWen = Bool() 541 val pdest = UInt(params.pregIdxWidth(backendParams).W) 542 val data = UInt(params.dataWidth.W) 543 val robIdx = new RobPtr()(p) 544 val flushPipe = Bool() 545 val replayInst = Bool() 546 val redirect = ValidIO(new Redirect) 547 val fflags = UInt(5.W) 548 val vxsat = Bool() 549 val exceptionVec = ExceptionVec() 550 val debug = new DebugBundle 551 val debugInfo = new PerfDebugInfo 552 553 this.wakeupSource = s"WB(${params.toString})" 554 555 def fromExuOutput(source: ExuOutput) = { 556 this.rfWen := source.intWen.getOrElse(false.B) 557 this.fpWen := source.fpWen.getOrElse(false.B) 558 this.vecWen := source.vecWen.getOrElse(false.B) 559 this.pdest := source.pdest 560 this.data := source.data 561 this.robIdx := source.robIdx 562 this.flushPipe := source.flushPipe.getOrElse(false.B) 563 this.replayInst := source.replay.getOrElse(false.B) 564 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 565 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 566 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 567 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 568 this.debug := source.debug 569 this.debugInfo := source.debugInfo 570 } 571 572 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 573 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 574 rfWrite.wen := this.rfWen && fire 575 rfWrite.addr := this.pdest 576 rfWrite.data := this.data 577 rfWrite.intWen := this.rfWen 578 rfWrite.fpWen := false.B 579 rfWrite.vecWen := false.B 580 rfWrite 581 } 582 583 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 584 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 585 rfWrite.wen := (this.fpWen || this.vecWen) && fire 586 rfWrite.addr := this.pdest 587 rfWrite.data := this.data 588 rfWrite.intWen := false.B 589 rfWrite.fpWen := this.fpWen 590 rfWrite.vecWen := this.vecWen 591 rfWrite 592 } 593 } 594 595 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 596 // / 597 // [IssueQueue]--> ExuInput -- 598 class ExuBypassBundle( 599 val params: ExeUnitParams, 600 )(implicit 601 val p: Parameters 602 ) extends Bundle { 603 val data = UInt(params.dataBitsMax.W) 604 val pdest = UInt(params.wbPregIdxWidth.W) 605 } 606 607 class ExceptionInfo extends Bundle { 608 val pc = UInt(VAddrData().dataWidth.W) 609 val instr = UInt(32.W) 610 val commitType = CommitType() 611 val exceptionVec = ExceptionVec() 612 val singleStep = Bool() 613 val crossPageIPFFix = Bool() 614 val isInterrupt = Bool() 615 } 616 617 object UopIdx { 618 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 619 } 620 621 object FuLatency { 622 def apply(): UInt = UInt(width.W) 623 624 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 625 } 626 627 object ExuVec { 628 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 629 630 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 631 632 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 633 } 634 635 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 636 val uop = new DynInst 637 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 638 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 639 val isFirstIssue = Bool() 640 } 641 642 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 643 val uop = new DynInst 644 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 645 val debug = new DebugBundle 646 } 647 648 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 649 val uop = new DynInst 650 val flag = UInt(1.W) 651 } 652} 653