1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, IssueQueueJumpBundle, SchedulerType, EntryDeqRespBundle} 19import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 20import xiangshan.backend.rob.RobPtr 21import xiangshan.frontend._ 22import xiangshan.mem.{LqPtr, SqPtr} 23 24object Bundles { 25 26 // frontend -> backend 27 class StaticInst(implicit p: Parameters) extends XSBundle { 28 val instr = UInt(32.W) 29 val pc = UInt(VAddrBits.W) 30 val foldpc = UInt(MemPredPCWidth.W) 31 val exceptionVec = ExceptionVec() 32 val trigger = new TriggerCf 33 val preDecodeInfo = new PreDecodeInfo 34 val pred_taken = Bool() 35 val crossPageIPFFix = Bool() 36 val ftqPtr = new FtqPtr 37 val ftqOffset = UInt(log2Up(PredictWidth).W) 38 39 def connectCtrlFlow(source: CtrlFlow): Unit = { 40 this.instr := source.instr 41 this.pc := source.pc 42 this.foldpc := source.foldpc 43 this.exceptionVec := source.exceptionVec 44 this.trigger := source.trigger 45 this.preDecodeInfo := source.pd 46 this.pred_taken := source.pred_taken 47 this.crossPageIPFFix := source.crossPageIPFFix 48 this.ftqPtr := source.ftqPtr 49 this.ftqOffset := source.ftqOffset 50 } 51 } 52 53 // StaticInst --[Decode]--> DecodedInst 54 class DecodedInst(implicit p: Parameters) extends XSBundle { 55 def numSrc = backendParams.numSrc 56 // passed from StaticInst 57 val instr = UInt(32.W) 58 val pc = UInt(VAddrBits.W) 59 val foldpc = UInt(MemPredPCWidth.W) 60 val exceptionVec = ExceptionVec() 61 val trigger = new TriggerCf 62 val preDecodeInfo = new PreDecodeInfo 63 val pred_taken = Bool() 64 val crossPageIPFFix = Bool() 65 val ftqPtr = new FtqPtr 66 val ftqOffset = UInt(log2Up(PredictWidth).W) 67 // decoded 68 val srcType = Vec(numSrc, SrcType()) 69 val lsrc = Vec(numSrc, UInt(6.W)) 70 val ldest = UInt(6.W) 71 val fuType = FuType() 72 val fuOpType = FuOpType() 73 val rfWen = Bool() 74 val fpWen = Bool() 75 val vecWen = Bool() 76 val isXSTrap = Bool() 77 val waitForward = Bool() // no speculate execution 78 val blockBackward = Bool() 79 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 80 val canRobCompress = Bool() 81 val selImm = SelImm() 82 val imm = UInt(ImmUnion.maxLen.W) 83 val fpu = new FPUCtrlSignals 84 val vpu = new VPUCtrlSignals 85 val wfflags = Bool() 86 val isMove = Bool() 87 val uopIdx = UInt(5.W) 88 val uopSplitType = UopSplitType() 89 val isVset = Bool() 90 val firstUop = Bool() 91 val lastUop = Bool() 92 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 93 val commitType = CommitType() // Todo: remove it 94 95 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 96 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 97 98 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 99 val decoder: Seq[UInt] = ListLookup( 100 inst, XDecode.decodeDefault.map(bitPatToUInt), 101 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 102 ) 103 allSignals zip decoder foreach { case (s, d) => s := d } 104 this 105 } 106 107 def isSoftPrefetch: Bool = { 108 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 109 } 110 111 def connectStaticInst(source: StaticInst): Unit = { 112 for ((name, data) <- this.elements) { 113 if (source.elements.contains(name)) { 114 data := source.elements(name) 115 } 116 } 117 } 118 } 119 120 // DecodedInst --[Rename]--> DynInst 121 class DynInst(implicit p: Parameters) extends XSBundle { 122 def numSrc = backendParams.numSrc 123 // passed from StaticInst 124 val instr = UInt(32.W) 125 val pc = UInt(VAddrBits.W) 126 val foldpc = UInt(MemPredPCWidth.W) 127 val exceptionVec = ExceptionVec() 128 val trigger = new TriggerCf 129 val preDecodeInfo = new PreDecodeInfo 130 val pred_taken = Bool() 131 val crossPageIPFFix = Bool() 132 val ftqPtr = new FtqPtr 133 val ftqOffset = UInt(log2Up(PredictWidth).W) 134 // passed from DecodedInst 135 val srcType = Vec(numSrc, SrcType()) 136 val lsrc = Vec(numSrc, UInt(6.W)) 137 val ldest = UInt(6.W) 138 val fuType = FuType() 139 val fuOpType = FuOpType() 140 val rfWen = Bool() 141 val fpWen = Bool() 142 val vecWen = Bool() 143 val isXSTrap = Bool() 144 val waitForward = Bool() // no speculate execution 145 val blockBackward = Bool() 146 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 147 val canRobCompress = Bool() 148 val selImm = SelImm() 149 val imm = UInt(XLEN.W) // Todo: check if it need minimized 150 val fpu = new FPUCtrlSignals 151 val vpu = new VPUCtrlSignals 152 val wfflags = Bool() 153 val isMove = Bool() 154 val uopIdx = UInt(5.W) 155 val isVset = Bool() 156 val firstUop = Bool() 157 val lastUop = Bool() 158 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 159 val commitType = CommitType() 160 // rename 161 val srcState = Vec(numSrc, SrcState()) 162 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 163 val pdest = UInt(PhyRegIdxWidth.W) 164 val robIdx = new RobPtr 165 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 166 167 val eliminatedMove = Bool() 168 // Take snapshot at this CFI inst 169 val snapshot = Bool() 170 val debugInfo = new PerfDebugInfo 171 val storeSetHit = Bool() // inst has been allocated an store set 172 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 173 // Load wait is needed 174 // load inst will not be executed until former store (predicted by mdp) addr calcuated 175 val loadWaitBit = Bool() 176 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 177 // load inst will not be executed until ALL former store addr calcuated 178 val loadWaitStrict = Bool() 179 val ssid = UInt(SSIDWidth.W) 180 // Todo 181 val lqIdx = new LqPtr 182 val sqIdx = new SqPtr 183 // debug module 184 val singleStep = Bool() 185 // schedule 186 val replayInst = Bool() 187 188 def isLUI: Bool = this.fuType === FuType.alu.U && this.selImm === SelImm.IMM_U 189 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 190 191 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 192 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 193 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 194 195 def srcIsReady: Vec[Bool] = { 196 VecInit(this.srcType.zip(this.srcState).map { 197 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 198 }) 199 } 200 201 def clearExceptions( 202 exceptionBits: Seq[Int] = Seq(), 203 flushPipe : Boolean = false, 204 replayInst : Boolean = false 205 ): DynInst = { 206 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 207 if (!flushPipe) { this.flushPipe := false.B } 208 if (!replayInst) { this.replayInst := false.B } 209 this 210 } 211 212 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen 213 } 214 215 trait BundleSource { 216 var wakeupSource = "undefined" 217 var idx = 0 218 } 219 220 /** 221 * 222 * @param pregIdxWidth index width of preg 223 * @param exuIndices exu indices of wakeup bundle 224 */ 225 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int]) extends Bundle { 226 val rfWen = Bool() 227 val fpWen = Bool() 228 val vecWen = Bool() 229 val pdest = UInt(pregIdxWidth.W) 230 231 /** 232 * @param successor Seq[(psrc, srcType)] 233 * @return Seq[if wakeup psrc] 234 */ 235 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 236 successor.map { case (thatPsrc, srcType) => 237 val pdestMatch = pdest === thatPsrc 238 pdestMatch && ( 239 SrcType.isFp(srcType) && this.fpWen || 240 SrcType.isXp(srcType) && this.rfWen || 241 SrcType.isVp(srcType) && this.vecWen 242 ) && valid 243 } 244 } 245 246 def hasOnlyOneSource: Boolean = exuIndices.size == 1 247 248 def hasMultiSources: Boolean = exuIndices.size > 1 249 250 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 251 252 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 253 254 def exuIdx: Int = { 255 require(hasOnlyOneSource) 256 this.exuIndices.head 257 } 258 } 259 260 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 261 262 } 263 264 class IssueQueueIQWakeUpBundle(exuIdx: Int, backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 265 def fromExuInput(exuInput: ExuInput, l2ExuVecs: Vec[Vec[Bool]]): Unit = { 266 this.rfWen := exuInput.rfWen.getOrElse(false.B) 267 this.fpWen := exuInput.fpWen.getOrElse(false.B) 268 this.vecWen := exuInput.vecWen.getOrElse(false.B) 269 this.pdest := exuInput.pdest 270 } 271 272 def fromExuInput(exuInput: ExuInput): Unit = { 273 this.rfWen := exuInput.rfWen.getOrElse(false.B) 274 this.fpWen := exuInput.fpWen.getOrElse(false.B) 275 this.vecWen := exuInput.vecWen.getOrElse(false.B) 276 this.pdest := exuInput.pdest 277 } 278 } 279 280 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 281 // vtype 282 val vill = Bool() 283 val vma = Bool() // 1: agnostic, 0: undisturbed 284 val vta = Bool() // 1: agnostic, 0: undisturbed 285 val vsew = VSew() 286 val vlmul = VLmul() // 1/8~8 --> -3~3 287 288 val vm = Bool() // 0: need v0.t 289 val vstart = Vl() 290 291 // float rounding mode 292 val frm = Frm() 293 // scalar float instr 294 val fpu = Fpu() 295 // vector fix int rounding mode 296 val vxrm = Vxrm() 297 // vector uop index, exclude other non-vector uop 298 val vuopIdx = UopIdx() 299 // maybe used if data dependancy 300 val vmask = UInt(MaskSrcData().dataWidth.W) 301 val vl = Vl() 302 303 // vector load/store 304 val nf = Nf() 305 306 val needScalaSrc = Bool() 307 val permImmTruncate = Bool() // opivi 308 309 val isReverse = Bool() // vrsub, vrdiv 310 val isExt = Bool() 311 val isNarrow = Bool() 312 val isDstMask = Bool() // vvm, vvvm, mmm 313 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 314 315 def vtype: VType = { 316 val res = Wire(VType()) 317 res.illegal := this.vill 318 res.vma := this.vma 319 res.vta := this.vta 320 res.vsew := this.vsew 321 res.vlmul := this.vlmul 322 res 323 } 324 325 def vconfig: VConfig = { 326 val res = Wire(VConfig()) 327 res.vtype := this.vtype 328 res.vl := this.vl 329 res 330 } 331 } 332 333 // DynInst --[IssueQueue]--> DataPath 334 class IssueQueueIssueBundle( 335 iqParams: IssueBlockParams, 336 val exuParams: ExeUnitParams, 337 )(implicit 338 p: Parameters 339 ) extends Bundle { 340 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 341 342 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 343 rfReadDataCfgSet.map((set: Set[DataConfig]) => 344 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 345 ) 346 )) 347 348 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 349 val immType = SelImm() // used to select imm extractor 350 val common = new ExuInput(exuParams) 351 val jmp = if (exuParams.needPc) Some(Flipped(new IssueQueueJumpBundle)) else None 352 val addrOH = UInt(iqParams.numEntries.W) 353 354 def exuIdx = exuParams.exuIdx 355 def getSource: SchedulerType = exuParams.getWBSource 356 def getIntWbBusyBundle = common.rfWen.toSeq 357 def getVfWbBusyBundle = common.getVfWen.toSeq 358 def getIntRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readInt) 359 def getVfRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readVf) 360 361 def getIntRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 362 getIntRfReadBundle.zip(srcType).map { 363 case (rfRd: RfReadPortWithConfig, t: UInt) => 364 makeValid(issueValid && SrcType.isXp(t), rfRd) 365 } 366 } 367 368 def getVfRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 369 getVfRfReadBundle.zip(srcType).map { 370 case (rfRd: RfReadPortWithConfig, t: UInt) => 371 makeValid(issueValid && SrcType.isVfp(t), rfRd) 372 } 373 } 374 375 def getIntRfWriteValidBundle(issueValid: Bool) = { 376 377 } 378 } 379 380 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 381 val issueQueueParams = this.params 382 val og0resp = Valid(new EntryDeqRespBundle) 383 val og1resp = Valid(new EntryDeqRespBundle) 384 } 385 386 class fuBusyRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 387 val respType = RSFeedbackType() // update credit if needs replay 388 val rfWen = Bool() // TODO: use params to identify IntWB/VfWB 389 val fuType = FuType() 390 } 391 392 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 393 private val intCertainLat = params.intLatencyCertain 394 private val vfCertainLat = params.vfLatencyCertain 395 private val intLat = params.intLatencyValMax 396 private val vfLat = params.vfLatencyValMax 397 398 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 399 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 400 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 401 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 402 } 403 404 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 405 private val intCertainLat = params.intLatencyCertain 406 private val vfCertainLat = params.vfLatencyCertain 407 private val intLat = params.intLatencyValMax 408 private val vfLat = params.vfLatencyValMax 409 410 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 411 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 412 } 413 414 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 415 private val intCertainLat = params.intLatencyCertain 416 private val vfCertainLat = params.vfLatencyCertain 417 418 val intConflict = OptionWrapper(intCertainLat, Bool()) 419 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 420 } 421 422 // DataPath --[ExuInput]--> Exu 423 class ExuInput(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 424 val fuType = FuType() 425 val fuOpType = FuOpType() 426 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 427 val imm = UInt(XLEN.W) 428 val robIdx = new RobPtr 429 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 430 val isFirstIssue = Bool() // Only used by store yet 431 val pdest = UInt(params.wbPregIdxWidth.W) 432 val rfWen = if (params.writeIntRf) Some(Bool()) else None 433 val fpWen = if (params.writeFpRf) Some(Bool()) else None 434 val vecWen = if (params.writeVecRf) Some(Bool()) else None 435 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 436 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 437 val flushPipe = if (params.flushPipe) Some(Bool()) else None 438 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 439 val jalrTarget = if (params.hasJmpFu) Some(UInt(VAddrData().dataWidth.W)) else None 440 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 441 val ftqIdx = if (params.needPc || params.replayInst) 442 Some(new FtqPtr) else None 443 val ftqOffset = if (params.needPc || params.replayInst) 444 Some(UInt(log2Up(PredictWidth).W)) else None 445 val predictInfo = if (params.hasPredecode) Some(new Bundle { 446 val target = UInt(VAddrData().dataWidth.W) 447 val taken = Bool() 448 }) else None 449 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 450 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 451 val dataSources = Vec(params.numRegSrc, DataSource()) 452 val l1ExuVec = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuVec())) 453 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 454 455 def exuIdx = this.params.exuIdx 456 457 def needCancel(og0CancelVec: Vec[Bool], og1CancelVec: Vec[Bool]) : Bool = { 458 if (params.isIQWakeUpSink) { 459 require( 460 og0CancelVec.size == l1ExuVec.get.head.size, 461 s"cancelVecSize: {og0: ${og0CancelVec.size}, og1: ${og1CancelVec.size}}" 462 ) 463 val l1Cancel: Bool = l1ExuVec.get.zip(srcTimer.get).map { 464 case(exuOH: Vec[Bool], srcTimer: UInt) => 465 (exuOH.asUInt & og0CancelVec.asUInt).orR && srcTimer === 1.U 466 }.reduce(_ | _) 467 l1Cancel 468 } else { 469 false.B 470 } 471 } 472 473 def getVfWen = { 474 if (params.writeFpRf) this.fpWen 475 else if(params.writeVecRf) this.vecWen 476 else None 477 } 478 479 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 480 // src is assigned to rfReadData 481 this.fuType := source.common.fuType 482 this.fuOpType := source.common.fuOpType 483 this.imm := source.common.imm 484 this.robIdx := source.common.robIdx 485 this.pdest := source.common.pdest 486 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 487 this.iqIdx := source.common.iqIdx // Only used by mem feedback 488 this.dataSources := source.common.dataSources 489 this.rfWen .foreach(_ := source.common.rfWen.get) 490 this.fpWen .foreach(_ := source.common.fpWen.get) 491 this.vecWen .foreach(_ := source.common.vecWen.get) 492 this.fpu .foreach(_ := source.common.fpu.get) 493 this.vpu .foreach(_ := source.common.vpu.get) 494 this.flushPipe .foreach(_ := source.common.flushPipe.get) 495 this.pc .foreach(_ := source.jmp.get.pc) 496 this.jalrTarget .foreach(_ := source.jmp.get.target) 497 this.preDecode .foreach(_ := source.common.preDecode.get) 498 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 499 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 500 this.predictInfo .foreach(_ := source.common.predictInfo.get) 501 this.lqIdx .foreach(_ := source.common.lqIdx.get) 502 this.sqIdx .foreach(_ := source.common.sqIdx.get) 503 this.l1ExuVec .foreach(_ := source.common.l1ExuVec.get) 504 this.srcTimer .foreach(_ := source.common.srcTimer.get) 505 } 506 } 507 508 // ExuInput --[FuncUnit]--> ExuOutput 509 class ExuOutput( 510 val params: ExeUnitParams, 511 )(implicit 512 val p: Parameters 513 ) extends Bundle with BundleSource with HasXSParameter { 514 val data = UInt(params.dataBitsMax.W) 515 val pdest = UInt(params.wbPregIdxWidth.W) 516 val robIdx = new RobPtr 517 val intWen = if (params.writeIntRf) Some(Bool()) else None 518 val fpWen = if (params.writeFpRf) Some(Bool()) else None 519 val vecWen = if (params.writeVecRf) Some(Bool()) else None 520 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 521 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 522 val wflags = if (params.writeFflags) Some(Bool()) else None 523 val vxsat = if (params.writeVxsat) Some(Bool()) else None 524 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 525 val flushPipe = if (params.flushPipe) Some(Bool()) else None 526 val replay = if (params.replayInst) Some(Bool()) else None 527 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 528 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 529 Some(new SqPtr()) else None 530 val ftqIdx = if (params.needPc || params.replayInst) 531 Some(new FtqPtr) else None 532 val ftqOffset = if (params.needPc || params.replayInst) 533 Some(UInt(log2Up(PredictWidth).W)) else None 534 // uop info 535 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 536 val debug = new DebugBundle 537 val debugInfo = new PerfDebugInfo 538 } 539 540 // ExuOutput + DynInst --> WriteBackBundle 541 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 542 val rfWen = Bool() 543 val fpWen = Bool() 544 val vecWen = Bool() 545 val pdest = UInt(params.pregIdxWidth(backendParams).W) 546 val data = UInt(params.dataWidth.W) 547 val robIdx = new RobPtr()(p) 548 val flushPipe = Bool() 549 val replayInst = Bool() 550 val redirect = ValidIO(new Redirect) 551 val fflags = UInt(5.W) 552 val vxsat = Bool() 553 val exceptionVec = ExceptionVec() 554 val debug = new DebugBundle 555 val debugInfo = new PerfDebugInfo 556 557 this.wakeupSource = s"WB(${params.toString})" 558 559 def fromExuOutput(source: ExuOutput) = { 560 this.rfWen := source.intWen.getOrElse(false.B) 561 this.fpWen := source.fpWen.getOrElse(false.B) 562 this.vecWen := source.vecWen.getOrElse(false.B) 563 this.pdest := source.pdest 564 this.data := source.data 565 this.robIdx := source.robIdx 566 this.flushPipe := source.flushPipe.getOrElse(false.B) 567 this.replayInst := source.replay.getOrElse(false.B) 568 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 569 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 570 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 571 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 572 this.debug := source.debug 573 this.debugInfo := source.debugInfo 574 } 575 576 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 577 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 578 rfWrite.wen := this.rfWen && fire 579 rfWrite.addr := this.pdest 580 rfWrite.data := this.data 581 rfWrite.intWen := this.rfWen 582 rfWrite.fpWen := false.B 583 rfWrite.vecWen := false.B 584 rfWrite 585 } 586 587 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 588 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 589 rfWrite.wen := (this.fpWen || this.vecWen) && fire 590 rfWrite.addr := this.pdest 591 rfWrite.data := this.data 592 rfWrite.intWen := false.B 593 rfWrite.fpWen := this.fpWen 594 rfWrite.vecWen := this.vecWen 595 rfWrite 596 } 597 } 598 599 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 600 // / 601 // [IssueQueue]--> ExuInput -- 602 class ExuBypassBundle( 603 val params: ExeUnitParams, 604 )(implicit 605 val p: Parameters 606 ) extends Bundle { 607 val data = UInt(params.dataBitsMax.W) 608 val pdest = UInt(params.wbPregIdxWidth.W) 609 } 610 611 class ExceptionInfo extends Bundle { 612 val pc = UInt(VAddrData().dataWidth.W) 613 val instr = UInt(32.W) 614 val commitType = CommitType() 615 val exceptionVec = ExceptionVec() 616 val singleStep = Bool() 617 val crossPageIPFFix = Bool() 618 val isInterrupt = Bool() 619 } 620 621 object UopIdx { 622 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 623 } 624 625 object FuLatency { 626 def apply(): UInt = UInt(width.W) 627 628 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 629 } 630 631 object ExuVec { 632 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 633 634 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 635 636 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 637 } 638 639 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 640 val uop = new DynInst 641 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 642 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 643 val isFirstIssue = Bool() 644 } 645 646 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 647 val uop = new DynInst 648 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 649 val debug = new DebugBundle 650 } 651 652 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 653 val uop = new DynInst 654 val flag = UInt(1.W) 655 } 656} 657