1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.OptionWrapper 8import xiangshan._ 9import xiangshan.backend.datapath.DataConfig._ 10import xiangshan.backend.datapath.DataSource 11import xiangshan.backend.datapath.WbConfig.WbConfig 12import xiangshan.backend.decode.{ImmUnion, XDecode} 13import xiangshan.backend.exu.ExeUnitParams 14import xiangshan.backend.fu.FuType 15import xiangshan.backend.fu.fpu.Bundles.Frm 16import xiangshan.backend.fu.vector.Bundles.{Category, Nf, VConfig, VLmul, VSew, VType, Vl, Vxrm} 17import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, IssueQueueJumpBundle, SchedulerType, StatusArrayDeqRespBundle} 18import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 19import xiangshan.backend.rob.RobPtr 20import xiangshan.frontend._ 21import xiangshan.mem.{LqPtr, SqPtr} 22 23object Bundles { 24 25 // frontend -> backend 26 class StaticInst(implicit p: Parameters) extends XSBundle { 27 val instr = UInt(32.W) 28 val pc = UInt(VAddrBits.W) 29 val foldpc = UInt(MemPredPCWidth.W) 30 val exceptionVec = ExceptionVec() 31 val trigger = new TriggerCf 32 val preDecodeInfo = new PreDecodeInfo 33 val pred_taken = Bool() 34 val crossPageIPFFix = Bool() 35 val ftqPtr = new FtqPtr 36 val ftqOffset = UInt(log2Up(PredictWidth).W) 37 38 def connectCtrlFlow(source: CtrlFlow): Unit = { 39 this.instr := source.instr 40 this.pc := source.pc 41 this.foldpc := source.foldpc 42 this.exceptionVec := source.exceptionVec 43 this.trigger := source.trigger 44 this.preDecodeInfo := source.pd 45 this.pred_taken := source.pred_taken 46 this.crossPageIPFFix := source.crossPageIPFFix 47 this.ftqPtr := source.ftqPtr 48 this.ftqOffset := source.ftqOffset 49 } 50 } 51 52 // StaticInst --[Decode]--> DecodedInst 53 class DecodedInst(implicit p: Parameters) extends XSBundle { 54 def numSrc = backendParams.numSrc 55 // passed from StaticInst 56 val instr = UInt(32.W) 57 val pc = UInt(VAddrBits.W) 58 val foldpc = UInt(MemPredPCWidth.W) 59 val exceptionVec = ExceptionVec() 60 val trigger = new TriggerCf 61 val preDecodeInfo = new PreDecodeInfo 62 val pred_taken = Bool() 63 val crossPageIPFFix = Bool() 64 val ftqPtr = new FtqPtr 65 val ftqOffset = UInt(log2Up(PredictWidth).W) 66 // decoded 67 val srcType = Vec(numSrc, SrcType()) 68 val lsrc = Vec(numSrc, UInt(6.W)) 69 val ldest = UInt(6.W) 70 val fuType = FuType() 71 val fuOpType = FuOpType() 72 val rfWen = Bool() 73 val fpWen = Bool() 74 val vecWen = Bool() 75 val isXSTrap = Bool() 76 val waitForward = Bool() // no speculate execution 77 val blockBackward = Bool() 78 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 79 val selImm = SelImm() 80 val imm = UInt(ImmUnion.maxLen.W) 81 val fpu = new FPUCtrlSignals 82 val vpu = new VPUCtrlSignals 83 val isMove = Bool() 84 val uopIdx = UInt(5.W) 85 val uopSplitType = UopSplitType() 86 val isVset = Bool() 87 val firstUop = Bool() 88 val lastUop = Bool() 89 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 90 val commitType = CommitType() // Todo: remove it 91 92 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 93 isXSTrap, waitForward, blockBackward, flushPipe, uopSplitType, selImm) 94 95 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 96 val decoder: Seq[UInt] = ListLookup( 97 inst, XDecode.decodeDefault.map(bitPatToUInt), 98 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 99 ) 100 allSignals zip decoder foreach { case (s, d) => s := d } 101 this 102 } 103 104 def isSoftPrefetch: Bool = { 105 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 106 } 107 108 def connectStaticInst(source: StaticInst): Unit = { 109 for ((name, data) <- this.elements) { 110 if (source.elements.contains(name)) { 111 data := source.elements(name) 112 } 113 } 114 } 115 } 116 117 // DecodedInst --[Rename]--> DynInst 118 class DynInst(implicit p: Parameters) extends XSBundle { 119 def numSrc = backendParams.numSrc 120 // passed from StaticInst 121 val instr = UInt(32.W) 122 val pc = UInt(VAddrBits.W) 123 val foldpc = UInt(MemPredPCWidth.W) 124 val exceptionVec = ExceptionVec() 125 val trigger = new TriggerCf 126 val preDecodeInfo = new PreDecodeInfo 127 val pred_taken = Bool() 128 val crossPageIPFFix = Bool() 129 val ftqPtr = new FtqPtr 130 val ftqOffset = UInt(log2Up(PredictWidth).W) 131 // passed from DecodedInst 132 val srcType = Vec(numSrc, SrcType()) 133 val lsrc = Vec(numSrc, UInt(6.W)) 134 val ldest = UInt(6.W) 135 val fuType = FuType() 136 val fuOpType = FuOpType() 137 val rfWen = Bool() 138 val fpWen = Bool() 139 val vecWen = Bool() 140 val isXSTrap = Bool() 141 val waitForward = Bool() // no speculate execution 142 val blockBackward = Bool() 143 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 144 val selImm = SelImm() 145 val imm = UInt(XLEN.W) // Todo: check if it need minimized 146 val fpu = new FPUCtrlSignals 147 val vpu = new VPUCtrlSignals 148 val isMove = Bool() 149 val uopIdx = UInt(5.W) 150 val isVset = Bool() 151 val firstUop = Bool() 152 val lastUop = Bool() 153 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 154 val commitType = CommitType() 155 // rename 156 val srcState = Vec(numSrc, SrcState()) 157 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 158 val pdest = UInt(PhyRegIdxWidth.W) 159 val oldPdest = UInt(PhyRegIdxWidth.W) 160 val robIdx = new RobPtr 161 162 val eliminatedMove = Bool() 163 val debugInfo = new PerfDebugInfo 164 val storeSetHit = Bool() // inst has been allocated an store set 165 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 166 // Load wait is needed 167 // load inst will not be executed until former store (predicted by mdp) addr calcuated 168 val loadWaitBit = Bool() 169 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 170 // load inst will not be executed until ALL former store addr calcuated 171 val loadWaitStrict = Bool() 172 val ssid = UInt(SSIDWidth.W) 173 // Todo 174 val lqIdx = new LqPtr 175 val sqIdx = new SqPtr 176 // debug module 177 val singleStep = Bool() 178 // schedule 179 val replayInst = Bool() 180 181 def isLUI: Bool = this.fuType === FuType.alu.U && this.selImm === SelImm.IMM_U 182 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 183 184 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 185 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 186 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 187 188 def srcIsReady: Vec[Bool] = { 189 VecInit(this.srcType.zip(this.srcState).map { 190 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 191 }) 192 } 193 194 def clearExceptions( 195 exceptionBits: Seq[Int] = Seq(), 196 flushPipe : Boolean = false, 197 replayInst : Boolean = false 198 ): DynInst = { 199 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 200 if (!flushPipe) { this.flushPipe := false.B } 201 if (!replayInst) { this.replayInst := false.B } 202 this 203 } 204 205 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen 206 } 207 208 trait BundleSource { 209 var wakeupSource = "undefined" 210 var idx = 0 211 } 212 213 /** 214 * 215 * @param pregIdxWidth index width of preg 216 * @param exuIndices exu indices of wakeup bundle 217 */ 218 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int]) extends Bundle { 219 val rfWen = Bool() 220 val fpWen = Bool() 221 val vecWen = Bool() 222 val pdest = UInt(pregIdxWidth.W) 223 224 /** 225 * @param successor Seq[(psrc, srcType)] 226 * @return Seq[if wakeup psrc] 227 */ 228 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 229 successor.map { case (thatPsrc, srcType) => 230 val pdestMatch = pdest === thatPsrc 231 pdestMatch && ( 232 SrcType.isFp(srcType) && this.fpWen || 233 SrcType.isXp(srcType) && this.rfWen || 234 SrcType.isVp(srcType) && this.vecWen 235 ) && valid 236 } 237 } 238 239 def hasOnlyOneSource: Boolean = exuIndices.size == 1 240 241 def hasMultiSources: Boolean = exuIndices.size > 1 242 243 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 244 245 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 246 247 def exuIdx: Int = { 248 require(hasOnlyOneSource) 249 this.exuIndices.head 250 } 251 } 252 253 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 254 255 } 256 257 class IssueQueueIQWakeUpBundle(exuIdx: Int, backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 258 def fromExuInput(exuInput: ExuInput, l2ExuVecs: Vec[Vec[Bool]]): Unit = { 259 this.rfWen := exuInput.rfWen.getOrElse(false.B) 260 this.fpWen := exuInput.fpWen.getOrElse(false.B) 261 this.vecWen := exuInput.vecWen.getOrElse(false.B) 262 this.pdest := exuInput.pdest 263 } 264 265 def fromExuInput(exuInput: ExuInput): Unit = { 266 this.rfWen := exuInput.rfWen.getOrElse(false.B) 267 this.fpWen := exuInput.fpWen.getOrElse(false.B) 268 this.vecWen := exuInput.vecWen.getOrElse(false.B) 269 this.pdest := exuInput.pdest 270 } 271 } 272 273 /** 274 * This bundle is used to set srcState as NotReady. 275 * @param cancelSeq cancel stage seq 276 */ 277 class IssueQueueCancelBundle(val exuIdx: Int, cancelSeq: Seq[String]) extends Bundle { 278 val cancelVec: Vec[Bool] = Vec(cancelSeq.size, Bool()) 279 280 def apply(cancelStage: String): Bool = { 281 this.cancelVec(cancelSeq.indexOf(cancelStage.toUpperCase)) 282 } 283 } 284 285 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 286 // vtype 287 val vill = Bool() 288 val vma = Bool() // 1: agnostic, 0: undisturbed 289 val vta = Bool() // 1: agnostic, 0: undisturbed 290 val vsew = VSew() 291 val vlmul = VLmul() // 1/8~8 --> -3~3 292 293 val vm = Bool() // 0: need v0.t 294 val vstart = Vl() 295 296 // float rounding mode 297 val frm = Frm() 298 // vector fix int rounding mode 299 val vxrm = Vxrm() 300 // vector uop index, exclude other non-vector uop 301 val vuopIdx = UopIdx() 302 // maybe used if data dependancy 303 val vmask = UInt(MaskSrcData().dataWidth.W) 304 val vl = Vl() 305 306 // vector load/store 307 val nf = Nf() 308 309 val needScalaSrc = Bool() 310 val permImmTruncate = Bool() // opivi 311 312 val isReverse = Bool() // vrsub, vrdiv 313 val isExt = Bool() 314 val isNarrow = Bool() 315 val isDstMask = Bool() // vvm, vvvm, mmm 316 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 317 318 def vtype: VType = { 319 val res = Wire(VType()) 320 res.illegal := this.vill 321 res.vma := this.vma 322 res.vta := this.vta 323 res.vsew := this.vsew 324 res.vlmul := this.vlmul 325 res 326 } 327 328 def vconfig: VConfig = { 329 val res = Wire(VConfig()) 330 res.vtype := this.vtype 331 res.vl := this.vl 332 res 333 } 334 } 335 336 // DynInst --[IssueQueue]--> DataPath 337 class IssueQueueIssueBundle( 338 iqParams: IssueBlockParams, 339 exuParams: ExeUnitParams, 340 addrWidth: Int, 341 vaddrBits: Int 342 )(implicit 343 p: Parameters 344 ) extends Bundle { 345 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 346 347 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 348 rfReadDataCfgSet.map((set: Set[DataConfig]) => 349 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, addrWidth)).toSeq) 350 ) 351 )) 352 353 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 354 val immType = SelImm() // used to select imm extractor 355 val common = new ExuInput(exuParams) 356 val jmp = if (exuParams.needPc) Some(Flipped(new IssueQueueJumpBundle)) else None 357 val addrOH = UInt(iqParams.numEntries.W) 358 359 def exuIdx = exuParams.exuIdx 360 def getSource: SchedulerType = exuParams.getWBSource 361 def getIntWbBusyBundle = common.rfWen.toSeq 362 def getVfWbBusyBundle = common.getVfWen.toSeq 363 def getIntRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readInt) 364 def getVfRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readVf) 365 } 366 367 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 368 val issueQueueParams = this.params 369 val og0resp = Valid(new StatusArrayDeqRespBundle) 370 val og1resp = Valid(new StatusArrayDeqRespBundle) 371 } 372 373 class fuBusyRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 374 val respType = RSFeedbackType() // update credit if needs replay 375 val rfWen = Bool() // TODO: use params to identify IntWB/VfWB 376 val fuType = FuType() 377 } 378 379 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 380 private val intCertainLat = params.intLatencyCertain 381 private val vfCertainLat = params.vfLatencyCertain 382 private val intLat = params.intLatencyValMax 383 private val vfLat = params.vfLatencyValMax 384 385 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 386 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 387 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 388 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 389 } 390 391 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 392 private val intCertainLat = params.intLatencyCertain 393 private val vfCertainLat = params.vfLatencyCertain 394 private val intLat = params.intLatencyValMax 395 private val vfLat = params.vfLatencyValMax 396 397 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 398 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 399 } 400 401 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 402 private val intCertainLat = params.intLatencyCertain 403 private val vfCertainLat = params.vfLatencyCertain 404 405 val intConflict = OptionWrapper(intCertainLat, Bool()) 406 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 407 } 408 409 // DataPath --[ExuInput]--> Exu 410 class ExuInput(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 411 val fuType = FuType() 412 val fuOpType = FuOpType() 413 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 414 val imm = UInt(XLEN.W) 415 val robIdx = new RobPtr 416 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 417 val isFirstIssue = Bool() // Only used by store yet 418 val pdest = UInt(params.wbPregIdxWidth.W) 419 val rfWen = if (params.writeIntRf) Some(Bool()) else None 420 val fpWen = if (params.writeFpRf) Some(Bool()) else None 421 val vecWen = if (params.writeVecRf) Some(Bool()) else None 422 val fpu = if (params.needFPUCtrl) Some(new FPUCtrlSignals) else None 423 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 424 val flushPipe = if (params.flushPipe) Some(Bool()) else None 425 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 426 val jalrTarget = if (params.hasJmpFu) Some(UInt(VAddrData().dataWidth.W)) else None 427 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 428 val ftqIdx = if (params.needPc || params.replayInst) 429 Some(new FtqPtr) else None 430 val ftqOffset = if (params.needPc || params.replayInst) 431 Some(UInt(log2Up(PredictWidth).W)) else None 432 val predictInfo = if (params.hasPredecode) Some(new Bundle { 433 val target = UInt(VAddrData().dataWidth.W) 434 val taken = Bool() 435 }) else None 436 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 437 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 438 val dataSources = Vec(params.numRegSrc, DataSource()) 439 val l1ExuVec = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuVec())) 440 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 441 442 def exuIdx = this.params.exuIdx 443 444 def needCancel(og0CancelVec: Vec[Bool], og1CancelVec: Vec[Bool]) : Bool = { 445 if (params.isIQWakeUpSink) { 446 require( 447 og0CancelVec.size == l1ExuVec.get.head.size, 448 s"cancelVecSize: {og0: ${og0CancelVec.size}, og1: ${og1CancelVec.size}}" 449 ) 450 val l1Cancel: Bool = l1ExuVec.get.zip(srcTimer.get).map { 451 case(exuOH: Vec[Bool], srcTimer: UInt) => 452 (exuOH.asUInt & og0CancelVec.asUInt).orR && srcTimer === 1.U 453 }.reduce(_ | _) 454 l1Cancel 455 } else { 456 false.B 457 } 458 } 459 460 def getVfWen = { 461 if (params.writeFpRf) this.fpWen 462 else if(params.writeVecRf) this.vecWen 463 else None 464 } 465 466 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 467 // src is assigned to rfReadData 468 this.fuType := source.common.fuType 469 this.fuOpType := source.common.fuOpType 470 this.imm := source.common.imm 471 this.robIdx := source.common.robIdx 472 this.pdest := source.common.pdest 473 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 474 this.iqIdx := source.common.iqIdx // Only used by mem feedback 475 this.dataSources := source.common.dataSources 476 this.rfWen .foreach(_ := source.common.rfWen.get) 477 this.fpWen .foreach(_ := source.common.fpWen.get) 478 this.vecWen .foreach(_ := source.common.vecWen.get) 479 this.fpu .foreach(_ := source.common.fpu.get) 480 this.vpu .foreach(_ := source.common.vpu.get) 481 this.flushPipe .foreach(_ := source.common.flushPipe.get) 482 this.pc .foreach(_ := source.jmp.get.pc) 483 this.jalrTarget .foreach(_ := source.jmp.get.target) 484 this.preDecode .foreach(_ := source.common.preDecode.get) 485 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 486 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 487 this.predictInfo .foreach(_ := source.common.predictInfo.get) 488 this.lqIdx .foreach(_ := source.common.lqIdx.get) 489 this.sqIdx .foreach(_ := source.common.sqIdx.get) 490 this.l1ExuVec .foreach(_ := source.common.l1ExuVec.get) 491 this.srcTimer .foreach(_ := source.common.srcTimer.get) 492 } 493 } 494 495 // ExuInput --[FuncUnit]--> ExuOutput 496 class ExuOutput( 497 val params: ExeUnitParams, 498 )(implicit 499 val p: Parameters 500 ) extends Bundle with BundleSource with HasXSParameter { 501 val data = UInt(params.dataBitsMax.W) 502 val pdest = UInt(params.wbPregIdxWidth.W) 503 val robIdx = new RobPtr 504 val intWen = if (params.writeIntRf) Some(Bool()) else None 505 val fpWen = if (params.writeFpRf) Some(Bool()) else None 506 val vecWen = if (params.writeVecRf) Some(Bool()) else None 507 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 508 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 509 val vxsat = if (params.writeVxsat) Some(Bool()) else None 510 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 511 val flushPipe = if (params.flushPipe) Some(Bool()) else None 512 val replay = if (params.replayInst) Some(Bool()) else None 513 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 514 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 515 Some(new SqPtr()) else None 516 val ftqIdx = if (params.needPc || params.replayInst) 517 Some(new FtqPtr) else None 518 val ftqOffset = if (params.needPc || params.replayInst) 519 Some(UInt(log2Up(PredictWidth).W)) else None 520 // uop info 521 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 522 val debug = new DebugBundle 523 val debugInfo = new PerfDebugInfo 524 } 525 526 // ExuOutput + DynInst --> WriteBackBundle 527 class WriteBackBundle(val params: WbConfig)(implicit p: Parameters) extends Bundle with BundleSource { 528 val rfWen = Bool() 529 val fpWen = Bool() 530 val vecWen = Bool() 531 val pdest = UInt(params.pregIdxWidth.W) 532 val data = UInt(params.dataWidth.W) 533 val robIdx = new RobPtr()(p) 534 val flushPipe = Bool() 535 val replayInst = Bool() 536 val redirect = ValidIO(new Redirect) 537 val fflags = UInt(5.W) 538 val vxsat = Bool() 539 val exceptionVec = ExceptionVec() 540 val debug = new DebugBundle 541 val debugInfo = new PerfDebugInfo 542 543 this.wakeupSource = s"WB(${params.toString})" 544 545 def fromExuOutput(source: ExuOutput) = { 546 this.rfWen := source.intWen.getOrElse(false.B) 547 this.fpWen := source.fpWen.getOrElse(false.B) 548 this.vecWen := source.vecWen.getOrElse(false.B) 549 this.pdest := source.pdest 550 this.data := source.data 551 this.robIdx := source.robIdx 552 this.flushPipe := source.flushPipe.getOrElse(false.B) 553 this.replayInst := source.replay.getOrElse(false.B) 554 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 555 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 556 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 557 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 558 this.debug := source.debug 559 this.debugInfo := source.debugInfo 560 } 561 562 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 563 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, this.params.pregIdxWidth))) 564 rfWrite.wen := this.rfWen && fire 565 rfWrite.addr := this.pdest 566 rfWrite.data := this.data 567 rfWrite.intWen := this.rfWen 568 rfWrite.fpWen := false.B 569 rfWrite.vecWen := false.B 570 rfWrite 571 } 572 573 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 574 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, this.params.pregIdxWidth))) 575 rfWrite.wen := (this.fpWen || this.vecWen) && fire 576 rfWrite.addr := this.pdest 577 rfWrite.data := this.data 578 rfWrite.intWen := false.B 579 rfWrite.fpWen := this.fpWen 580 rfWrite.vecWen := this.vecWen 581 rfWrite 582 } 583 } 584 585 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 586 // / 587 // [IssueQueue]--> ExuInput -- 588 class ExuBypassBundle( 589 val params: ExeUnitParams, 590 )(implicit 591 val p: Parameters 592 ) extends Bundle { 593 val data = UInt(params.dataBitsMax.W) 594 val pdest = UInt(params.wbPregIdxWidth.W) 595 } 596 597 class ExceptionInfo extends Bundle { 598 val pc = UInt(VAddrData().dataWidth.W) 599 val instr = UInt(32.W) 600 val commitType = CommitType() 601 val exceptionVec = ExceptionVec() 602 val singleStep = Bool() 603 val crossPageIPFFix = Bool() 604 val isInterrupt = Bool() 605 } 606 607 object UopIdx { 608 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 609 } 610 611 object FuLatency { 612 def apply(): UInt = UInt(width.W) 613 614 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 615 } 616 617 object ExuVec { 618 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 619 620 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 621 622 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 623 } 624 625 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 626 val uop = new DynInst 627 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 628 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 629 val isFirstIssue = Bool() 630 } 631 632 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 633 val uop = new DynInst 634 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 635 val debug = new DebugBundle 636 } 637 638 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 639 val uop = new DynInst 640 val flag = UInt(1.W) 641 } 642} 643