Parameters: support 2 vlsu

Parameters: fix VFEX1's vf read port number

Rename: VecLogicRegs change to 32+15

Decode: add V0_IDX Vl_IDX

RegFile: change VlLogicRegs to 1

Backend: vfexu add V0WB VlWB

Backend: vfexu add V0RD VlRD

Rename: add parameters V0LogicRegs VlLogicRegs

Rename: v0 vl split

Backend: add some basic signals for v0 & vl split

Backend: reduce IQ entries for fix timing

Backend: change intRegfile read write port for better timing and performance

Parameters: remove one vector load/store RS (#3015)

This commit remove one vector load/store RS, which is for timing.

Backend: refactor fpSchdParams for 4 pipe

Parameters: refactor L2 prefetch parameters (#2996)

Now bop/receiver/tp are decoupled

Parameters, FuConfig: add FpWB port for Vfalu to execute v2f uops

Merge branch 'master' into vlsu-merge-master-0504

Add CoupledL2 with CHI interface (#2953)

This pull request introduces TL2CHICoupledL2, which adopts TileLink
standard to connect L1 DCache/ICache/PTW, and CHI Issue B specification
to connect down

Add CoupledL2 with CHI interface (#2953)

This pull request introduces TL2CHICoupledL2, which adopts TileLink
standard to connect L1 DCache/ICache/PTW, and CHI Issue B specification
to connect downstream interconnect. The key features of TL2CHICoupledL2
are:
* Fully coherent Request Node in a CHI interconnect.
* Coherency granule of 64B cache line.
* MESI cache coherence model, which is based on TileLink coherence
policies.
* Transition from TL-C transactions to CHI snoopable requests.
* Transition from TL-UL transactions to CHI non-snoopable requests.
* Support for ReadNoSnp, ReadNotSharedDirty, ReadUnique, MakeUnique.
* Support for WriteNoSnp, WriteBackFull, Evict.
* Support for all the snoops except for SnpDVMOp.
* Request retry to manage protocol resources.
* Message transfer across CHI interfaces based on Link Layer Credit.
* Power aware signaling on the component interface.

The original CoupledL2 is now renamed to TL2TLCoupledL2. TL2TLCoupledL2
still works as default L2 Cache instance in
[XiangShan](https://github.com/OpenXiangShan/XiangShan) processor for
now. TL2CHICoupledL2 is still not available for verilator simulation in
this pr.

To compile XSTile verilog with TL2CHICoupledL2, run `make verilog
CONFIG=KunminghuV2Config RELEASE_ARGS MFC=1`.

---------

Signed-off-by: Yangyu Chen <[email protected]>
Co-authored-by: Zhu Yu <[email protected]>
Co-authored-by: Tang Haojin <[email protected]>
Co-authored-by: Yangyu Chen <[email protected]>

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VLSU: Set two vlsu issuequeues as default

Backend: split vector load/store FuType by is segment or not

args: modify the optional configuration of the run command (#2984)

Configure restgen as an optional option. RESETGEN is disabled by default
on palladium. It should be noted that multi-core XIANGSHA

args: modify the optional configuration of the run command (#2984)

Configure restgen as an optional option. RESETGEN is disabled by default
on palladium. It should be noted that multi-core XIANGSHAN cannot be
started after enabling RESETGEN, which may still be bug.

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Merge branch 'master' into vlsu-merge-master-0504

Wakeup: add fp wakeup, remove vf to std wakeup

Backend: i2f and fdiv use same write port

Backend: change fp write port