1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import freechips.rocketchip.tile.MaxHartIdBits 42import system.SoCParamsKey 43import huancun._ 44import huancun.debug._ 45import xiangshan.cache.wpu.WPUParameters 46import coupledL2._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.min 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBits: Int = 39, 72 GPAddrBits: Int = 41, 73 HasFPU: Boolean = true, 74 HasVPU: Boolean = true, 75 HasCustomCSRCacheOp: Boolean = true, 76 FetchWidth: Int = 8, 77 AsidLength: Int = 16, 78 VmidLength: Int = 14, 79 EnableBPU: Boolean = true, 80 EnableBPD: Boolean = true, 81 EnableRAS: Boolean = true, 82 EnableLB: Boolean = false, 83 EnableLoop: Boolean = true, 84 EnableSC: Boolean = true, 85 EnbaleTlbDebug: Boolean = false, 86 EnableClockGate: Boolean = true, 87 EnableJal: Boolean = false, 88 EnableFauFTB: Boolean = true, 89 UbtbGHRLength: Int = 4, 90 // HistoryLength: Int = 512, 91 EnableGHistDiff: Boolean = true, 92 EnableCommitGHistDiff: Boolean = true, 93 UbtbSize: Int = 256, 94 FtbSize: Int = 2048, 95 RasSize: Int = 16, 96 RasSpecSize: Int = 32, 97 RasCtrSize: Int = 3, 98 CacheLineSize: Int = 512, 99 FtbWays: Int = 4, 100 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 101 // Sets Hist Tag 102 Seq(( 4096, 8, 8), 103 ( 4096, 13, 8), 104 ( 4096, 32, 8), 105 ( 4096, 119, 8)), 106 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 107 // Sets Hist Tag 108 Seq(( 256, 4, 9), 109 ( 256, 8, 9), 110 ( 512, 13, 9), 111 ( 512, 16, 9), 112 ( 512, 32, 9)), 113 SCNRows: Int = 512, 114 SCNTables: Int = 4, 115 SCCtrBits: Int = 6, 116 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 117 numBr: Int = 2, 118 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 119 (resp_in: BranchPredictionResp, p: Parameters) => { 120 val ftb = Module(new FTB()(p)) 121 val uftb = Module(new FauFTB()(p)) 122 val tage = Module(new Tage_SC()(p)) 123 val ras = Module(new RAS()(p)) 124 val ittage = Module(new ITTage()(p)) 125 val preds = Seq(uftb, tage, ftb, ittage, ras) 126 preds.map(_.io := DontCare) 127 128 uftb.io.in.bits.resp_in(0) := resp_in 129 tage.io.in.bits.resp_in(0) := uftb.io.out 130 ftb.io.in.bits.resp_in(0) := tage.io.out 131 ittage.io.in.bits.resp_in(0) := ftb.io.out 132 ras.io.in.bits.resp_in(0) := ittage.io.out 133 134 (preds, ras.io.out) 135 }, 136 ICacheECCForceError: Boolean = false, 137 IBufSize: Int = 48, 138 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 139 DecodeWidth: Int = 6, 140 RenameWidth: Int = 6, 141 CommitWidth: Int = 8, 142 RobCommitWidth: Int = 8, 143 RabCommitWidth: Int = 6, 144 MaxUopSize: Int = 65, 145 EnableRenameSnapshot: Boolean = true, 146 RenameSnapshotNum: Int = 4, 147 FtqSize: Int = 64, 148 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 149 IntLogicRegs: Int = 32, 150 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 151 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 152 VCONFIG_IDX: Int = 32, 153 NRPhyRegs: Int = 192, 154 VirtualLoadQueueSize: Int = 72, 155 LoadQueueRARSize: Int = 72, 156 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 157 RollbackGroupSize: Int = 8, 158 LoadQueueReplaySize: Int = 72, 159 LoadUncacheBufferSize: Int = 20, 160 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 161 StoreQueueSize: Int = 64, 162 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 163 StoreQueueForwardWithMask: Boolean = true, 164 VlsQueueSize: Int = 8, 165 RobSize: Int = 160, 166 RabSize: Int = 256, 167 VTypeBufferSize: Int = 64, // used to reorder vtype 168 IssueQueueSize: Int = 24, 169 IssueQueueCompEntrySize: Int = 16, 170 dpParams: DispatchParameters = DispatchParameters( 171 IntDqSize = 16, 172 FpDqSize = 16, 173 LsDqSize = 18, 174 IntDqDeqWidth = 8, 175 FpDqDeqWidth = 6, 176 VecDqDeqWidth = 6, 177 LsDqDeqWidth = 6, 178 ), 179 intPreg: PregParams = IntPregParams( 180 numEntries = 224, 181 numRead = None, 182 numWrite = None, 183 ), 184 fpPreg: PregParams = FpPregParams( 185 numEntries = 192, 186 numRead = None, 187 numWrite = None, 188 ), 189 vfPreg: VfPregParams = VfPregParams( 190 numEntries = 128, 191 numRead = None, 192 numWrite = None, 193 ), 194 v0Preg: V0PregParams = V0PregParams( 195 numEntries = 22, 196 numRead = None, 197 numWrite = None, 198 ), 199 vlPreg: VlPregParams = VlPregParams( 200 numEntries = 32, 201 numRead = None, 202 numWrite = None, 203 ), 204 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 205 LoadPipelineWidth: Int = 3, 206 StorePipelineWidth: Int = 2, 207 VecLoadPipelineWidth: Int = 1, 208 VecStorePipelineWidth: Int = 1, 209 VecMemSrcInWidth: Int = 2, 210 VecMemInstWbWidth: Int = 1, 211 VecMemDispatchWidth: Int = 1, 212 VecMemDispatchMaxNumber: Int = 16, 213 StoreBufferSize: Int = 16, 214 StoreBufferThreshold: Int = 7, 215 EnsbufferWidth: Int = 2, 216 LoadDependencyWidth: Int = 2, 217 // ============ VLSU ============ 218 VlMergeBufferSize: Int = 16, 219 VsMergeBufferSize: Int = 16, 220 UopWritebackWidth: Int = 1, 221 VLUopWritebackWidth: Int = 1, 222 VSUopWritebackWidth: Int = 1, 223 SplitBufferSize: Int = 8, 224 VSegmentBufferSize: Int = 8, 225 // ============================== 226 UncacheBufferSize: Int = 4, 227 EnableLoadToLoadForward: Boolean = false, 228 EnableFastForward: Boolean = true, 229 EnableLdVioCheckAfterReset: Boolean = true, 230 EnableSoftPrefetchAfterReset: Boolean = true, 231 EnableCacheErrorAfterReset: Boolean = true, 232 EnableAccurateLoadError: Boolean = true, 233 EnableUncacheWriteOutstanding: Boolean = false, 234 EnableStorePrefetchAtIssue: Boolean = false, 235 EnableStorePrefetchAtCommit: Boolean = false, 236 EnableAtCommitMissTrigger: Boolean = true, 237 EnableStorePrefetchSMS: Boolean = false, 238 EnableStorePrefetchSPB: Boolean = false, 239 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 240 MMUVmidLen: Int = 14, 241 ReSelectLen: Int = 7, // load replay queue replay select counter len 242 iwpuParameters: WPUParameters = WPUParameters( 243 enWPU = false, 244 algoName = "mmru", 245 isICache = true, 246 ), 247 dwpuParameters: WPUParameters = WPUParameters( 248 enWPU = false, 249 algoName = "mmru", 250 enCfPred = false, 251 isICache = false, 252 ), 253 itlbParameters: TLBParameters = TLBParameters( 254 name = "itlb", 255 fetchi = true, 256 useDmode = false, 257 NWays = 48, 258 ), 259 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 260 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 261 ldtlbParameters: TLBParameters = TLBParameters( 262 name = "ldtlb", 263 NWays = 48, 264 outReplace = false, 265 partialStaticPMP = true, 266 outsideRecvFlush = true, 267 saveLevel = true, 268 lgMaxSize = 4 269 ), 270 sttlbParameters: TLBParameters = TLBParameters( 271 name = "sttlb", 272 NWays = 48, 273 outReplace = false, 274 partialStaticPMP = true, 275 outsideRecvFlush = true, 276 saveLevel = true, 277 lgMaxSize = 4 278 ), 279 hytlbParameters: TLBParameters = TLBParameters( 280 name = "hytlb", 281 NWays = 48, 282 outReplace = false, 283 partialStaticPMP = true, 284 outsideRecvFlush = true, 285 saveLevel = true, 286 lgMaxSize = 4 287 ), 288 pftlbParameters: TLBParameters = TLBParameters( 289 name = "pftlb", 290 NWays = 48, 291 outReplace = false, 292 partialStaticPMP = true, 293 outsideRecvFlush = true, 294 saveLevel = true, 295 lgMaxSize = 4 296 ), 297 l2ToL1tlbParameters: TLBParameters = TLBParameters( 298 name = "l2tlb", 299 NWays = 48, 300 outReplace = false, 301 partialStaticPMP = true, 302 outsideRecvFlush = true, 303 saveLevel = true 304 ), 305 refillBothTlb: Boolean = false, 306 btlbParameters: TLBParameters = TLBParameters( 307 name = "btlb", 308 NWays = 48, 309 ), 310 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 311 NumPerfCounters: Int = 16, 312 icacheParameters: ICacheParameters = ICacheParameters( 313 tagECC = Some("parity"), 314 dataECC = Some("parity"), 315 replacer = Some("setplru"), 316 nMissEntries = 2, 317 nProbeEntries = 2, 318 nPrefetchEntries = 12, 319 nPrefBufferEntries = 32, 320 ), 321 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 322 tagECC = Some("secded"), 323 dataECC = Some("secded"), 324 replacer = Some("setplru"), 325 nMissEntries = 16, 326 nProbeEntries = 8, 327 nReleaseEntries = 18, 328 nMaxPrefetchEntry = 6, 329 )), 330 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 331 name = "l2", 332 ways = 8, 333 sets = 1024, // default 512KB L2 334 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 335 coupledL2.prefetch.TPParameters()), 336 )), 337 L2NBanks: Int = 1, 338 usePTWRepeater: Boolean = false, 339 softTLB: Boolean = false, // dpi-c l1tlb debug only 340 softPTW: Boolean = false, // dpi-c l2tlb debug only 341 softPTWDelay: Int = 1 342){ 343 def vlWidth = log2Up(VLEN) + 1 344 345 /** 346 * the minimum element length of vector elements 347 */ 348 val minVecElen: Int = 8 349 350 /** 351 * the maximum number of elements in vector register 352 */ 353 val maxElemPerVreg: Int = VLEN / minVecElen 354 355 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 356 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 357 358 val intSchdParams = { 359 implicit val schdType: SchedulerType = IntScheduler() 360 SchdBlockParams(Seq( 361 IssueBlockParams(Seq( 362 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 363 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(1, 1))), true, 2), 364 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 365 IssueBlockParams(Seq( 366 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 367 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(3, 1))), true, 2), 368 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 369 IssueBlockParams(Seq( 370 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 371 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 4, 0), FpWB(port = 4, 0), VfWB(1, 1)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(5, 1)))), 372 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 373 IssueBlockParams(Seq( 374 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 375 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(7, 1)))), 376 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 377 ), 378 numPregs = intPreg.numEntries, 379 numDeqOutside = 0, 380 schdType = schdType, 381 rfDataWidth = intPreg.dataCfg.dataWidth, 382 numUopIn = dpParams.IntDqDeqWidth, 383 ) 384 } 385 386 val fpSchdParams = { 387 implicit val schdType: SchedulerType = FpScheduler() 388 SchdBlockParams(Seq( 389 IssueBlockParams(Seq( 390 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 1, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 391 ), numEntries = 18, numEnq = 2, numComp = 16), 392 IssueBlockParams(Seq( 393 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 394 ), numEntries = 18, numEnq = 2, numComp = 16), 395 IssueBlockParams(Seq( 396 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 397 ), numEntries = 18, numEnq = 2, numComp = 16), 398 IssueBlockParams(Seq( 399 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 400 ), numEntries = 18, numEnq = 2, numComp = 16), 401 IssueBlockParams(Seq( 402 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 403 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 404 ), numEntries = 18, numEnq = 2, numComp = 16), 405 ), 406 numPregs = fpPreg.numEntries, 407 numDeqOutside = 0, 408 schdType = schdType, 409 rfDataWidth = fpPreg.dataCfg.dataWidth, 410 numUopIn = dpParams.VecDqDeqWidth, 411 ) 412 } 413 414 val vfSchdParams = { 415 implicit val schdType: SchedulerType = VfScheduler() 416 SchdBlockParams(Seq( 417 IssueBlockParams(Seq( 418 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 1, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 419 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 2, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 420 ), numEntries = 16, numEnq = 2, numComp = 14), 421 IssueBlockParams(Seq( 422 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 3, 0)), Seq(Seq(VfRD(7, 1)), Seq(VfRD(8, 1)), Seq(VfRD(9, 1)), Seq(VfRD(5, 1)), Seq(VfRD(6, 1)))), 423 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 4, 0), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)))), 424 ), numEntries = 16, numEnq = 2, numComp = 14), 425 IssueBlockParams(Seq( 426 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(0, 2)), Seq(VfRD(1, 2)), Seq(VfRD(2, 2)))), 427 ), numEntries = 16, numEnq = 2, numComp = 14), 428 ), 429 numPregs = vfPreg.numEntries, 430 numDeqOutside = 0, 431 schdType = schdType, 432 rfDataWidth = vfPreg.dataCfg.dataWidth, 433 numUopIn = dpParams.VecDqDeqWidth, 434 ) 435 } 436 437 val memSchdParams = { 438 implicit val schdType: SchedulerType = MemScheduler() 439 val rfDataWidth = 64 440 441 SchdBlockParams(Seq( 442 IssueBlockParams(Seq( 443 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(11, 1)))), 444 ), numEntries = 16, numEnq = 2, numComp = 14), 445 IssueBlockParams(Seq( 446 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(8, 1)))), 447 ), numEntries = 16, numEnq = 2, numComp = 14), 448 IssueBlockParams(Seq( 449 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 450 ), numEntries = 16, numEnq = 2, numComp = 14), 451 IssueBlockParams(Seq( 452 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 453 ), numEntries = 16, numEnq = 2, numComp = 14), 454 IssueBlockParams(Seq( 455 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 456 ), numEntries = 16, numEnq = 2, numComp = 14), 457 IssueBlockParams(Seq( 458 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(0, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(VfRD(12, 0)), Seq(VfRD(13, 0)), Seq(VfRD(14, 0)))), 459 ), numEntries = 16, numEnq = 2, numComp = 14), 460 IssueBlockParams(Seq( 461 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(10, 1), FpRD(12, 0)))), 462 ), numEntries = 16, numEnq = 2, numComp = 14), 463 IssueBlockParams(Seq( 464 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(11, 1), FpRD(13, 0)))), 465 ), numEntries = 16, numEnq = 2, numComp = 14), 466 ), 467 numPregs = intPreg.numEntries max vfPreg.numEntries, 468 numDeqOutside = 0, 469 schdType = schdType, 470 rfDataWidth = rfDataWidth, 471 numUopIn = dpParams.LsDqDeqWidth, 472 ) 473 } 474 475 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 476 477 def iqWakeUpParams = { 478 Seq( 479 WakeUpConfig( 480 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 481 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 482 ), 483 WakeUpConfig( 484 Seq("FEX0", "FEX1", "FEX2", "FEX3", "LDU0", "LDU1", "LDU2") -> 485 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 486 ), 487 WakeUpConfig( 488 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 489 Seq("STD0", "STD1") 490 ), 491 WakeUpConfig( 492 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 493 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "VFEX4") 494 ), 495 ).flatten 496 } 497 498 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 499 500 val backendParams: BackendParams = backend.BackendParams( 501 Map( 502 IntScheduler() -> intSchdParams, 503 FpScheduler() -> fpSchdParams, 504 VfScheduler() -> vfSchdParams, 505 MemScheduler() -> memSchdParams, 506 ), 507 Seq( 508 intPreg, 509 fpPreg, 510 vfPreg, 511 v0Preg, 512 vlPreg, 513 fakeIntPreg 514 ), 515 iqWakeUpParams, 516 ) 517} 518 519case object DebugOptionsKey extends Field[DebugOptions] 520 521case class DebugOptions 522( 523 FPGAPlatform: Boolean = false, 524 ResetGen: Boolean = false, 525 EnableDifftest: Boolean = false, 526 AlwaysBasicDiff: Boolean = true, 527 EnableDebug: Boolean = false, 528 EnablePerfDebug: Boolean = true, 529 UseDRAMSim: Boolean = false, 530 EnableConstantin: Boolean = false, 531 EnableChiselDB: Boolean = false, 532 AlwaysBasicDB: Boolean = true, 533 EnableTopDown: Boolean = false, 534 EnableRollingDB: Boolean = false 535) 536 537trait HasXSParameter { 538 539 implicit val p: Parameters 540 541 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 542 def NodeIDWidth = p(SoCParamsKey).NodeIDWidth // NodeID width among NoC 543 544 def coreParams = p(XSCoreParamsKey) 545 def env = p(DebugOptionsKey) 546 547 def XLEN = coreParams.XLEN 548 def VLEN = coreParams.VLEN 549 def ELEN = coreParams.ELEN 550 def HSXLEN = coreParams.HSXLEN 551 val minFLen = 32 552 val fLen = 64 553 def hartIdLen = p(MaxHartIdBits) 554 val xLen = XLEN 555 556 def HasMExtension = coreParams.HasMExtension 557 def HasCExtension = coreParams.HasCExtension 558 def HasHExtension = coreParams.HasHExtension 559 def HasDiv = coreParams.HasDiv 560 def HasIcache = coreParams.HasICache 561 def HasDcache = coreParams.HasDCache 562 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 563 def GPAddrBits = coreParams.GPAddrBits 564 def VAddrBits = { 565 if(HasHExtension){ 566 coreParams.GPAddrBits 567 }else{ 568 coreParams.VAddrBits 569 } 570 } // VAddrBits is Virtual Memory addr bits 571 572 def AsidLength = coreParams.AsidLength 573 def VmidLength = coreParams.VmidLength 574 def ReSelectLen = coreParams.ReSelectLen 575 def AddrBytes = AddrBits / 8 // unused 576 def DataBits = XLEN 577 def DataBytes = DataBits / 8 578 def VDataBytes = VLEN / 8 579 def HasFPU = coreParams.HasFPU 580 def HasVPU = coreParams.HasVPU 581 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 582 def FetchWidth = coreParams.FetchWidth 583 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 584 def EnableBPU = coreParams.EnableBPU 585 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 586 def EnableRAS = coreParams.EnableRAS 587 def EnableLB = coreParams.EnableLB 588 def EnableLoop = coreParams.EnableLoop 589 def EnableSC = coreParams.EnableSC 590 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 591 def HistoryLength = coreParams.HistoryLength 592 def EnableGHistDiff = coreParams.EnableGHistDiff 593 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 594 def EnableClockGate = coreParams.EnableClockGate 595 def UbtbGHRLength = coreParams.UbtbGHRLength 596 def UbtbSize = coreParams.UbtbSize 597 def EnableFauFTB = coreParams.EnableFauFTB 598 def FtbSize = coreParams.FtbSize 599 def FtbWays = coreParams.FtbWays 600 def RasSize = coreParams.RasSize 601 def RasSpecSize = coreParams.RasSpecSize 602 def RasCtrSize = coreParams.RasCtrSize 603 604 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 605 coreParams.branchPredictor(resp_in, p) 606 } 607 def numBr = coreParams.numBr 608 def TageTableInfos = coreParams.TageTableInfos 609 def TageBanks = coreParams.numBr 610 def SCNRows = coreParams.SCNRows 611 def SCCtrBits = coreParams.SCCtrBits 612 def SCHistLens = coreParams.SCHistLens 613 def SCNTables = coreParams.SCNTables 614 615 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 616 case ((n, cb), h) => (n, cb, h) 617 } 618 def ITTageTableInfos = coreParams.ITTageTableInfos 619 type FoldedHistoryInfo = Tuple2[Int, Int] 620 def foldedGHistInfos = 621 (TageTableInfos.map{ case (nRows, h, t) => 622 if (h > 0) 623 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 624 else 625 Set[FoldedHistoryInfo]() 626 }.reduce(_++_).toSet ++ 627 SCTableInfos.map{ case (nRows, _, h) => 628 if (h > 0) 629 Set((h, min(log2Ceil(nRows/TageBanks), h))) 630 else 631 Set[FoldedHistoryInfo]() 632 }.reduce(_++_).toSet ++ 633 ITTageTableInfos.map{ case (nRows, h, t) => 634 if (h > 0) 635 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 636 else 637 Set[FoldedHistoryInfo]() 638 }.reduce(_++_) ++ 639 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 640 ).toList 641 642 643 644 def CacheLineSize = coreParams.CacheLineSize 645 def CacheLineHalfWord = CacheLineSize / 16 646 def ExtHistoryLength = HistoryLength + 64 647 def ICacheECCForceError = coreParams.ICacheECCForceError 648 def IBufSize = coreParams.IBufSize 649 def IBufNBank = coreParams.IBufNBank 650 def backendParams: BackendParams = coreParams.backendParams 651 def DecodeWidth = coreParams.DecodeWidth 652 def RenameWidth = coreParams.RenameWidth 653 def CommitWidth = coreParams.CommitWidth 654 def RobCommitWidth = coreParams.RobCommitWidth 655 def RabCommitWidth = coreParams.RabCommitWidth 656 def MaxUopSize = coreParams.MaxUopSize 657 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 658 def RenameSnapshotNum = coreParams.RenameSnapshotNum 659 def FtqSize = coreParams.FtqSize 660 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 661 def IntLogicRegs = coreParams.IntLogicRegs 662 def FpLogicRegs = coreParams.FpLogicRegs 663 def VecLogicRegs = coreParams.VecLogicRegs 664 def VCONFIG_IDX = coreParams.VCONFIG_IDX 665 def IntPhyRegs = coreParams.intPreg.numEntries 666 def FpPhyRegs = coreParams.fpPreg.numEntries 667 def VfPhyRegs = coreParams.vfPreg.numEntries 668 def V0PhyRegs = coreParams.v0Preg.numEntries 669 def VlPhyRegs = coreParams.vlPreg.numEntries 670 def MaxPhyPregs = IntPhyRegs max VfPhyRegs 671 def PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 672 def RobSize = coreParams.RobSize 673 def RabSize = coreParams.RabSize 674 def VTypeBufferSize = coreParams.VTypeBufferSize 675 /** 676 * the minimum element length of vector elements 677 */ 678 def minVecElen: Int = coreParams.minVecElen 679 680 /** 681 * the maximum number of elements in vector register 682 */ 683 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 684 685 def IntRefCounterWidth = log2Ceil(RobSize) 686 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 687 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 688 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 689 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 690 def LoadQueueRARSize = coreParams.LoadQueueRARSize 691 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 692 def RollbackGroupSize = coreParams.RollbackGroupSize 693 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 694 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 695 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 696 def StoreQueueSize = coreParams.StoreQueueSize 697 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 698 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 699 def VlsQueueSize = coreParams.VlsQueueSize 700 def dpParams = coreParams.dpParams 701 702 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 703 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 704 705 def NumRedirect = backendParams.numRedirect 706 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 707 def FtqRedirectAheadNum = NumRedirect 708 def LoadPipelineWidth = coreParams.LoadPipelineWidth 709 def StorePipelineWidth = coreParams.StorePipelineWidth 710 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 711 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 712 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 713 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 714 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 715 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 716 def StoreBufferSize = coreParams.StoreBufferSize 717 def StoreBufferThreshold = coreParams.StoreBufferThreshold 718 def EnsbufferWidth = coreParams.EnsbufferWidth 719 def LoadDependencyWidth = coreParams.LoadDependencyWidth 720 def VlMergeBufferSize = coreParams.VlMergeBufferSize 721 def VsMergeBufferSize = coreParams.VsMergeBufferSize 722 def UopWritebackWidth = coreParams.UopWritebackWidth 723 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 724 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 725 def SplitBufferSize = coreParams.SplitBufferSize 726 def VSegmentBufferSize = coreParams.VSegmentBufferSize 727 def UncacheBufferSize = coreParams.UncacheBufferSize 728 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 729 def EnableFastForward = coreParams.EnableFastForward 730 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 731 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 732 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 733 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 734 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 735 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 736 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 737 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 738 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 739 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 740 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 741 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 742 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 743 def asidLen = coreParams.MMUAsidLen 744 def vmidLen = coreParams.MMUVmidLen 745 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 746 def refillBothTlb = coreParams.refillBothTlb 747 def iwpuParam = coreParams.iwpuParameters 748 def dwpuParam = coreParams.dwpuParameters 749 def itlbParams = coreParams.itlbParameters 750 def ldtlbParams = coreParams.ldtlbParameters 751 def sttlbParams = coreParams.sttlbParameters 752 def hytlbParams = coreParams.hytlbParameters 753 def pftlbParams = coreParams.pftlbParameters 754 def l2ToL1Params = coreParams.l2ToL1tlbParameters 755 def btlbParams = coreParams.btlbParameters 756 def l2tlbParams = coreParams.l2tlbParameters 757 def NumPerfCounters = coreParams.NumPerfCounters 758 759 def instBytes = if (HasCExtension) 2 else 4 760 def instOffsetBits = log2Ceil(instBytes) 761 762 def icacheParameters = coreParams.icacheParameters 763 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 764 765 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 766 // for constrained LR/SC loop 767 def LRSCCycles = 64 768 // for lr storm 769 def LRSCBackOff = 8 770 771 // cache hierarchy configurations 772 def l1BusDataWidth = 256 773 774 // load violation predict 775 def ResetTimeMax2Pow = 20 //1078576 776 def ResetTimeMin2Pow = 10 //1024 777 // wait table parameters 778 def WaitTableSize = 1024 779 def MemPredPCWidth = log2Up(WaitTableSize) 780 def LWTUse2BitCounter = true 781 // store set parameters 782 def SSITSize = WaitTableSize 783 def LFSTSize = 32 784 def SSIDWidth = log2Up(LFSTSize) 785 def LFSTWidth = 4 786 def StoreSetEnable = true // LWT will be disabled if SS is enabled 787 def LFSTEnable = true 788 789 def PCntIncrStep: Int = 6 790 def numPCntHc: Int = 25 791 def numPCntPtw: Int = 19 792 793 def numCSRPCntFrontend = 8 794 def numCSRPCntCtrl = 8 795 def numCSRPCntLsu = 8 796 def numCSRPCntHc = 5 797 def printEventCoding = true 798 799 // Parameters for Sdtrig extension 800 protected def TriggerNum = 4 801 protected def TriggerChainMaxLength = 2 802} 803