1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams, FakeIntPregParams, FpPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import freechips.rocketchip.tile.MaxHartIdBits 42import system.SoCParamsKey 43import huancun._ 44import huancun.debug._ 45import xiangshan.cache.wpu.WPUParameters 46import coupledL2._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.min 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBits: Int = 39, 72 GPAddrBits: Int = 41, 73 HasFPU: Boolean = true, 74 HasVPU: Boolean = true, 75 HasCustomCSRCacheOp: Boolean = true, 76 FetchWidth: Int = 8, 77 AsidLength: Int = 16, 78 VmidLength: Int = 14, 79 EnableBPU: Boolean = true, 80 EnableBPD: Boolean = true, 81 EnableRAS: Boolean = true, 82 EnableLB: Boolean = false, 83 EnableLoop: Boolean = true, 84 EnableSC: Boolean = true, 85 EnbaleTlbDebug: Boolean = false, 86 EnableClockGate: Boolean = true, 87 EnableJal: Boolean = false, 88 EnableFauFTB: Boolean = true, 89 UbtbGHRLength: Int = 4, 90 // HistoryLength: Int = 512, 91 EnableGHistDiff: Boolean = true, 92 EnableCommitGHistDiff: Boolean = true, 93 UbtbSize: Int = 256, 94 FtbSize: Int = 2048, 95 RasSize: Int = 16, 96 RasSpecSize: Int = 32, 97 RasCtrSize: Int = 3, 98 CacheLineSize: Int = 512, 99 FtbWays: Int = 4, 100 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 101 // Sets Hist Tag 102 Seq(( 4096, 8, 8), 103 ( 4096, 13, 8), 104 ( 4096, 32, 8), 105 ( 4096, 119, 8)), 106 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 107 // Sets Hist Tag 108 Seq(( 256, 4, 9), 109 ( 256, 8, 9), 110 ( 512, 13, 9), 111 ( 512, 16, 9), 112 ( 512, 32, 9)), 113 SCNRows: Int = 512, 114 SCNTables: Int = 4, 115 SCCtrBits: Int = 6, 116 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 117 numBr: Int = 2, 118 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 119 (resp_in: BranchPredictionResp, p: Parameters) => { 120 val ftb = Module(new FTB()(p)) 121 val uftb = Module(new FauFTB()(p)) 122 val tage = Module(new Tage_SC()(p)) 123 val ras = Module(new RAS()(p)) 124 val ittage = Module(new ITTage()(p)) 125 val preds = Seq(uftb, tage, ftb, ittage, ras) 126 preds.map(_.io := DontCare) 127 128 uftb.io.in.bits.resp_in(0) := resp_in 129 tage.io.in.bits.resp_in(0) := uftb.io.out 130 ftb.io.in.bits.resp_in(0) := tage.io.out 131 ittage.io.in.bits.resp_in(0) := ftb.io.out 132 ras.io.in.bits.resp_in(0) := ittage.io.out 133 134 (preds, ras.io.out) 135 }, 136 ICacheECCForceError: Boolean = false, 137 IBufSize: Int = 48, 138 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 139 DecodeWidth: Int = 6, 140 RenameWidth: Int = 6, 141 CommitWidth: Int = 8, 142 RobCommitWidth: Int = 8, 143 RabCommitWidth: Int = 6, 144 MaxUopSize: Int = 65, 145 EnableRenameSnapshot: Boolean = true, 146 RenameSnapshotNum: Int = 4, 147 FtqSize: Int = 64, 148 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 149 IntLogicRegs: Int = 32, 150 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 151 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 152 VCONFIG_IDX: Int = 32, 153 NRPhyRegs: Int = 192, 154 VirtualLoadQueueSize: Int = 72, 155 LoadQueueRARSize: Int = 72, 156 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 157 RollbackGroupSize: Int = 8, 158 LoadQueueReplaySize: Int = 72, 159 LoadUncacheBufferSize: Int = 20, 160 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 161 StoreQueueSize: Int = 64, 162 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 163 StoreQueueForwardWithMask: Boolean = true, 164 VlsQueueSize: Int = 8, 165 RobSize: Int = 160, 166 RabSize: Int = 256, 167 VTypeBufferSize: Int = 64, // used to reorder vtype 168 IssueQueueSize: Int = 24, 169 IssueQueueCompEntrySize: Int = 16, 170 dpParams: DispatchParameters = DispatchParameters( 171 IntDqSize = 16, 172 FpDqSize = 16, 173 LsDqSize = 18, 174 IntDqDeqWidth = 8, 175 FpDqDeqWidth = 6, 176 VecDqDeqWidth = 6, 177 LsDqDeqWidth = 6, 178 ), 179 intPreg: PregParams = IntPregParams( 180 numEntries = 224, 181 numRead = None, 182 numWrite = None, 183 ), 184 fpPreg: PregParams = FpPregParams( 185 numEntries = 192, 186 numRead = None, 187 numWrite = None, 188 ), 189 vfPreg: VfPregParams = VfPregParams( 190 numEntries = 128, 191 numRead = None, 192 numWrite = None, 193 ), 194 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 195 LoadPipelineWidth: Int = 3, 196 StorePipelineWidth: Int = 2, 197 VecLoadPipelineWidth: Int = 1, 198 VecStorePipelineWidth: Int = 1, 199 VecMemSrcInWidth: Int = 2, 200 VecMemInstWbWidth: Int = 1, 201 VecMemDispatchWidth: Int = 1, 202 VecMemDispatchMaxNumber: Int = 16, 203 StoreBufferSize: Int = 16, 204 StoreBufferThreshold: Int = 7, 205 EnsbufferWidth: Int = 2, 206 LoadDependencyWidth: Int = 2, 207 // ============ VLSU ============ 208 VlMergeBufferSize: Int = 16, 209 VsMergeBufferSize: Int = 16, 210 UopWritebackWidth: Int = 1, 211 VLUopWritebackWidth: Int = 1, 212 VSUopWritebackWidth: Int = 1, 213 SplitBufferSize: Int = 8, 214 VSegmentBufferSize: Int = 8, 215 // ============================== 216 UncacheBufferSize: Int = 4, 217 EnableLoadToLoadForward: Boolean = false, 218 EnableFastForward: Boolean = true, 219 EnableLdVioCheckAfterReset: Boolean = true, 220 EnableSoftPrefetchAfterReset: Boolean = true, 221 EnableCacheErrorAfterReset: Boolean = true, 222 EnableAccurateLoadError: Boolean = true, 223 EnableUncacheWriteOutstanding: Boolean = false, 224 EnableStorePrefetchAtIssue: Boolean = false, 225 EnableStorePrefetchAtCommit: Boolean = false, 226 EnableAtCommitMissTrigger: Boolean = true, 227 EnableStorePrefetchSMS: Boolean = false, 228 EnableStorePrefetchSPB: Boolean = false, 229 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 230 MMUVmidLen: Int = 14, 231 ReSelectLen: Int = 7, // load replay queue replay select counter len 232 iwpuParameters: WPUParameters = WPUParameters( 233 enWPU = false, 234 algoName = "mmru", 235 isICache = true, 236 ), 237 dwpuParameters: WPUParameters = WPUParameters( 238 enWPU = false, 239 algoName = "mmru", 240 enCfPred = false, 241 isICache = false, 242 ), 243 itlbParameters: TLBParameters = TLBParameters( 244 name = "itlb", 245 fetchi = true, 246 useDmode = false, 247 NWays = 48, 248 ), 249 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 250 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 251 ldtlbParameters: TLBParameters = TLBParameters( 252 name = "ldtlb", 253 NWays = 48, 254 outReplace = false, 255 partialStaticPMP = true, 256 outsideRecvFlush = true, 257 saveLevel = true, 258 lgMaxSize = 4 259 ), 260 sttlbParameters: TLBParameters = TLBParameters( 261 name = "sttlb", 262 NWays = 48, 263 outReplace = false, 264 partialStaticPMP = true, 265 outsideRecvFlush = true, 266 saveLevel = true, 267 lgMaxSize = 4 268 ), 269 hytlbParameters: TLBParameters = TLBParameters( 270 name = "hytlb", 271 NWays = 48, 272 outReplace = false, 273 partialStaticPMP = true, 274 outsideRecvFlush = true, 275 saveLevel = true, 276 lgMaxSize = 4 277 ), 278 pftlbParameters: TLBParameters = TLBParameters( 279 name = "pftlb", 280 NWays = 48, 281 outReplace = false, 282 partialStaticPMP = true, 283 outsideRecvFlush = true, 284 saveLevel = true, 285 lgMaxSize = 4 286 ), 287 l2ToL1tlbParameters: TLBParameters = TLBParameters( 288 name = "l2tlb", 289 NWays = 48, 290 outReplace = false, 291 partialStaticPMP = true, 292 outsideRecvFlush = true, 293 saveLevel = true 294 ), 295 refillBothTlb: Boolean = false, 296 btlbParameters: TLBParameters = TLBParameters( 297 name = "btlb", 298 NWays = 48, 299 ), 300 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 301 NumPerfCounters: Int = 16, 302 icacheParameters: ICacheParameters = ICacheParameters( 303 tagECC = Some("parity"), 304 dataECC = Some("parity"), 305 replacer = Some("setplru"), 306 nMissEntries = 2, 307 nProbeEntries = 2, 308 nPrefetchEntries = 12, 309 nPrefBufferEntries = 32, 310 ), 311 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 312 tagECC = Some("secded"), 313 dataECC = Some("secded"), 314 replacer = Some("setplru"), 315 nMissEntries = 16, 316 nProbeEntries = 8, 317 nReleaseEntries = 18, 318 nMaxPrefetchEntry = 6, 319 )), 320 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 321 name = "l2", 322 ways = 8, 323 sets = 1024, // default 512KB L2 324 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 325 coupledL2.prefetch.TPParameters()), 326 )), 327 L2NBanks: Int = 1, 328 usePTWRepeater: Boolean = false, 329 softTLB: Boolean = false, // dpi-c l1tlb debug only 330 softPTW: Boolean = false, // dpi-c l2tlb debug only 331 softPTWDelay: Int = 1 332){ 333 def vlWidth = log2Up(VLEN) + 1 334 335 /** 336 * the minimum element length of vector elements 337 */ 338 val minVecElen: Int = 8 339 340 /** 341 * the maximum number of elements in vector register 342 */ 343 val maxElemPerVreg: Int = VLEN / minVecElen 344 345 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 346 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 347 348 val intSchdParams = { 349 implicit val schdType: SchedulerType = IntScheduler() 350 SchdBlockParams(Seq( 351 IssueBlockParams(Seq( 352 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 353 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(7, 1))), true, 2), 354 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 355 IssueBlockParams(Seq( 356 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 357 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 2, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(5, 1))), true, 2), 358 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 359 IssueBlockParams(Seq( 360 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 361 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 0, 1), FpWB(port = 4, 0), VfWB(5, 1)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(3, 1)))), 362 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 363 IssueBlockParams(Seq( 364 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 365 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(1, 1)))), 366 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 367 ), 368 numPregs = intPreg.numEntries, 369 numDeqOutside = 0, 370 schdType = schdType, 371 rfDataWidth = intPreg.dataCfg.dataWidth, 372 numUopIn = dpParams.IntDqDeqWidth, 373 ) 374 } 375 376 val fpSchdParams = { 377 implicit val schdType: SchedulerType = FpScheduler() 378 SchdBlockParams(Seq( 379 IssueBlockParams(Seq( 380 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 1, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 381 ), numEntries = 18, numEnq = 2, numComp = 16), 382 IssueBlockParams(Seq( 383 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 384 ), numEntries = 18, numEnq = 2, numComp = 16), 385 IssueBlockParams(Seq( 386 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 387 ), numEntries = 18, numEnq = 2, numComp = 16), 388 IssueBlockParams(Seq( 389 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 390 ), numEntries = 18, numEnq = 2, numComp = 16), 391 IssueBlockParams(Seq( 392 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 393 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 394 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 395 ), 396 numPregs = fpPreg.numEntries, 397 numDeqOutside = 0, 398 schdType = schdType, 399 rfDataWidth = fpPreg.dataCfg.dataWidth, 400 numUopIn = dpParams.VecDqDeqWidth, 401 ) 402 } 403 404 val vfSchdParams = { 405 implicit val schdType: SchedulerType = VfScheduler() 406 SchdBlockParams(Seq( 407 IssueBlockParams(Seq( 408 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 409 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 5, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 410 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 411 IssueBlockParams(Seq( 412 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 6, 0)), Seq(Seq(VfRD(7, 1)), Seq(VfRD(8, 1)), Seq(VfRD(9, 1)), Seq(VfRD(5, 1)), Seq(VfRD(6, 1)))), 413 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 7, 0), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)))), 414 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 415 IssueBlockParams(Seq( 416 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 2, 0)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(0, 2)), Seq(VfRD(1, 2)), Seq(VfRD(2, 2)))), 417 ExeUnitParams("VFEX5", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 0)), Seq(Seq(VfRD(8, 2)), Seq(VfRD(9, 2)), Seq(VfRD(5, 2)), Seq(VfRD(6, 2)), Seq(VfRD(7, 2)))), 418 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 419 ), 420 numPregs = vfPreg.numEntries, 421 numDeqOutside = 0, 422 schdType = schdType, 423 rfDataWidth = vfPreg.dataCfg.dataWidth, 424 numUopIn = dpParams.VecDqDeqWidth, 425 ) 426 } 427 428 val memSchdParams = { 429 implicit val schdType: SchedulerType = MemScheduler() 430 val rfDataWidth = 64 431 432 SchdBlockParams(Seq( 433 IssueBlockParams(Seq( 434 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(8, 1)))), 435 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 436 IssueBlockParams(Seq( 437 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(9, 1)))), 438 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 439 IssueBlockParams(Seq( 440 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 441 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 442 IssueBlockParams(Seq( 443 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 444 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 445 IssueBlockParams(Seq( 446 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 447 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 448 IssueBlockParams(Seq( 449 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(0, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(VfRD(12, 0)), Seq(VfRD(13, 0)), Seq(VfRD(14, 0)))), 450 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 451 IssueBlockParams(Seq( 452 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(10, 1), FpRD(12, 0)))), 453 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 454 IssueBlockParams(Seq( 455 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(11, 1), FpRD(13, 0)))), 456 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 457 ), 458 numPregs = intPreg.numEntries max vfPreg.numEntries, 459 numDeqOutside = 0, 460 schdType = schdType, 461 rfDataWidth = rfDataWidth, 462 numUopIn = dpParams.LsDqDeqWidth, 463 ) 464 } 465 466 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 467 468 def iqWakeUpParams = { 469 Seq( 470 WakeUpConfig( 471 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 472 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 473 ), 474 WakeUpConfig( 475 Seq("FEX0", "FEX1", "FEX2", "FEX3", "LDU0", "LDU1", "LDU2") -> 476 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 477 ), 478 WakeUpConfig( 479 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 480 Seq("STD0", "STD1") 481 ), 482 WakeUpConfig( 483 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 484 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "VFEX4", "VFEX5") 485 ), 486 ).flatten 487 } 488 489 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 490 491 val backendParams: BackendParams = backend.BackendParams( 492 Map( 493 IntScheduler() -> intSchdParams, 494 FpScheduler() -> fpSchdParams, 495 VfScheduler() -> vfSchdParams, 496 MemScheduler() -> memSchdParams, 497 ), 498 Seq( 499 intPreg, 500 fpPreg, 501 vfPreg, 502 fakeIntPreg 503 ), 504 iqWakeUpParams, 505 ) 506} 507 508case object DebugOptionsKey extends Field[DebugOptions] 509 510case class DebugOptions 511( 512 FPGAPlatform: Boolean = false, 513 ResetGen: Boolean = false, 514 EnableDifftest: Boolean = false, 515 AlwaysBasicDiff: Boolean = true, 516 EnableDebug: Boolean = false, 517 EnablePerfDebug: Boolean = true, 518 UseDRAMSim: Boolean = false, 519 EnableConstantin: Boolean = false, 520 EnableChiselDB: Boolean = false, 521 AlwaysBasicDB: Boolean = true, 522 EnableTopDown: Boolean = false, 523 EnableRollingDB: Boolean = false 524) 525 526trait HasXSParameter { 527 528 implicit val p: Parameters 529 530 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 531 def NodeIDWidth = p(SoCParamsKey).NodeIDWidth // NodeID width among NoC 532 533 def coreParams = p(XSCoreParamsKey) 534 def env = p(DebugOptionsKey) 535 536 def XLEN = coreParams.XLEN 537 def VLEN = coreParams.VLEN 538 def ELEN = coreParams.ELEN 539 def HSXLEN = coreParams.HSXLEN 540 val minFLen = 32 541 val fLen = 64 542 def hartIdLen = p(MaxHartIdBits) 543 val xLen = XLEN 544 545 def HasMExtension = coreParams.HasMExtension 546 def HasCExtension = coreParams.HasCExtension 547 def HasHExtension = coreParams.HasHExtension 548 def HasDiv = coreParams.HasDiv 549 def HasIcache = coreParams.HasICache 550 def HasDcache = coreParams.HasDCache 551 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 552 def GPAddrBits = coreParams.GPAddrBits 553 def VAddrBits = { 554 if(HasHExtension){ 555 coreParams.GPAddrBits 556 }else{ 557 coreParams.VAddrBits 558 } 559 } // VAddrBits is Virtual Memory addr bits 560 561 def AsidLength = coreParams.AsidLength 562 def VmidLength = coreParams.VmidLength 563 def ReSelectLen = coreParams.ReSelectLen 564 def AddrBytes = AddrBits / 8 // unused 565 def DataBits = XLEN 566 def DataBytes = DataBits / 8 567 def VDataBytes = VLEN / 8 568 def HasFPU = coreParams.HasFPU 569 def HasVPU = coreParams.HasVPU 570 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 571 def FetchWidth = coreParams.FetchWidth 572 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 573 def EnableBPU = coreParams.EnableBPU 574 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 575 def EnableRAS = coreParams.EnableRAS 576 def EnableLB = coreParams.EnableLB 577 def EnableLoop = coreParams.EnableLoop 578 def EnableSC = coreParams.EnableSC 579 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 580 def HistoryLength = coreParams.HistoryLength 581 def EnableGHistDiff = coreParams.EnableGHistDiff 582 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 583 def EnableClockGate = coreParams.EnableClockGate 584 def UbtbGHRLength = coreParams.UbtbGHRLength 585 def UbtbSize = coreParams.UbtbSize 586 def EnableFauFTB = coreParams.EnableFauFTB 587 def FtbSize = coreParams.FtbSize 588 def FtbWays = coreParams.FtbWays 589 def RasSize = coreParams.RasSize 590 def RasSpecSize = coreParams.RasSpecSize 591 def RasCtrSize = coreParams.RasCtrSize 592 593 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 594 coreParams.branchPredictor(resp_in, p) 595 } 596 def numBr = coreParams.numBr 597 def TageTableInfos = coreParams.TageTableInfos 598 def TageBanks = coreParams.numBr 599 def SCNRows = coreParams.SCNRows 600 def SCCtrBits = coreParams.SCCtrBits 601 def SCHistLens = coreParams.SCHistLens 602 def SCNTables = coreParams.SCNTables 603 604 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 605 case ((n, cb), h) => (n, cb, h) 606 } 607 def ITTageTableInfos = coreParams.ITTageTableInfos 608 type FoldedHistoryInfo = Tuple2[Int, Int] 609 def foldedGHistInfos = 610 (TageTableInfos.map{ case (nRows, h, t) => 611 if (h > 0) 612 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 613 else 614 Set[FoldedHistoryInfo]() 615 }.reduce(_++_).toSet ++ 616 SCTableInfos.map{ case (nRows, _, h) => 617 if (h > 0) 618 Set((h, min(log2Ceil(nRows/TageBanks), h))) 619 else 620 Set[FoldedHistoryInfo]() 621 }.reduce(_++_).toSet ++ 622 ITTageTableInfos.map{ case (nRows, h, t) => 623 if (h > 0) 624 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 625 else 626 Set[FoldedHistoryInfo]() 627 }.reduce(_++_) ++ 628 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 629 ).toList 630 631 632 633 def CacheLineSize = coreParams.CacheLineSize 634 def CacheLineHalfWord = CacheLineSize / 16 635 def ExtHistoryLength = HistoryLength + 64 636 def ICacheECCForceError = coreParams.ICacheECCForceError 637 def IBufSize = coreParams.IBufSize 638 def IBufNBank = coreParams.IBufNBank 639 def backendParams: BackendParams = coreParams.backendParams 640 def DecodeWidth = coreParams.DecodeWidth 641 def RenameWidth = coreParams.RenameWidth 642 def CommitWidth = coreParams.CommitWidth 643 def RobCommitWidth = coreParams.RobCommitWidth 644 def RabCommitWidth = coreParams.RabCommitWidth 645 def MaxUopSize = coreParams.MaxUopSize 646 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 647 def RenameSnapshotNum = coreParams.RenameSnapshotNum 648 def FtqSize = coreParams.FtqSize 649 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 650 def IntLogicRegs = coreParams.IntLogicRegs 651 def FpLogicRegs = coreParams.FpLogicRegs 652 def VecLogicRegs = coreParams.VecLogicRegs 653 def VCONFIG_IDX = coreParams.VCONFIG_IDX 654 def IntPhyRegs = coreParams.intPreg.numEntries 655 def FpPhyRegs = coreParams.fpPreg.numEntries 656 def VfPhyRegs = coreParams.vfPreg.numEntries 657 def MaxPhyPregs = IntPhyRegs max VfPhyRegs 658 def PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 659 def RobSize = coreParams.RobSize 660 def RabSize = coreParams.RabSize 661 def VTypeBufferSize = coreParams.VTypeBufferSize 662 /** 663 * the minimum element length of vector elements 664 */ 665 def minVecElen: Int = coreParams.minVecElen 666 667 /** 668 * the maximum number of elements in vector register 669 */ 670 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 671 672 def IntRefCounterWidth = log2Ceil(RobSize) 673 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 674 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 675 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 676 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 677 def LoadQueueRARSize = coreParams.LoadQueueRARSize 678 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 679 def RollbackGroupSize = coreParams.RollbackGroupSize 680 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 681 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 682 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 683 def StoreQueueSize = coreParams.StoreQueueSize 684 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 685 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 686 def VlsQueueSize = coreParams.VlsQueueSize 687 def dpParams = coreParams.dpParams 688 689 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 690 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 691 692 def NumRedirect = backendParams.numRedirect 693 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 694 def FtqRedirectAheadNum = NumRedirect 695 def LoadPipelineWidth = coreParams.LoadPipelineWidth 696 def StorePipelineWidth = coreParams.StorePipelineWidth 697 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 698 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 699 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 700 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 701 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 702 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 703 def StoreBufferSize = coreParams.StoreBufferSize 704 def StoreBufferThreshold = coreParams.StoreBufferThreshold 705 def EnsbufferWidth = coreParams.EnsbufferWidth 706 def LoadDependencyWidth = coreParams.LoadDependencyWidth 707 def VlMergeBufferSize = coreParams.VlMergeBufferSize 708 def VsMergeBufferSize = coreParams.VsMergeBufferSize 709 def UopWritebackWidth = coreParams.UopWritebackWidth 710 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 711 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 712 def SplitBufferSize = coreParams.SplitBufferSize 713 def VSegmentBufferSize = coreParams.VSegmentBufferSize 714 def UncacheBufferSize = coreParams.UncacheBufferSize 715 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 716 def EnableFastForward = coreParams.EnableFastForward 717 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 718 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 719 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 720 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 721 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 722 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 723 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 724 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 725 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 726 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 727 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 728 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 729 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 730 def asidLen = coreParams.MMUAsidLen 731 def vmidLen = coreParams.MMUVmidLen 732 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 733 def refillBothTlb = coreParams.refillBothTlb 734 def iwpuParam = coreParams.iwpuParameters 735 def dwpuParam = coreParams.dwpuParameters 736 def itlbParams = coreParams.itlbParameters 737 def ldtlbParams = coreParams.ldtlbParameters 738 def sttlbParams = coreParams.sttlbParameters 739 def hytlbParams = coreParams.hytlbParameters 740 def pftlbParams = coreParams.pftlbParameters 741 def l2ToL1Params = coreParams.l2ToL1tlbParameters 742 def btlbParams = coreParams.btlbParameters 743 def l2tlbParams = coreParams.l2tlbParameters 744 def NumPerfCounters = coreParams.NumPerfCounters 745 746 def instBytes = if (HasCExtension) 2 else 4 747 def instOffsetBits = log2Ceil(instBytes) 748 749 def icacheParameters = coreParams.icacheParameters 750 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 751 752 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 753 // for constrained LR/SC loop 754 def LRSCCycles = 64 755 // for lr storm 756 def LRSCBackOff = 8 757 758 // cache hierarchy configurations 759 def l1BusDataWidth = 256 760 761 // load violation predict 762 def ResetTimeMax2Pow = 20 //1078576 763 def ResetTimeMin2Pow = 10 //1024 764 // wait table parameters 765 def WaitTableSize = 1024 766 def MemPredPCWidth = log2Up(WaitTableSize) 767 def LWTUse2BitCounter = true 768 // store set parameters 769 def SSITSize = WaitTableSize 770 def LFSTSize = 32 771 def SSIDWidth = log2Up(LFSTSize) 772 def LFSTWidth = 4 773 def StoreSetEnable = true // LWT will be disabled if SS is enabled 774 def LFSTEnable = true 775 776 def PCntIncrStep: Int = 6 777 def numPCntHc: Int = 25 778 def numPCntPtw: Int = 19 779 780 def numCSRPCntFrontend = 8 781 def numCSRPCntCtrl = 8 782 def numCSRPCntLsu = 8 783 def numCSRPCntHc = 5 784 def printEventCoding = true 785 786 // Parameters for Sdtrig extension 787 protected def TriggerNum = 4 788 protected def TriggerChainMaxLength = 2 789} 790