1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams, FakeIntPregParams, FpPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import freechips.rocketchip.tile.MaxHartIdBits 42import system.SoCParamsKey 43import huancun._ 44import huancun.debug._ 45import xiangshan.cache.wpu.WPUParameters 46import coupledL2._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.min 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBits: Int = 39, 72 GPAddrBits: Int = 41, 73 HasFPU: Boolean = true, 74 HasVPU: Boolean = true, 75 HasCustomCSRCacheOp: Boolean = true, 76 FetchWidth: Int = 8, 77 AsidLength: Int = 16, 78 VmidLength: Int = 14, 79 EnableBPU: Boolean = true, 80 EnableBPD: Boolean = true, 81 EnableRAS: Boolean = true, 82 EnableLB: Boolean = false, 83 EnableLoop: Boolean = true, 84 EnableSC: Boolean = true, 85 EnbaleTlbDebug: Boolean = false, 86 EnableClockGate: Boolean = true, 87 EnableJal: Boolean = false, 88 EnableFauFTB: Boolean = true, 89 UbtbGHRLength: Int = 4, 90 // HistoryLength: Int = 512, 91 EnableGHistDiff: Boolean = true, 92 EnableCommitGHistDiff: Boolean = true, 93 UbtbSize: Int = 256, 94 FtbSize: Int = 2048, 95 RasSize: Int = 16, 96 RasSpecSize: Int = 32, 97 RasCtrSize: Int = 3, 98 CacheLineSize: Int = 512, 99 FtbWays: Int = 4, 100 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 101 // Sets Hist Tag 102 Seq(( 4096, 8, 8), 103 ( 4096, 13, 8), 104 ( 4096, 32, 8), 105 ( 4096, 119, 8)), 106 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 107 // Sets Hist Tag 108 Seq(( 256, 4, 9), 109 ( 256, 8, 9), 110 ( 512, 13, 9), 111 ( 512, 16, 9), 112 ( 512, 32, 9)), 113 SCNRows: Int = 512, 114 SCNTables: Int = 4, 115 SCCtrBits: Int = 6, 116 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 117 numBr: Int = 2, 118 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 119 (resp_in: BranchPredictionResp, p: Parameters) => { 120 val ftb = Module(new FTB()(p)) 121 val uftb = Module(new FauFTB()(p)) 122 val tage = Module(new Tage_SC()(p)) 123 val ras = Module(new RAS()(p)) 124 val ittage = Module(new ITTage()(p)) 125 val preds = Seq(uftb, tage, ftb, ittage, ras) 126 preds.map(_.io := DontCare) 127 128 uftb.io.in.bits.resp_in(0) := resp_in 129 tage.io.in.bits.resp_in(0) := uftb.io.out 130 ftb.io.in.bits.resp_in(0) := tage.io.out 131 ittage.io.in.bits.resp_in(0) := ftb.io.out 132 ras.io.in.bits.resp_in(0) := ittage.io.out 133 134 (preds, ras.io.out) 135 }, 136 ICacheECCForceError: Boolean = false, 137 IBufSize: Int = 48, 138 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 139 DecodeWidth: Int = 6, 140 RenameWidth: Int = 6, 141 CommitWidth: Int = 8, 142 RobCommitWidth: Int = 8, 143 RabCommitWidth: Int = 6, 144 MaxUopSize: Int = 65, 145 EnableRenameSnapshot: Boolean = true, 146 RenameSnapshotNum: Int = 4, 147 FtqSize: Int = 64, 148 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 149 IntLogicRegs: Int = 32, 150 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 151 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 152 VCONFIG_IDX: Int = 32, 153 NRPhyRegs: Int = 192, 154 VirtualLoadQueueSize: Int = 72, 155 LoadQueueRARSize: Int = 72, 156 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 157 RollbackGroupSize: Int = 8, 158 LoadQueueReplaySize: Int = 72, 159 LoadUncacheBufferSize: Int = 20, 160 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 161 StoreQueueSize: Int = 64, 162 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 163 StoreQueueForwardWithMask: Boolean = true, 164 VlsQueueSize: Int = 8, 165 RobSize: Int = 160, 166 RabSize: Int = 256, 167 VTypeBufferSize: Int = 64, // used to reorder vtype 168 IssueQueueSize: Int = 24, 169 IssueQueueCompEntrySize: Int = 16, 170 dpParams: DispatchParameters = DispatchParameters( 171 IntDqSize = 16, 172 FpDqSize = 16, 173 LsDqSize = 18, 174 IntDqDeqWidth = 8, 175 FpDqDeqWidth = 6, 176 VecDqDeqWidth = 6, 177 LsDqDeqWidth = 6, 178 ), 179 intPreg: PregParams = IntPregParams( 180 numEntries = 224, 181 numRead = None, 182 numWrite = None, 183 ), 184 fpPreg: PregParams = FpPregParams( 185 numEntries = 192, 186 numRead = None, 187 numWrite = None, 188 ), 189 vfPreg: VfPregParams = VfPregParams( 190 numEntries = 128, 191 numRead = None, 192 numWrite = None, 193 ), 194 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 195 LoadPipelineWidth: Int = 3, 196 StorePipelineWidth: Int = 2, 197 VecLoadPipelineWidth: Int = 2, 198 VecStorePipelineWidth: Int = 2, 199 VecMemSrcInWidth: Int = 2, 200 VecMemInstWbWidth: Int = 1, 201 VecMemDispatchWidth: Int = 1, 202 VecMemDispatchMaxNumber: Int = 16, 203 StoreBufferSize: Int = 16, 204 StoreBufferThreshold: Int = 7, 205 EnsbufferWidth: Int = 2, 206 LoadDependencyWidth: Int = 2, 207 // ============ VLSU ============ 208 VlMergeBufferSize: Int = 16, 209 VsMergeBufferSize: Int = 16, 210 UopWritebackWidth: Int = 2, 211 VLUopWritebackWidth: Int = 2, 212 VSUopWritebackWidth: Int = 1, 213 SplitBufferSize: Int = 8, 214 VSegmentBufferSize: Int = 8, 215 // ============================== 216 UncacheBufferSize: Int = 4, 217 EnableLoadToLoadForward: Boolean = false, 218 EnableFastForward: Boolean = true, 219 EnableLdVioCheckAfterReset: Boolean = true, 220 EnableSoftPrefetchAfterReset: Boolean = true, 221 EnableCacheErrorAfterReset: Boolean = true, 222 EnableAccurateLoadError: Boolean = true, 223 EnableUncacheWriteOutstanding: Boolean = false, 224 EnableStorePrefetchAtIssue: Boolean = false, 225 EnableStorePrefetchAtCommit: Boolean = false, 226 EnableAtCommitMissTrigger: Boolean = true, 227 EnableStorePrefetchSMS: Boolean = false, 228 EnableStorePrefetchSPB: Boolean = false, 229 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 230 MMUVmidLen: Int = 14, 231 ReSelectLen: Int = 7, // load replay queue replay select counter len 232 iwpuParameters: WPUParameters = WPUParameters( 233 enWPU = false, 234 algoName = "mmru", 235 isICache = true, 236 ), 237 dwpuParameters: WPUParameters = WPUParameters( 238 enWPU = false, 239 algoName = "mmru", 240 enCfPred = false, 241 isICache = false, 242 ), 243 itlbParameters: TLBParameters = TLBParameters( 244 name = "itlb", 245 fetchi = true, 246 useDmode = false, 247 NWays = 48, 248 ), 249 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 250 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 251 ldtlbParameters: TLBParameters = TLBParameters( 252 name = "ldtlb", 253 NWays = 48, 254 outReplace = false, 255 partialStaticPMP = true, 256 outsideRecvFlush = true, 257 saveLevel = true, 258 lgMaxSize = 4 259 ), 260 sttlbParameters: TLBParameters = TLBParameters( 261 name = "sttlb", 262 NWays = 48, 263 outReplace = false, 264 partialStaticPMP = true, 265 outsideRecvFlush = true, 266 saveLevel = true, 267 lgMaxSize = 4 268 ), 269 hytlbParameters: TLBParameters = TLBParameters( 270 name = "hytlb", 271 NWays = 48, 272 outReplace = false, 273 partialStaticPMP = true, 274 outsideRecvFlush = true, 275 saveLevel = true, 276 lgMaxSize = 4 277 ), 278 pftlbParameters: TLBParameters = TLBParameters( 279 name = "pftlb", 280 NWays = 48, 281 outReplace = false, 282 partialStaticPMP = true, 283 outsideRecvFlush = true, 284 saveLevel = true, 285 lgMaxSize = 4 286 ), 287 l2ToL1tlbParameters: TLBParameters = TLBParameters( 288 name = "l2tlb", 289 NWays = 48, 290 outReplace = false, 291 partialStaticPMP = true, 292 outsideRecvFlush = true, 293 saveLevel = true 294 ), 295 refillBothTlb: Boolean = false, 296 btlbParameters: TLBParameters = TLBParameters( 297 name = "btlb", 298 NWays = 48, 299 ), 300 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 301 NumPerfCounters: Int = 16, 302 icacheParameters: ICacheParameters = ICacheParameters( 303 tagECC = Some("parity"), 304 dataECC = Some("parity"), 305 replacer = Some("setplru"), 306 nMissEntries = 2, 307 nProbeEntries = 2, 308 nPrefetchEntries = 12, 309 nPrefBufferEntries = 32, 310 ), 311 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 312 tagECC = Some("secded"), 313 dataECC = Some("secded"), 314 replacer = Some("setplru"), 315 nMissEntries = 16, 316 nProbeEntries = 8, 317 nReleaseEntries = 18, 318 nMaxPrefetchEntry = 6, 319 )), 320 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 321 name = "l2", 322 ways = 8, 323 sets = 1024, // default 512KB L2 324 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 325 )), 326 L2NBanks: Int = 1, 327 usePTWRepeater: Boolean = false, 328 softTLB: Boolean = false, // dpi-c l1tlb debug only 329 softPTW: Boolean = false, // dpi-c l2tlb debug only 330 softPTWDelay: Int = 1 331){ 332 def vlWidth = log2Up(VLEN) + 1 333 334 /** 335 * the minimum element length of vector elements 336 */ 337 val minVecElen: Int = 8 338 339 /** 340 * the maximum number of elements in vector register 341 */ 342 val maxElemPerVreg: Int = VLEN / minVecElen 343 344 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 345 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 346 347 val intSchdParams = { 348 implicit val schdType: SchedulerType = IntScheduler() 349 SchdBlockParams(Seq( 350 IssueBlockParams(Seq( 351 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 352 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(7, 1))), true, 2), 353 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 354 IssueBlockParams(Seq( 355 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 356 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 2, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(5, 1))), true, 2), 357 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 358 IssueBlockParams(Seq( 359 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 360 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 0, 1), FpWB(port = 4, 0), VfWB(5, 1)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(3, 1)))), 361 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 362 IssueBlockParams(Seq( 363 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 364 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(1, 1)))), 365 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 366 ), 367 numPregs = intPreg.numEntries, 368 numDeqOutside = 0, 369 schdType = schdType, 370 rfDataWidth = intPreg.dataCfg.dataWidth, 371 numUopIn = dpParams.IntDqDeqWidth, 372 ) 373 } 374 375 val fpSchdParams = { 376 implicit val schdType: SchedulerType = FpScheduler() 377 SchdBlockParams(Seq( 378 IssueBlockParams(Seq( 379 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 1), VfWB(port = 1, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)))), 380 ExeUnitParams("FEX1", Seq(FmacCfg), Seq(FpWB(port = 1, 0)), Seq(Seq(FpRD(2, 0)), Seq(FpRD(3, 0)), Seq(FpRD(4, 0)))), 381 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 382 IssueBlockParams(Seq( 383 ExeUnitParams("FEX2", Seq(FaluCfg), Seq(FpWB(port = 2, 0), IntWB(port = 0, 2)), Seq(Seq(FpRD(5, 0)), Seq(FpRD(6, 0)))), 384 ExeUnitParams("FEX3", Seq(FmacCfg), Seq(FpWB(port = 3, 0)), Seq(Seq(FpRD(7, 0)), Seq(FpRD(8, 0)), Seq(FpRD(9, 0)))), 385 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 386 IssueBlockParams(Seq( 387 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 388 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 5, 1)), Seq(Seq(FpRD(12, 0)), Seq(FpRD(13, 0)))), 389 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 390 ), 391 numPregs = fpPreg.numEntries, 392 numDeqOutside = 0, 393 schdType = schdType, 394 rfDataWidth = fpPreg.dataCfg.dataWidth, 395 numUopIn = dpParams.VecDqDeqWidth, 396 ) 397 } 398 399 val vfSchdParams = { 400 implicit val schdType: SchedulerType = VfScheduler() 401 SchdBlockParams(Seq( 402 IssueBlockParams(Seq( 403 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 404 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 5, 0), IntWB(port = 2, 2)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 405 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 406 IssueBlockParams(Seq( 407 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 6, 0)), Seq(Seq(VfRD(7, 1)), Seq(VfRD(8, 1)), Seq(VfRD(9, 1)), Seq(VfRD(5, 1)), Seq(VfRD(6, 1)))), 408 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 7, 0), IntWB(port = 3, 2)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)))), 409 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 410 IssueBlockParams(Seq( 411 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 2, 0)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(0, 2)), Seq(VfRD(1, 2)), Seq(VfRD(2, 2)))), 412 ExeUnitParams("VFEX5", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 0)), Seq(Seq(VfRD(8, 2)), Seq(VfRD(9, 2)), Seq(VfRD(5, 2)), Seq(VfRD(6, 2)), Seq(VfRD(7, 2)))), 413 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 414 ), 415 numPregs = vfPreg.numEntries, 416 numDeqOutside = 0, 417 schdType = schdType, 418 rfDataWidth = vfPreg.dataCfg.dataWidth, 419 numUopIn = dpParams.VecDqDeqWidth, 420 ) 421 } 422 423 val memSchdParams = { 424 implicit val schdType: SchedulerType = MemScheduler() 425 val rfDataWidth = 64 426 427 SchdBlockParams(Seq( 428 IssueBlockParams(Seq( 429 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(8, 1)))), 430 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 431 IssueBlockParams(Seq( 432 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(9, 1)))), 433 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 434 IssueBlockParams(Seq( 435 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 436 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 437 IssueBlockParams(Seq( 438 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 439 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 440 IssueBlockParams(Seq( 441 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 442 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 443 IssueBlockParams(Seq( 444 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(0, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(VfRD(12, 0)), Seq(VfRD(13, 0)), Seq(VfRD(14, 0)))), 445 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 446 IssueBlockParams(Seq( 447 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(8, 0)), Seq(Seq(VfRD(15, 0)), Seq(VfRD(16, 0)), Seq(VfRD(17, 0)), Seq(VfRD(18, 0)), Seq(VfRD(19, 0)))), 448 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 449 IssueBlockParams(Seq( 450 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(10, 1), FpRD(14, 0)))), 451 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 452 IssueBlockParams(Seq( 453 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(11, 1), FpRD(15, 0)))), 454 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 455 ), 456 numPregs = intPreg.numEntries max vfPreg.numEntries, 457 numDeqOutside = 0, 458 schdType = schdType, 459 rfDataWidth = rfDataWidth, 460 numUopIn = dpParams.LsDqDeqWidth, 461 ) 462 } 463 464 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 465 466 def iqWakeUpParams = { 467 Seq( 468 WakeUpConfig( 469 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 470 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 471 ), 472 WakeUpConfig( 473 Seq("FEX0", "FEX1", "FEX2", "FEX3", "LDU0", "LDU1", "LDU2") -> 474 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 475 ), 476 WakeUpConfig( 477 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 478 Seq("STD0", "STD1") 479 ), 480 WakeUpConfig( 481 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 482 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "VFEX4", "VFEX5") 483 ), 484 ).flatten 485 } 486 487 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 488 489 val backendParams: BackendParams = backend.BackendParams( 490 Map( 491 IntScheduler() -> intSchdParams, 492 FpScheduler() -> fpSchdParams, 493 VfScheduler() -> vfSchdParams, 494 MemScheduler() -> memSchdParams, 495 ), 496 Seq( 497 intPreg, 498 fpPreg, 499 vfPreg, 500 fakeIntPreg 501 ), 502 iqWakeUpParams, 503 ) 504} 505 506case object DebugOptionsKey extends Field[DebugOptions] 507 508case class DebugOptions 509( 510 FPGAPlatform: Boolean = false, 511 ResetGen: Boolean = false, 512 EnableDifftest: Boolean = false, 513 AlwaysBasicDiff: Boolean = true, 514 EnableDebug: Boolean = false, 515 EnablePerfDebug: Boolean = true, 516 UseDRAMSim: Boolean = false, 517 EnableConstantin: Boolean = false, 518 EnableChiselDB: Boolean = false, 519 AlwaysBasicDB: Boolean = true, 520 EnableTopDown: Boolean = false, 521 EnableRollingDB: Boolean = false 522) 523 524trait HasXSParameter { 525 526 implicit val p: Parameters 527 528 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 529 def NodeIDWidth = p(SoCParamsKey).NodeIDWidth // NodeID width among NoC 530 531 def coreParams = p(XSCoreParamsKey) 532 def env = p(DebugOptionsKey) 533 534 def XLEN = coreParams.XLEN 535 def VLEN = coreParams.VLEN 536 def ELEN = coreParams.ELEN 537 def HSXLEN = coreParams.HSXLEN 538 val minFLen = 32 539 val fLen = 64 540 def hartIdLen = p(MaxHartIdBits) 541 val xLen = XLEN 542 543 def HasMExtension = coreParams.HasMExtension 544 def HasCExtension = coreParams.HasCExtension 545 def HasHExtension = coreParams.HasHExtension 546 def HasDiv = coreParams.HasDiv 547 def HasIcache = coreParams.HasICache 548 def HasDcache = coreParams.HasDCache 549 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 550 def GPAddrBits = coreParams.GPAddrBits 551 def VAddrBits = { 552 if(HasHExtension){ 553 coreParams.GPAddrBits 554 }else{ 555 coreParams.VAddrBits 556 } 557 } // VAddrBits is Virtual Memory addr bits 558 559 def AsidLength = coreParams.AsidLength 560 def VmidLength = coreParams.VmidLength 561 def ReSelectLen = coreParams.ReSelectLen 562 def AddrBytes = AddrBits / 8 // unused 563 def DataBits = XLEN 564 def DataBytes = DataBits / 8 565 def VDataBytes = VLEN / 8 566 def HasFPU = coreParams.HasFPU 567 def HasVPU = coreParams.HasVPU 568 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 569 def FetchWidth = coreParams.FetchWidth 570 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 571 def EnableBPU = coreParams.EnableBPU 572 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 573 def EnableRAS = coreParams.EnableRAS 574 def EnableLB = coreParams.EnableLB 575 def EnableLoop = coreParams.EnableLoop 576 def EnableSC = coreParams.EnableSC 577 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 578 def HistoryLength = coreParams.HistoryLength 579 def EnableGHistDiff = coreParams.EnableGHistDiff 580 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 581 def EnableClockGate = coreParams.EnableClockGate 582 def UbtbGHRLength = coreParams.UbtbGHRLength 583 def UbtbSize = coreParams.UbtbSize 584 def EnableFauFTB = coreParams.EnableFauFTB 585 def FtbSize = coreParams.FtbSize 586 def FtbWays = coreParams.FtbWays 587 def RasSize = coreParams.RasSize 588 def RasSpecSize = coreParams.RasSpecSize 589 def RasCtrSize = coreParams.RasCtrSize 590 591 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 592 coreParams.branchPredictor(resp_in, p) 593 } 594 def numBr = coreParams.numBr 595 def TageTableInfos = coreParams.TageTableInfos 596 def TageBanks = coreParams.numBr 597 def SCNRows = coreParams.SCNRows 598 def SCCtrBits = coreParams.SCCtrBits 599 def SCHistLens = coreParams.SCHistLens 600 def SCNTables = coreParams.SCNTables 601 602 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 603 case ((n, cb), h) => (n, cb, h) 604 } 605 def ITTageTableInfos = coreParams.ITTageTableInfos 606 type FoldedHistoryInfo = Tuple2[Int, Int] 607 def foldedGHistInfos = 608 (TageTableInfos.map{ case (nRows, h, t) => 609 if (h > 0) 610 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 611 else 612 Set[FoldedHistoryInfo]() 613 }.reduce(_++_).toSet ++ 614 SCTableInfos.map{ case (nRows, _, h) => 615 if (h > 0) 616 Set((h, min(log2Ceil(nRows/TageBanks), h))) 617 else 618 Set[FoldedHistoryInfo]() 619 }.reduce(_++_).toSet ++ 620 ITTageTableInfos.map{ case (nRows, h, t) => 621 if (h > 0) 622 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 623 else 624 Set[FoldedHistoryInfo]() 625 }.reduce(_++_) ++ 626 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 627 ).toList 628 629 630 631 def CacheLineSize = coreParams.CacheLineSize 632 def CacheLineHalfWord = CacheLineSize / 16 633 def ExtHistoryLength = HistoryLength + 64 634 def ICacheECCForceError = coreParams.ICacheECCForceError 635 def IBufSize = coreParams.IBufSize 636 def IBufNBank = coreParams.IBufNBank 637 def backendParams: BackendParams = coreParams.backendParams 638 def DecodeWidth = coreParams.DecodeWidth 639 def RenameWidth = coreParams.RenameWidth 640 def CommitWidth = coreParams.CommitWidth 641 def RobCommitWidth = coreParams.RobCommitWidth 642 def RabCommitWidth = coreParams.RabCommitWidth 643 def MaxUopSize = coreParams.MaxUopSize 644 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 645 def RenameSnapshotNum = coreParams.RenameSnapshotNum 646 def FtqSize = coreParams.FtqSize 647 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 648 def IntLogicRegs = coreParams.IntLogicRegs 649 def FpLogicRegs = coreParams.FpLogicRegs 650 def VecLogicRegs = coreParams.VecLogicRegs 651 def VCONFIG_IDX = coreParams.VCONFIG_IDX 652 def IntPhyRegs = coreParams.intPreg.numEntries 653 def FpPhyRegs = coreParams.fpPreg.numEntries 654 def VfPhyRegs = coreParams.vfPreg.numEntries 655 def MaxPhyPregs = IntPhyRegs max VfPhyRegs 656 def PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 657 def RobSize = coreParams.RobSize 658 def RabSize = coreParams.RabSize 659 def VTypeBufferSize = coreParams.VTypeBufferSize 660 /** 661 * the minimum element length of vector elements 662 */ 663 def minVecElen: Int = coreParams.minVecElen 664 665 /** 666 * the maximum number of elements in vector register 667 */ 668 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 669 670 def IntRefCounterWidth = log2Ceil(RobSize) 671 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 672 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 673 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 674 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 675 def LoadQueueRARSize = coreParams.LoadQueueRARSize 676 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 677 def RollbackGroupSize = coreParams.RollbackGroupSize 678 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 679 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 680 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 681 def StoreQueueSize = coreParams.StoreQueueSize 682 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 683 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 684 def VlsQueueSize = coreParams.VlsQueueSize 685 def dpParams = coreParams.dpParams 686 687 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 688 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 689 690 def NumRedirect = backendParams.numRedirect 691 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 692 def FtqRedirectAheadNum = NumRedirect 693 def LoadPipelineWidth = coreParams.LoadPipelineWidth 694 def StorePipelineWidth = coreParams.StorePipelineWidth 695 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 696 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 697 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 698 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 699 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 700 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 701 def StoreBufferSize = coreParams.StoreBufferSize 702 def StoreBufferThreshold = coreParams.StoreBufferThreshold 703 def EnsbufferWidth = coreParams.EnsbufferWidth 704 def LoadDependencyWidth = coreParams.LoadDependencyWidth 705 def VlMergeBufferSize = coreParams.VlMergeBufferSize 706 def VsMergeBufferSize = coreParams.VsMergeBufferSize 707 def UopWritebackWidth = coreParams.UopWritebackWidth 708 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 709 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 710 def SplitBufferSize = coreParams.SplitBufferSize 711 def VSegmentBufferSize = coreParams.VSegmentBufferSize 712 def UncacheBufferSize = coreParams.UncacheBufferSize 713 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 714 def EnableFastForward = coreParams.EnableFastForward 715 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 716 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 717 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 718 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 719 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 720 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 721 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 722 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 723 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 724 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 725 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 726 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 727 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 728 def asidLen = coreParams.MMUAsidLen 729 def vmidLen = coreParams.MMUVmidLen 730 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 731 def refillBothTlb = coreParams.refillBothTlb 732 def iwpuParam = coreParams.iwpuParameters 733 def dwpuParam = coreParams.dwpuParameters 734 def itlbParams = coreParams.itlbParameters 735 def ldtlbParams = coreParams.ldtlbParameters 736 def sttlbParams = coreParams.sttlbParameters 737 def hytlbParams = coreParams.hytlbParameters 738 def pftlbParams = coreParams.pftlbParameters 739 def l2ToL1Params = coreParams.l2ToL1tlbParameters 740 def btlbParams = coreParams.btlbParameters 741 def l2tlbParams = coreParams.l2tlbParameters 742 def NumPerfCounters = coreParams.NumPerfCounters 743 744 def instBytes = if (HasCExtension) 2 else 4 745 def instOffsetBits = log2Ceil(instBytes) 746 747 def icacheParameters = coreParams.icacheParameters 748 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 749 750 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 751 // for constrained LR/SC loop 752 def LRSCCycles = 64 753 // for lr storm 754 def LRSCBackOff = 8 755 756 // cache hierarchy configurations 757 def l1BusDataWidth = 256 758 759 // load violation predict 760 def ResetTimeMax2Pow = 20 //1078576 761 def ResetTimeMin2Pow = 10 //1024 762 // wait table parameters 763 def WaitTableSize = 1024 764 def MemPredPCWidth = log2Up(WaitTableSize) 765 def LWTUse2BitCounter = true 766 // store set parameters 767 def SSITSize = WaitTableSize 768 def LFSTSize = 32 769 def SSIDWidth = log2Up(LFSTSize) 770 def LFSTWidth = 4 771 def StoreSetEnable = true // LWT will be disabled if SS is enabled 772 def LFSTEnable = true 773 774 def PCntIncrStep: Int = 6 775 def numPCntHc: Int = 25 776 def numPCntPtw: Int = 19 777 778 def numCSRPCntFrontend = 8 779 def numCSRPCntCtrl = 8 780 def numCSRPCntLsu = 8 781 def numCSRPCntHc = 5 782 def printEventCoding = true 783 784 // Parameters for Sdtrig extension 785 protected def TriggerNum = 4 786 protected def TriggerChainMaxLength = 2 787} 788