1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams, FakeIntPregParams, FpPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import freechips.rocketchip.tile.MaxHartIdBits 42import system.SoCParamsKey 43import huancun._ 44import huancun.debug._ 45import xiangshan.cache.wpu.WPUParameters 46import coupledL2._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.min 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBits: Int = 39, 72 GPAddrBits: Int = 41, 73 HasFPU: Boolean = true, 74 HasVPU: Boolean = true, 75 HasCustomCSRCacheOp: Boolean = true, 76 FetchWidth: Int = 8, 77 AsidLength: Int = 16, 78 VmidLength: Int = 14, 79 EnableBPU: Boolean = true, 80 EnableBPD: Boolean = true, 81 EnableRAS: Boolean = true, 82 EnableLB: Boolean = false, 83 EnableLoop: Boolean = true, 84 EnableSC: Boolean = true, 85 EnbaleTlbDebug: Boolean = false, 86 EnableClockGate: Boolean = true, 87 EnableJal: Boolean = false, 88 EnableFauFTB: Boolean = true, 89 UbtbGHRLength: Int = 4, 90 // HistoryLength: Int = 512, 91 EnableGHistDiff: Boolean = true, 92 EnableCommitGHistDiff: Boolean = true, 93 UbtbSize: Int = 256, 94 FtbSize: Int = 2048, 95 RasSize: Int = 16, 96 RasSpecSize: Int = 32, 97 RasCtrSize: Int = 3, 98 CacheLineSize: Int = 512, 99 FtbWays: Int = 4, 100 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 101 // Sets Hist Tag 102 Seq(( 4096, 8, 8), 103 ( 4096, 13, 8), 104 ( 4096, 32, 8), 105 ( 4096, 119, 8)), 106 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 107 // Sets Hist Tag 108 Seq(( 256, 4, 9), 109 ( 256, 8, 9), 110 ( 512, 13, 9), 111 ( 512, 16, 9), 112 ( 512, 32, 9)), 113 SCNRows: Int = 512, 114 SCNTables: Int = 4, 115 SCCtrBits: Int = 6, 116 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 117 numBr: Int = 2, 118 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 119 (resp_in: BranchPredictionResp, p: Parameters) => { 120 val ftb = Module(new FTB()(p)) 121 val uftb = Module(new FauFTB()(p)) 122 val tage = Module(new Tage_SC()(p)) 123 val ras = Module(new RAS()(p)) 124 val ittage = Module(new ITTage()(p)) 125 val preds = Seq(uftb, tage, ftb, ittage, ras) 126 preds.map(_.io := DontCare) 127 128 uftb.io.in.bits.resp_in(0) := resp_in 129 tage.io.in.bits.resp_in(0) := uftb.io.out 130 ftb.io.in.bits.resp_in(0) := tage.io.out 131 ittage.io.in.bits.resp_in(0) := ftb.io.out 132 ras.io.in.bits.resp_in(0) := ittage.io.out 133 134 (preds, ras.io.out) 135 }, 136 ICacheECCForceError: Boolean = false, 137 IBufSize: Int = 48, 138 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 139 DecodeWidth: Int = 6, 140 RenameWidth: Int = 6, 141 CommitWidth: Int = 8, 142 RobCommitWidth: Int = 8, 143 RabCommitWidth: Int = 6, 144 MaxUopSize: Int = 65, 145 EnableRenameSnapshot: Boolean = true, 146 RenameSnapshotNum: Int = 4, 147 FtqSize: Int = 64, 148 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 149 IntLogicRegs: Int = 32, 150 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 151 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 152 VCONFIG_IDX: Int = 32, 153 NRPhyRegs: Int = 192, 154 VirtualLoadQueueSize: Int = 72, 155 LoadQueueRARSize: Int = 72, 156 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 157 RollbackGroupSize: Int = 8, 158 LoadQueueReplaySize: Int = 72, 159 LoadUncacheBufferSize: Int = 20, 160 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 161 StoreQueueSize: Int = 64, 162 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 163 StoreQueueForwardWithMask: Boolean = true, 164 VlsQueueSize: Int = 8, 165 RobSize: Int = 160, 166 RabSize: Int = 256, 167 VTypeBufferSize: Int = 64, // used to reorder vtype 168 IssueQueueSize: Int = 24, 169 IssueQueueCompEntrySize: Int = 16, 170 dpParams: DispatchParameters = DispatchParameters( 171 IntDqSize = 16, 172 FpDqSize = 16, 173 LsDqSize = 18, 174 IntDqDeqWidth = 8, 175 FpDqDeqWidth = 6, 176 VecDqDeqWidth = 6, 177 LsDqDeqWidth = 6, 178 ), 179 intPreg: PregParams = IntPregParams( 180 numEntries = 224, 181 numRead = None, 182 numWrite = None, 183 ), 184 fpPreg: PregParams = FpPregParams( 185 numEntries = 192, 186 numRead = None, 187 numWrite = None, 188 ), 189 vfPreg: VfPregParams = VfPregParams( 190 numEntries = 128, 191 numRead = None, 192 numWrite = None, 193 ), 194 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 195 LoadPipelineWidth: Int = 3, 196 StorePipelineWidth: Int = 2, 197 VecLoadPipelineWidth: Int = 2, 198 VecStorePipelineWidth: Int = 2, 199 VecMemSrcInWidth: Int = 2, 200 VecMemInstWbWidth: Int = 1, 201 VecMemDispatchWidth: Int = 1, 202 StoreBufferSize: Int = 16, 203 StoreBufferThreshold: Int = 7, 204 EnsbufferWidth: Int = 2, 205 LoadDependencyWidth: Int = 2, 206 // ============ VLSU ============ 207 UsQueueSize: Int = 8, 208 VlFlowSize: Int = 32, 209 VlUopSize: Int = 32, 210 VsFlowL1Size: Int = 128, 211 VsFlowL2Size: Int = 32, 212 VsUopSize: Int = 32, 213 // ============================== 214 UncacheBufferSize: Int = 4, 215 EnableLoadToLoadForward: Boolean = false, 216 EnableFastForward: Boolean = true, 217 EnableLdVioCheckAfterReset: Boolean = true, 218 EnableSoftPrefetchAfterReset: Boolean = true, 219 EnableCacheErrorAfterReset: Boolean = true, 220 EnableAccurateLoadError: Boolean = true, 221 EnableUncacheWriteOutstanding: Boolean = false, 222 EnableStorePrefetchAtIssue: Boolean = false, 223 EnableStorePrefetchAtCommit: Boolean = false, 224 EnableAtCommitMissTrigger: Boolean = true, 225 EnableStorePrefetchSMS: Boolean = false, 226 EnableStorePrefetchSPB: Boolean = false, 227 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 228 MMUVmidLen: Int = 14, 229 ReSelectLen: Int = 7, // load replay queue replay select counter len 230 iwpuParameters: WPUParameters = WPUParameters( 231 enWPU = false, 232 algoName = "mmru", 233 isICache = true, 234 ), 235 dwpuParameters: WPUParameters = WPUParameters( 236 enWPU = false, 237 algoName = "mmru", 238 enCfPred = false, 239 isICache = false, 240 ), 241 itlbParameters: TLBParameters = TLBParameters( 242 name = "itlb", 243 fetchi = true, 244 useDmode = false, 245 NWays = 48, 246 ), 247 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 248 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 249 ldtlbParameters: TLBParameters = TLBParameters( 250 name = "ldtlb", 251 NWays = 48, 252 outReplace = false, 253 partialStaticPMP = true, 254 outsideRecvFlush = true, 255 saveLevel = true 256 ), 257 sttlbParameters: TLBParameters = TLBParameters( 258 name = "sttlb", 259 NWays = 48, 260 outReplace = false, 261 partialStaticPMP = true, 262 outsideRecvFlush = true, 263 saveLevel = true 264 ), 265 hytlbParameters: TLBParameters = TLBParameters( 266 name = "hytlb", 267 NWays = 48, 268 outReplace = false, 269 partialStaticPMP = true, 270 outsideRecvFlush = true, 271 saveLevel = true 272 ), 273 pftlbParameters: TLBParameters = TLBParameters( 274 name = "pftlb", 275 NWays = 48, 276 outReplace = false, 277 partialStaticPMP = true, 278 outsideRecvFlush = true, 279 saveLevel = true 280 ), 281 l2ToL1tlbParameters: TLBParameters = TLBParameters( 282 name = "l2tlb", 283 NWays = 48, 284 outReplace = false, 285 partialStaticPMP = true, 286 outsideRecvFlush = true, 287 saveLevel = true 288 ), 289 refillBothTlb: Boolean = false, 290 btlbParameters: TLBParameters = TLBParameters( 291 name = "btlb", 292 NWays = 48, 293 ), 294 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 295 NumPerfCounters: Int = 16, 296 icacheParameters: ICacheParameters = ICacheParameters( 297 tagECC = Some("parity"), 298 dataECC = Some("parity"), 299 replacer = Some("setplru"), 300 nMissEntries = 2, 301 nProbeEntries = 2, 302 nPrefetchEntries = 12, 303 nPrefBufferEntries = 32, 304 ), 305 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 306 tagECC = Some("secded"), 307 dataECC = Some("secded"), 308 replacer = Some("setplru"), 309 nMissEntries = 16, 310 nProbeEntries = 8, 311 nReleaseEntries = 18, 312 nMaxPrefetchEntry = 6, 313 )), 314 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 315 name = "l2", 316 ways = 8, 317 sets = 1024, // default 512KB L2 318 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 319 )), 320 L2NBanks: Int = 1, 321 usePTWRepeater: Boolean = false, 322 softTLB: Boolean = false, // dpi-c l1tlb debug only 323 softPTW: Boolean = false, // dpi-c l2tlb debug only 324 softPTWDelay: Int = 1 325){ 326 def vlWidth = log2Up(VLEN) + 1 327 328 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 329 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 330 331 val intSchdParams = { 332 implicit val schdType: SchedulerType = IntScheduler() 333 SchdBlockParams(Seq( 334 IssueBlockParams(Seq( 335 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 336 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(7, 1))), true, 2), 337 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 338 IssueBlockParams(Seq( 339 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 340 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 2, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(5, 1))), true, 2), 341 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 342 IssueBlockParams(Seq( 343 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 344 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 0, 1), FpWB(port = 4, 0), VfWB(5, 1)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(3, 1)))), 345 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 346 IssueBlockParams(Seq( 347 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 348 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(1, 1)))), 349 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 350 ), 351 numPregs = intPreg.numEntries, 352 numDeqOutside = 0, 353 schdType = schdType, 354 rfDataWidth = intPreg.dataCfg.dataWidth, 355 numUopIn = dpParams.IntDqDeqWidth, 356 ) 357 } 358 359 val fpSchdParams = { 360 implicit val schdType: SchedulerType = FpScheduler() 361 SchdBlockParams(Seq( 362 IssueBlockParams(Seq( 363 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 1), VfWB(port = 1, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)))), 364 ExeUnitParams("FEX1", Seq(FmacCfg), Seq(FpWB(port = 1, 0)), Seq(Seq(FpRD(2, 0)), Seq(FpRD(3, 0)), Seq(FpRD(4, 0)))), 365 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 366 IssueBlockParams(Seq( 367 ExeUnitParams("FEX2", Seq(FaluCfg), Seq(FpWB(port = 2, 0), IntWB(port = 0, 2)), Seq(Seq(FpRD(5, 0)), Seq(FpRD(6, 0)))), 368 ExeUnitParams("FEX3", Seq(FmacCfg), Seq(FpWB(port = 3, 0)), Seq(Seq(FpRD(7, 0)), Seq(FpRD(8, 0)), Seq(FpRD(9, 0)))), 369 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 370 IssueBlockParams(Seq( 371 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 372 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 5, 1)), Seq(Seq(FpRD(12, 0)), Seq(FpRD(13, 0)))), 373 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 374 ), 375 numPregs = fpPreg.numEntries, 376 numDeqOutside = 0, 377 schdType = schdType, 378 rfDataWidth = fpPreg.dataCfg.dataWidth, 379 numUopIn = dpParams.VecDqDeqWidth, 380 ) 381 } 382 383 val vfSchdParams = { 384 implicit val schdType: SchedulerType = VfScheduler() 385 SchdBlockParams(Seq( 386 IssueBlockParams(Seq( 387 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 388 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 5, 0), IntWB(port = 2, 2)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 389 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 390 IssueBlockParams(Seq( 391 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 6, 0)), Seq(Seq(VfRD(7, 1)), Seq(VfRD(8, 1)), Seq(VfRD(9, 1)), Seq(VfRD(5, 1)), Seq(VfRD(6, 1)))), 392 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 7, 0), IntWB(port = 3, 2)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)))), 393 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 394 IssueBlockParams(Seq( 395 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 2, 0)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(0, 2)), Seq(VfRD(1, 2)), Seq(VfRD(2, 2)))), 396 ExeUnitParams("VFEX5", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 0)), Seq(Seq(VfRD(8, 2)), Seq(VfRD(9, 2)), Seq(VfRD(5, 2)), Seq(VfRD(6, 2)), Seq(VfRD(7, 2)))), 397 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 398 ), 399 numPregs = vfPreg.numEntries, 400 numDeqOutside = 0, 401 schdType = schdType, 402 rfDataWidth = vfPreg.dataCfg.dataWidth, 403 numUopIn = dpParams.VecDqDeqWidth, 404 ) 405 } 406 407 val memSchdParams = { 408 implicit val schdType: SchedulerType = MemScheduler() 409 val rfDataWidth = 64 410 411 SchdBlockParams(Seq( 412 IssueBlockParams(Seq( 413 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(8, 1)))), 414 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 415 IssueBlockParams(Seq( 416 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(9, 1)))), 417 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 418 IssueBlockParams(Seq( 419 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 420 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 421 IssueBlockParams(Seq( 422 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 423 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 424 IssueBlockParams(Seq( 425 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 426 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 427 IssueBlockParams(Seq( 428 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(0, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(VfRD(12, 0)), Seq(VfRD(13, 0)), Seq(VfRD(14, 0)))), 429 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 430 IssueBlockParams(Seq( 431 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(10, 1), FpRD(14, 0)))), 432 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 433 IssueBlockParams(Seq( 434 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(11, 1), FpRD(15, 0)))), 435 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 436 ), 437 numPregs = intPreg.numEntries max vfPreg.numEntries, 438 numDeqOutside = 0, 439 schdType = schdType, 440 rfDataWidth = rfDataWidth, 441 numUopIn = dpParams.LsDqDeqWidth, 442 ) 443 } 444 445 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 446 447 def iqWakeUpParams = { 448 Seq( 449 WakeUpConfig( 450 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 451 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 452 ), 453 WakeUpConfig( 454 Seq("FEX0", "FEX1", "FEX2", "FEX3", "LDU0", "LDU1", "LDU2") -> 455 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 456 ), 457 WakeUpConfig( 458 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 459 Seq("STD0", "STD1") 460 ), 461 WakeUpConfig( 462 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 463 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "VFEX4", "VFEX5") 464 ), 465 ).flatten 466 } 467 468 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 469 470 val backendParams: BackendParams = backend.BackendParams( 471 Map( 472 IntScheduler() -> intSchdParams, 473 FpScheduler() -> fpSchdParams, 474 VfScheduler() -> vfSchdParams, 475 MemScheduler() -> memSchdParams, 476 ), 477 Seq( 478 intPreg, 479 fpPreg, 480 vfPreg, 481 fakeIntPreg 482 ), 483 iqWakeUpParams, 484 ) 485} 486 487case object DebugOptionsKey extends Field[DebugOptions] 488 489case class DebugOptions 490( 491 FPGAPlatform: Boolean = false, 492 ResetGen: Boolean = false, 493 EnableDifftest: Boolean = false, 494 AlwaysBasicDiff: Boolean = true, 495 EnableDebug: Boolean = false, 496 EnablePerfDebug: Boolean = true, 497 UseDRAMSim: Boolean = false, 498 EnableConstantin: Boolean = false, 499 EnableChiselDB: Boolean = false, 500 AlwaysBasicDB: Boolean = true, 501 EnableTopDown: Boolean = false, 502 EnableRollingDB: Boolean = false 503) 504 505trait HasXSParameter { 506 507 implicit val p: Parameters 508 509 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 510 def NodeIDWidth = p(SoCParamsKey).NodeIDWidth // NodeID width among NoC 511 512 def coreParams = p(XSCoreParamsKey) 513 def env = p(DebugOptionsKey) 514 515 def XLEN = coreParams.XLEN 516 def VLEN = coreParams.VLEN 517 def ELEN = coreParams.ELEN 518 def HSXLEN = coreParams.HSXLEN 519 val minFLen = 32 520 val fLen = 64 521 def hartIdLen = p(MaxHartIdBits) 522 val xLen = XLEN 523 524 def HasMExtension = coreParams.HasMExtension 525 def HasCExtension = coreParams.HasCExtension 526 def HasHExtension = coreParams.HasHExtension 527 def HasDiv = coreParams.HasDiv 528 def HasIcache = coreParams.HasICache 529 def HasDcache = coreParams.HasDCache 530 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 531 def GPAddrBits = coreParams.GPAddrBits 532 def VAddrBits = { 533 if(HasHExtension){ 534 coreParams.GPAddrBits 535 }else{ 536 coreParams.VAddrBits 537 } 538 } // VAddrBits is Virtual Memory addr bits 539 540 def AsidLength = coreParams.AsidLength 541 def VmidLength = coreParams.VmidLength 542 def ReSelectLen = coreParams.ReSelectLen 543 def AddrBytes = AddrBits / 8 // unused 544 def DataBits = XLEN 545 def DataBytes = DataBits / 8 546 def VDataBytes = VLEN / 8 547 def HasFPU = coreParams.HasFPU 548 def HasVPU = coreParams.HasVPU 549 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 550 def FetchWidth = coreParams.FetchWidth 551 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 552 def EnableBPU = coreParams.EnableBPU 553 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 554 def EnableRAS = coreParams.EnableRAS 555 def EnableLB = coreParams.EnableLB 556 def EnableLoop = coreParams.EnableLoop 557 def EnableSC = coreParams.EnableSC 558 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 559 def HistoryLength = coreParams.HistoryLength 560 def EnableGHistDiff = coreParams.EnableGHistDiff 561 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 562 def EnableClockGate = coreParams.EnableClockGate 563 def UbtbGHRLength = coreParams.UbtbGHRLength 564 def UbtbSize = coreParams.UbtbSize 565 def EnableFauFTB = coreParams.EnableFauFTB 566 def FtbSize = coreParams.FtbSize 567 def FtbWays = coreParams.FtbWays 568 def RasSize = coreParams.RasSize 569 def RasSpecSize = coreParams.RasSpecSize 570 def RasCtrSize = coreParams.RasCtrSize 571 572 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 573 coreParams.branchPredictor(resp_in, p) 574 } 575 def numBr = coreParams.numBr 576 def TageTableInfos = coreParams.TageTableInfos 577 def TageBanks = coreParams.numBr 578 def SCNRows = coreParams.SCNRows 579 def SCCtrBits = coreParams.SCCtrBits 580 def SCHistLens = coreParams.SCHistLens 581 def SCNTables = coreParams.SCNTables 582 583 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 584 case ((n, cb), h) => (n, cb, h) 585 } 586 def ITTageTableInfos = coreParams.ITTageTableInfos 587 type FoldedHistoryInfo = Tuple2[Int, Int] 588 def foldedGHistInfos = 589 (TageTableInfos.map{ case (nRows, h, t) => 590 if (h > 0) 591 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 592 else 593 Set[FoldedHistoryInfo]() 594 }.reduce(_++_).toSet ++ 595 SCTableInfos.map{ case (nRows, _, h) => 596 if (h > 0) 597 Set((h, min(log2Ceil(nRows/TageBanks), h))) 598 else 599 Set[FoldedHistoryInfo]() 600 }.reduce(_++_).toSet ++ 601 ITTageTableInfos.map{ case (nRows, h, t) => 602 if (h > 0) 603 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 604 else 605 Set[FoldedHistoryInfo]() 606 }.reduce(_++_) ++ 607 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 608 ).toList 609 610 611 612 def CacheLineSize = coreParams.CacheLineSize 613 def CacheLineHalfWord = CacheLineSize / 16 614 def ExtHistoryLength = HistoryLength + 64 615 def ICacheECCForceError = coreParams.ICacheECCForceError 616 def IBufSize = coreParams.IBufSize 617 def IBufNBank = coreParams.IBufNBank 618 def backendParams: BackendParams = coreParams.backendParams 619 def DecodeWidth = coreParams.DecodeWidth 620 def RenameWidth = coreParams.RenameWidth 621 def CommitWidth = coreParams.CommitWidth 622 def RobCommitWidth = coreParams.RobCommitWidth 623 def RabCommitWidth = coreParams.RabCommitWidth 624 def MaxUopSize = coreParams.MaxUopSize 625 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 626 def RenameSnapshotNum = coreParams.RenameSnapshotNum 627 def FtqSize = coreParams.FtqSize 628 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 629 def IntLogicRegs = coreParams.IntLogicRegs 630 def FpLogicRegs = coreParams.FpLogicRegs 631 def VecLogicRegs = coreParams.VecLogicRegs 632 def VCONFIG_IDX = coreParams.VCONFIG_IDX 633 def IntPhyRegs = coreParams.intPreg.numEntries 634 def FpPhyRegs = coreParams.fpPreg.numEntries 635 def VfPhyRegs = coreParams.vfPreg.numEntries 636 def MaxPhyPregs = IntPhyRegs max VfPhyRegs 637 def PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 638 def RobSize = coreParams.RobSize 639 def RabSize = coreParams.RabSize 640 def VTypeBufferSize = coreParams.VTypeBufferSize 641 def IntRefCounterWidth = log2Ceil(RobSize) 642 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 643 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 644 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 645 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 646 def LoadQueueRARSize = coreParams.LoadQueueRARSize 647 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 648 def RollbackGroupSize = coreParams.RollbackGroupSize 649 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 650 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 651 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 652 def StoreQueueSize = coreParams.StoreQueueSize 653 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 654 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 655 def VlsQueueSize = coreParams.VlsQueueSize 656 def dpParams = coreParams.dpParams 657 658 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 659 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 660 661 def NumRedirect = backendParams.numRedirect 662 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 663 def FtqRedirectAheadNum = NumRedirect 664 def LoadPipelineWidth = coreParams.LoadPipelineWidth 665 def StorePipelineWidth = coreParams.StorePipelineWidth 666 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 667 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 668 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 669 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 670 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 671 def StoreBufferSize = coreParams.StoreBufferSize 672 def StoreBufferThreshold = coreParams.StoreBufferThreshold 673 def EnsbufferWidth = coreParams.EnsbufferWidth 674 def LoadDependencyWidth = coreParams.LoadDependencyWidth 675 def UsQueueSize = coreParams.UsQueueSize 676 def VlFlowSize = coreParams.VlFlowSize 677 def VlUopSize = coreParams.VlUopSize 678 def VsFlowL1Size = coreParams.VsFlowL1Size 679 def VsFlowL2Size = coreParams.VsFlowL2Size 680 def VsUopSize = coreParams.VsUopSize 681 def UncacheBufferSize = coreParams.UncacheBufferSize 682 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 683 def EnableFastForward = coreParams.EnableFastForward 684 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 685 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 686 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 687 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 688 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 689 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 690 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 691 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 692 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 693 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 694 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 695 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 696 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 697 def asidLen = coreParams.MMUAsidLen 698 def vmidLen = coreParams.MMUVmidLen 699 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 700 def refillBothTlb = coreParams.refillBothTlb 701 def iwpuParam = coreParams.iwpuParameters 702 def dwpuParam = coreParams.dwpuParameters 703 def itlbParams = coreParams.itlbParameters 704 def ldtlbParams = coreParams.ldtlbParameters 705 def sttlbParams = coreParams.sttlbParameters 706 def hytlbParams = coreParams.hytlbParameters 707 def pftlbParams = coreParams.pftlbParameters 708 def l2ToL1Params = coreParams.l2ToL1tlbParameters 709 def btlbParams = coreParams.btlbParameters 710 def l2tlbParams = coreParams.l2tlbParameters 711 def NumPerfCounters = coreParams.NumPerfCounters 712 713 def instBytes = if (HasCExtension) 2 else 4 714 def instOffsetBits = log2Ceil(instBytes) 715 716 def icacheParameters = coreParams.icacheParameters 717 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 718 719 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 720 // for constrained LR/SC loop 721 def LRSCCycles = 64 722 // for lr storm 723 def LRSCBackOff = 8 724 725 // cache hierarchy configurations 726 def l1BusDataWidth = 256 727 728 // load violation predict 729 def ResetTimeMax2Pow = 20 //1078576 730 def ResetTimeMin2Pow = 10 //1024 731 // wait table parameters 732 def WaitTableSize = 1024 733 def MemPredPCWidth = log2Up(WaitTableSize) 734 def LWTUse2BitCounter = true 735 // store set parameters 736 def SSITSize = WaitTableSize 737 def LFSTSize = 32 738 def SSIDWidth = log2Up(LFSTSize) 739 def LFSTWidth = 4 740 def StoreSetEnable = true // LWT will be disabled if SS is enabled 741 def LFSTEnable = true 742 743 def PCntIncrStep: Int = 6 744 def numPCntHc: Int = 25 745 def numPCntPtw: Int = 19 746 747 def numCSRPCntFrontend = 8 748 def numCSRPCntCtrl = 8 749 def numCSRPCntLsu = 8 750 def numCSRPCntHc = 5 751 def printEventCoding = true 752 753 // Parameters for Sdtrig extension 754 protected def TriggerNum = 4 755 protected def TriggerChainMaxLength = 2 756} 757