core: add basic debug mode features (#918)

Basic features of debug mode are implemented.

* Rewrite CSR for debug mode
* Peripheral work for implementing debug module
* Added single step support

core: add basic debug mode features (#918)

Basic features of debug mode are implemented.

* Rewrite CSR for debug mode
* Peripheral work for implementing debug module
* Added single step support
* Use difftest with JTAG support

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Merge branch 'master' into merge-master

bpu: add support for path hist

misc: update MinimalConfig and add it to ci

misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

configs: change function unit configs for MinimalConfig (#884)

* change the number of function units in MinimalConfig
* remove some hard-wired values

config: add a MinimalSimConfigForFetch

configs: change function unit configs for MinimalConfig (#884)

* change the number of function units in MinimalConfig
* remove some hard-wired values

[WIP] finish ftq logic and fix syntax errors

* Now can pass compiling.

[WIP] comment out-of-date code in frontend

[WIP] move NewFtq to xiangshan.frontend and rename class to Ftq

Ibuffer: update s

[WIP] finish ftq logic and fix syntax errors

* Now can pass compiling.

[WIP] comment out-of-date code in frontend

[WIP] move NewFtq to xiangshan.frontend and rename class to Ftq

Ibuffer: update sigal names for new IFU

[WIP] remove redundant NewFrontend

[WIP] set entry_fetch_status to f_sent once send req to buf

Fix syntax error in IFU

Fix syntax error in IFU/ICache/Ibuffer

[WIP] indent fix in ftq

BPU: Move GlobalHistory define from IFU.scala to BPU.scala

[WIP] fix some compilation errors

BPU: Remove HasIFUConst
and move some bundles from BPU.scala to frontendBundle.scala

[WIP] fix some compilation errors

[WIP] rename ftq-bpu ios

[WIP] recover some const definitions

[WIP] fix some compilation errors

[WIP]connect some IOs in frontend

BPU: fix syntax error

[WIP] fix compilation errors in predecode

BPU: fix RAS syntax error

[WIP] add some simulation perf counters back

BPU: Remove numBr redefine in ubtb and bim

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Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.

Configs: update MinimalConfig for FPGA (#809)

* Configs: add MinimalFPGAConfig

* TODO: change cache parameters

* Chore: add parameter print

* README: add simulation usage

Currently, Xian

Configs: update MinimalConfig for FPGA (#809)

* Configs: add MinimalFPGAConfig

* TODO: change cache parameters

* Chore: add parameter print

* README: add simulation usage

Currently, XiangShan does not support NOOP FPGA. FPGA related
instructions are removed

* Configs: limit frontend width in MinimalConfig

* MinimalConfig: limit L1/L2 cache size

* MinimalConfig: limit ptw size, disable L2

* MinimalConfig: limit L3 size

* Sbuffer: force trigger write if sbuffer fulls

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Disable L2 and L3 in MinimalConfig

Rewrite arg parser