1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package top 17 18import chisel3._ 19import chisel3.util._ 20import xiangshan._ 21import utils._ 22import system._ 23import chipsalliance.rocketchip.config._ 24import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 25import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExuParameters 28import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters} 29import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 30 31class DefaultConfig(n: Int) extends Config((site, here, up) => { 32 case XLen => 64 33 case DebugOptionsKey => DebugOptions() 34 case SoCParamsKey => SoCParameters( 35 cores = List.tabulate(n){ i => XSCoreParameters(HartId = i) } 36 ) 37}) 38 39// Synthesizable minimal XiangShan 40// * It is still an out-of-order, super-scalaer arch 41// * L1 cache included 42// * L2 cache NOT included 43// * L3 cache included 44class MinimalConfig(n: Int = 1) extends Config( 45 new DefaultConfig(n).alter((site, here, up) => { 46 case SoCParamsKey => up(SoCParamsKey).copy( 47 cores = up(SoCParamsKey).cores.map(_.copy( 48 DecodeWidth = 2, 49 RenameWidth = 2, 50 FetchWidth = 4, 51 IssQueSize = 8, 52 NRPhyRegs = 64, 53 LoadQueueSize = 16, 54 StoreQueueSize = 12, 55 RoqSize = 32, 56 BrqSize = 8, 57 FtqSize = 8, 58 IBufSize = 16, 59 StoreBufferSize = 4, 60 StoreBufferThreshold = 3, 61 dpParams = DispatchParameters( 62 IntDqSize = 12, 63 FpDqSize = 12, 64 LsDqSize = 12, 65 IntDqDeqWidth = 4, 66 FpDqDeqWidth = 4, 67 LsDqDeqWidth = 4 68 ), 69 exuParameters = ExuParameters( 70 JmpCnt = 1, 71 AluCnt = 2, 72 MulCnt = 0, 73 MduCnt = 1, 74 FmacCnt = 1, 75 FmiscCnt = 1, 76 FmiscDivSqrtCnt = 0, 77 LduCnt = 2, 78 StuCnt = 2 79 ), 80 icacheParameters = ICacheParameters( 81 nSets = 64, // 16KB ICache 82 tagECC = Some("parity"), 83 dataECC = Some("parity"), 84 replacer = Some("setplru"), 85 nMissEntries = 2 86 ), 87 dcacheParameters = DCacheParameters( 88 nSets = 64, // 32KB DCache 89 nWays = 8, 90 tagECC = Some("secded"), 91 dataECC = Some("secded"), 92 replacer = Some("setplru"), 93 nMissEntries = 4, 94 nProbeEntries = 4, 95 nReleaseEntries = 4, 96 nStoreReplayEntries = 4, 97 ), 98 L2Size = 128 * 1024, // 128KB 99 L2NWays = 8, 100 EnableBPD = false, // disable TAGE 101 EnableLoop = false, 102 TlbEntrySize = 4, 103 TlbSPEntrySize = 2, 104 PtwL1EntrySize = 2, 105 PtwL2EntrySize = 64, 106 PtwL3EntrySize = 128, 107 PtwSPEntrySize = 2, 108 useFakeL2Cache = true, 109 )), 110 L3Size = 32 * 1024, // 32KB 111 ) 112 }) 113) 114 115// Non-synthesizable MinimalConfig, for fast simulation only 116class MinimalSimConfig(n: Int = 1) extends Config( 117 new MinimalConfig(n).alter((site, here, up) => { 118 case SoCParamsKey => up(SoCParamsKey).copy( 119 cores = up(SoCParamsKey).cores.map(_.copy( 120 useFakeDCache = true, 121 useFakePTW = true, 122 useFakeL1plusCache = true, 123 )), 124 useFakeL3Cache = true 125 ) 126 }) 127) 128