1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package top 17 18import chisel3._ 19import chisel3.util._ 20import xiangshan._ 21import utils._ 22import system._ 23import chipsalliance.rocketchip.config._ 24import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 25import sifive.blocks.inclusivecache.{InclusiveCache, InclusiveCacheMicroParameters, CacheParameters} 26import xiangshan.frontend.{ICacheParameters} 27import xiangshan.backend.dispatch.DispatchParameters 28import xiangshan.cache.{DCacheParameters, L1plusCacheParameters} 29import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 30 31class DefaultConfig(n: Int) extends Config((site, here, up) => { 32 case XLen => 64 33 case DebugOptionsKey => DebugOptions() 34 case SoCParamsKey => SoCParameters( 35 cores = List.tabulate(n){ i => XSCoreParameters(HartId = i) } 36 ) 37}) 38 39// Synthesizable minimal XiangShan 40// * It is still an out-of-order, super-scalaer arch 41// * L1 cache included 42// * L2 cache NOT included 43// * L3 cache included 44class MinimalConfig(n: Int = 1) extends Config( 45 new DefaultConfig(n).alter((site, here, up) => { 46 case SoCParamsKey => up(SoCParamsKey).copy( 47 cores = up(SoCParamsKey).cores.map(_.copy( 48 DecodeWidth = 2, 49 RenameWidth = 2, 50 FetchWidth = 4, 51 IssQueSize = 8, 52 NRPhyRegs = 80, 53 LoadQueueSize = 16, 54 StoreQueueSize = 16, 55 RoqSize = 32, 56 BrqSize = 8, 57 FtqSize = 16, 58 IBufSize = 16, 59 StoreBufferSize = 4, 60 StoreBufferThreshold = 3, 61 dpParams = DispatchParameters( 62 IntDqSize = 8, 63 FpDqSize = 8, 64 LsDqSize = 8, 65 IntDqDeqWidth = 4, 66 FpDqDeqWidth = 4, 67 LsDqDeqWidth = 4 68 ), 69 icacheParameters = ICacheParameters( 70 nSets = 8, // 4KB ICache 71 tagECC = Some("parity"), 72 dataECC = Some("parity"), 73 replacer = Some("setplru"), 74 nMissEntries = 2 75 ), 76 dcacheParameters = DCacheParameters( 77 nSets = 8, // 4KB DCache 78 nWays = 4, 79 tagECC = Some("secded"), 80 dataECC = Some("secded"), 81 replacer = Some("setplru"), 82 nMissEntries = 4, 83 nProbeEntries = 4, 84 nReleaseEntries = 4, 85 nStoreReplayEntries = 4, 86 ), 87 L2Size = 16 * 1024, // 16KB 88 L2NWays = 8, 89 EnableBPD = false, // disable TAGE 90 EnableLoop = false, 91 TlbEntrySize = 4, 92 TlbSPEntrySize = 2, 93 PtwL1EntrySize = 2, 94 PtwL2EntrySize = 64, 95 PtwL3EntrySize = 128, 96 PtwSPEntrySize = 2, 97 useFakeL2Cache = true, 98 )), 99 L3Size = 32 * 1024, // 32KB 100 ) 101 }) 102) 103 104// Non-synthesizable MinimalConfig, for fast simulation only 105class MinimalSimConfig(n: Int = 1) extends Config( 106 new MinimalConfig(n).alter((site, here, up) => { 107 case SoCParamsKey => up(SoCParamsKey).copy( 108 cores = up(SoCParamsKey).cores.map(_.copy( 109 useFakeDCache = true, 110 useFakePTW = true, 111 useFakeL1plusCache = true, 112 )), 113 useFakeL3Cache = true 114 ) 115 }) 116) 117 118class MinimalSimConfigForFetch(n: Int = 1) extends Config( 119 new MinimalSimConfig(n).alter((site, here, up) => { 120 case SoCParamsKey => up(SoCParamsKey).copy( 121 cores = up(SoCParamsKey).cores.map(_.copy( 122 FetchWidth = 8 123 )) 124 ) 125 }) 126) 127