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Searched full:miss (Results 1 – 21 of 21) sorted by relevance

/nrf52832-nimble/rt-thread/libcpu/c-sky/common/
H A Dcsi_core.h222 \brief cache miss times
223 \details Cache miss times
224 \note every 256 miss add 1.
/nrf52832-nimble/rt-thread/libcpu/avr32/uc3/
H A Dexception_gcc.S167 // ITLB Miss.
172 // DTLB Miss (Read).
177 // DTLB Miss (Write).
/nrf52832-nimble/rt-thread/libcpu/mips/xburst/
H A Dexception.c57 rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); in tlb_refill_handler()
/nrf52832-nimble/rt-thread/libcpu/mips/loongson_1c/
H A Dexception.c50 rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); in tlb_refill_handler()
/nrf52832-nimble/rt-thread/libcpu/mips/loongson_1b/
H A Dexception.c50 rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); in tlb_refill_handler()
/nrf52832-nimble/rt-thread/libcpu/ppc/ppc405/include/asm/
H A Dprocessor.h198 #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
226 #define ESR_DST 0x00800000 /* Storage Exception - Data miss */
303 #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
412 #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
576 #define DMISS SPRN_DMISS /* Data TLB Miss Register */
604 #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
/nrf52832-nimble/packages/NimBLE-latest/nimble/host/mesh/
H A Dsyscfg.yml208 is that the node may miss out on messages intended for it
/nrf52832-nimble/rt-thread/libcpu/mips/x1000/
H A Dmips_excpt.c377 rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); in mips_tlb_refill_handler()
/nrf52832-nimble/packages/NimBLE-latest/nimble/controller/src/
H A Dble_ll_sched.c362 * could miss the transmit window. A final note: the actual transmission in ble_ll_sched_master_new()
592 * could miss the transmit window. A final note: the actual transmission in ble_ll_sched_master_new()
H A Dble_ll_scan.c2041 * we do miss original event type, which we need for advertising report. in ble_ll_scan_parse_ext_hdr()
/nrf52832-nimble/packages/NimBLE-latest/nimble/drivers/nrf52/src/
H A Dble_phy.c612 * to be scheduled 1 or 2 ticks too late so we'll miss it - it's acceptable in ble_phy_set_start_now()
1014 * armed) so we may simply miss the slot and set the timer in the past. in ble_phy_rx_end_isr()
/nrf52832-nimble/packages/NimBLE-latest/nimble/drivers/nrf51/src/
H A Dble_phy.c329 * more time and thus less of a chance to miss a tick. Another note: we in ble_phy_set_start_time()
/nrf52832-nimble/nordic/nrfx/mdk/
H A Dnrf9160.h1885 …__IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter …
H A Dnrf52.h2100 …__IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-Code cache miss counter. …
H A Dnrf52840.h2357 …__IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter. …
H A Dnrf9160_bitfields.h2622 /* Description: I-code cache miss counter */
H A Dnrf52_bitfields.h4824 /* Description: I-Code cache miss counter. */
H A Dnrf52840_bitfields.h4910 /* Description: I-code cache miss counter. */
H A Dnrf9160.svd28401 <description>I-code cache miss counter</description>
H A Dnrf52.svd28051 <description>I-Code cache miss counter.</description>
H A Dnrf52840.svd31293 <description>I-code cache miss counter.</description>