1*150812a8SEvalZero /* 2*150812a8SEvalZero * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. 3*150812a8SEvalZero * 4*150812a8SEvalZero * Redistribution and use in source and binary forms, with or without 5*150812a8SEvalZero * modification, are permitted provided that the following conditions are met: 6*150812a8SEvalZero * 7*150812a8SEvalZero * 1. Redistributions of source code must retain the above copyright notice, this 8*150812a8SEvalZero * list of conditions and the following disclaimer. 9*150812a8SEvalZero * 10*150812a8SEvalZero * 2. Redistributions in binary form must reproduce the above copyright 11*150812a8SEvalZero * notice, this list of conditions and the following disclaimer in the 12*150812a8SEvalZero * documentation and/or other materials provided with the distribution. 13*150812a8SEvalZero * 14*150812a8SEvalZero * 3. Neither the name of Nordic Semiconductor ASA nor the names of its 15*150812a8SEvalZero * contributors may be used to endorse or promote products derived from this 16*150812a8SEvalZero * software without specific prior written permission. 17*150812a8SEvalZero * 18*150812a8SEvalZero * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*150812a8SEvalZero * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*150812a8SEvalZero * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 21*150812a8SEvalZero * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 22*150812a8SEvalZero * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*150812a8SEvalZero * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*150812a8SEvalZero * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*150812a8SEvalZero * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*150812a8SEvalZero * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*150812a8SEvalZero * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*150812a8SEvalZero * POSSIBILITY OF SUCH DAMAGE. 29*150812a8SEvalZero * 30*150812a8SEvalZero * @file nrf52.h 31*150812a8SEvalZero * @brief CMSIS HeaderFile 32*150812a8SEvalZero * @version 1 33*150812a8SEvalZero * @date 03. December 2018 34*150812a8SEvalZero * @note Generated by SVDConv V3.3.18 on Monday, 03.12.2018 11:18:25 35*150812a8SEvalZero * from File 'nrf52.svd', 36*150812a8SEvalZero * last modified on Monday, 03.12.2018 10:18:20 37*150812a8SEvalZero */ 38*150812a8SEvalZero 39*150812a8SEvalZero 40*150812a8SEvalZero 41*150812a8SEvalZero /** @addtogroup Nordic Semiconductor 42*150812a8SEvalZero * @{ 43*150812a8SEvalZero */ 44*150812a8SEvalZero 45*150812a8SEvalZero 46*150812a8SEvalZero /** @addtogroup nrf52 47*150812a8SEvalZero * @{ 48*150812a8SEvalZero */ 49*150812a8SEvalZero 50*150812a8SEvalZero 51*150812a8SEvalZero #ifndef NRF52_H 52*150812a8SEvalZero #define NRF52_H 53*150812a8SEvalZero 54*150812a8SEvalZero #ifdef __cplusplus 55*150812a8SEvalZero extern "C" { 56*150812a8SEvalZero #endif 57*150812a8SEvalZero 58*150812a8SEvalZero 59*150812a8SEvalZero /** @addtogroup Configuration_of_CMSIS 60*150812a8SEvalZero * @{ 61*150812a8SEvalZero */ 62*150812a8SEvalZero 63*150812a8SEvalZero 64*150812a8SEvalZero 65*150812a8SEvalZero /* =========================================================================================================================== */ 66*150812a8SEvalZero /* ================ Interrupt Number Definition ================ */ 67*150812a8SEvalZero /* =========================================================================================================================== */ 68*150812a8SEvalZero 69*150812a8SEvalZero typedef enum { 70*150812a8SEvalZero /* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ 71*150812a8SEvalZero Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 72*150812a8SEvalZero NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 73*150812a8SEvalZero HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 74*150812a8SEvalZero MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 75*150812a8SEvalZero and No Match */ 76*150812a8SEvalZero BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 77*150812a8SEvalZero related Fault */ 78*150812a8SEvalZero UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 79*150812a8SEvalZero SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 80*150812a8SEvalZero DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 81*150812a8SEvalZero PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 82*150812a8SEvalZero SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 83*150812a8SEvalZero /* =========================================== nrf52 Specific Interrupt Numbers ============================================ */ 84*150812a8SEvalZero POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 85*150812a8SEvalZero RADIO_IRQn = 1, /*!< 1 RADIO */ 86*150812a8SEvalZero UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ 87*150812a8SEvalZero SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ 88*150812a8SEvalZero SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ 89*150812a8SEvalZero NFCT_IRQn = 5, /*!< 5 NFCT */ 90*150812a8SEvalZero GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 91*150812a8SEvalZero SAADC_IRQn = 7, /*!< 7 SAADC */ 92*150812a8SEvalZero TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 93*150812a8SEvalZero TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 94*150812a8SEvalZero TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 95*150812a8SEvalZero RTC0_IRQn = 11, /*!< 11 RTC0 */ 96*150812a8SEvalZero TEMP_IRQn = 12, /*!< 12 TEMP */ 97*150812a8SEvalZero RNG_IRQn = 13, /*!< 13 RNG */ 98*150812a8SEvalZero ECB_IRQn = 14, /*!< 14 ECB */ 99*150812a8SEvalZero CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 100*150812a8SEvalZero WDT_IRQn = 16, /*!< 16 WDT */ 101*150812a8SEvalZero RTC1_IRQn = 17, /*!< 17 RTC1 */ 102*150812a8SEvalZero QDEC_IRQn = 18, /*!< 18 QDEC */ 103*150812a8SEvalZero COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ 104*150812a8SEvalZero SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ 105*150812a8SEvalZero SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ 106*150812a8SEvalZero SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ 107*150812a8SEvalZero SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ 108*150812a8SEvalZero SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ 109*150812a8SEvalZero SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ 110*150812a8SEvalZero TIMER3_IRQn = 26, /*!< 26 TIMER3 */ 111*150812a8SEvalZero TIMER4_IRQn = 27, /*!< 27 TIMER4 */ 112*150812a8SEvalZero PWM0_IRQn = 28, /*!< 28 PWM0 */ 113*150812a8SEvalZero PDM_IRQn = 29, /*!< 29 PDM */ 114*150812a8SEvalZero MWU_IRQn = 32, /*!< 32 MWU */ 115*150812a8SEvalZero PWM1_IRQn = 33, /*!< 33 PWM1 */ 116*150812a8SEvalZero PWM2_IRQn = 34, /*!< 34 PWM2 */ 117*150812a8SEvalZero SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ 118*150812a8SEvalZero RTC2_IRQn = 36, /*!< 36 RTC2 */ 119*150812a8SEvalZero I2S_IRQn = 37, /*!< 37 I2S */ 120*150812a8SEvalZero FPU_IRQn = 38 /*!< 38 FPU */ 121*150812a8SEvalZero } IRQn_Type; 122*150812a8SEvalZero 123*150812a8SEvalZero 124*150812a8SEvalZero 125*150812a8SEvalZero /* =========================================================================================================================== */ 126*150812a8SEvalZero /* ================ Processor and Core Peripheral Section ================ */ 127*150812a8SEvalZero /* =========================================================================================================================== */ 128*150812a8SEvalZero 129*150812a8SEvalZero /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ 130*150812a8SEvalZero #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 131*150812a8SEvalZero #define __DSP_PRESENT 0 /*!< DSP present or not */ 132*150812a8SEvalZero #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 133*150812a8SEvalZero #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 134*150812a8SEvalZero #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 135*150812a8SEvalZero #define __MPU_PRESENT 1 /*!< MPU present or not */ 136*150812a8SEvalZero #define __FPU_PRESENT 1 /*!< FPU present or not */ 137*150812a8SEvalZero 138*150812a8SEvalZero 139*150812a8SEvalZero /** @} */ /* End of group Configuration_of_CMSIS */ 140*150812a8SEvalZero 141*150812a8SEvalZero #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 142*150812a8SEvalZero #include "system_nrf52.h" /*!< nrf52 System */ 143*150812a8SEvalZero 144*150812a8SEvalZero #ifndef __IM /*!< Fallback for older CMSIS versions */ 145*150812a8SEvalZero #define __IM __I 146*150812a8SEvalZero #endif 147*150812a8SEvalZero #ifndef __OM /*!< Fallback for older CMSIS versions */ 148*150812a8SEvalZero #define __OM __O 149*150812a8SEvalZero #endif 150*150812a8SEvalZero #ifndef __IOM /*!< Fallback for older CMSIS versions */ 151*150812a8SEvalZero #define __IOM __IO 152*150812a8SEvalZero #endif 153*150812a8SEvalZero 154*150812a8SEvalZero 155*150812a8SEvalZero /* ======================================== Start of section using anonymous unions ======================================== */ 156*150812a8SEvalZero #if defined (__CC_ARM) 157*150812a8SEvalZero #pragma push 158*150812a8SEvalZero #pragma anon_unions 159*150812a8SEvalZero #elif defined (__ICCARM__) 160*150812a8SEvalZero #pragma language=extended 161*150812a8SEvalZero #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 162*150812a8SEvalZero #pragma clang diagnostic push 163*150812a8SEvalZero #pragma clang diagnostic ignored "-Wc11-extensions" 164*150812a8SEvalZero #pragma clang diagnostic ignored "-Wreserved-id-macro" 165*150812a8SEvalZero #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 166*150812a8SEvalZero #pragma clang diagnostic ignored "-Wnested-anon-types" 167*150812a8SEvalZero #elif defined (__GNUC__) 168*150812a8SEvalZero /* anonymous unions are enabled by default */ 169*150812a8SEvalZero #elif defined (__TMS470__) 170*150812a8SEvalZero /* anonymous unions are enabled by default */ 171*150812a8SEvalZero #elif defined (__TASKING__) 172*150812a8SEvalZero #pragma warning 586 173*150812a8SEvalZero #elif defined (__CSMC__) 174*150812a8SEvalZero /* anonymous unions are enabled by default */ 175*150812a8SEvalZero #else 176*150812a8SEvalZero #warning Not supported compiler type 177*150812a8SEvalZero #endif 178*150812a8SEvalZero 179*150812a8SEvalZero 180*150812a8SEvalZero /* =========================================================================================================================== */ 181*150812a8SEvalZero /* ================ Device Specific Cluster Section ================ */ 182*150812a8SEvalZero /* =========================================================================================================================== */ 183*150812a8SEvalZero 184*150812a8SEvalZero 185*150812a8SEvalZero /** @addtogroup Device_Peripheral_clusters 186*150812a8SEvalZero * @{ 187*150812a8SEvalZero */ 188*150812a8SEvalZero 189*150812a8SEvalZero 190*150812a8SEvalZero /** 191*150812a8SEvalZero * @brief FICR_INFO [INFO] (Device info) 192*150812a8SEvalZero */ 193*150812a8SEvalZero typedef struct { 194*150812a8SEvalZero __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ 195*150812a8SEvalZero __IM uint32_t VARIANT; /*!< (@ 0x00000004) Part Variant, Hardware version and Production 196*150812a8SEvalZero configuration */ 197*150812a8SEvalZero __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ 198*150812a8SEvalZero __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ 199*150812a8SEvalZero __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ 200*150812a8SEvalZero __IOM uint32_t UNUSED0[3]; /*!< (@ 0x00000014) Description collection[0]: Unspecified */ 201*150812a8SEvalZero } FICR_INFO_Type; /*!< Size = 32 (0x20) */ 202*150812a8SEvalZero 203*150812a8SEvalZero 204*150812a8SEvalZero /** 205*150812a8SEvalZero * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) 206*150812a8SEvalZero */ 207*150812a8SEvalZero typedef struct { 208*150812a8SEvalZero __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0. */ 209*150812a8SEvalZero __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1. */ 210*150812a8SEvalZero __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2. */ 211*150812a8SEvalZero __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3. */ 212*150812a8SEvalZero __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4. */ 213*150812a8SEvalZero __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5. */ 214*150812a8SEvalZero __IM uint32_t B0; /*!< (@ 0x00000018) y-intercept B0. */ 215*150812a8SEvalZero __IM uint32_t B1; /*!< (@ 0x0000001C) y-intercept B1. */ 216*150812a8SEvalZero __IM uint32_t B2; /*!< (@ 0x00000020) y-intercept B2. */ 217*150812a8SEvalZero __IM uint32_t B3; /*!< (@ 0x00000024) y-intercept B3. */ 218*150812a8SEvalZero __IM uint32_t B4; /*!< (@ 0x00000028) y-intercept B4. */ 219*150812a8SEvalZero __IM uint32_t B5; /*!< (@ 0x0000002C) y-intercept B5. */ 220*150812a8SEvalZero __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0. */ 221*150812a8SEvalZero __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1. */ 222*150812a8SEvalZero __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2. */ 223*150812a8SEvalZero __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3. */ 224*150812a8SEvalZero __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4. */ 225*150812a8SEvalZero } FICR_TEMP_Type; /*!< Size = 68 (0x44) */ 226*150812a8SEvalZero 227*150812a8SEvalZero 228*150812a8SEvalZero /** 229*150812a8SEvalZero * @brief FICR_NFC [NFC] (Unspecified) 230*150812a8SEvalZero */ 231*150812a8SEvalZero typedef struct { 232*150812a8SEvalZero __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC Tag. Software can read 233*150812a8SEvalZero these values to populate NFCID1_3RD_LAST, 234*150812a8SEvalZero NFCID1_2ND_LAST and NFCID1_LAST. */ 235*150812a8SEvalZero __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC Tag. Software can read 236*150812a8SEvalZero these values to populate NFCID1_3RD_LAST, 237*150812a8SEvalZero NFCID1_2ND_LAST and NFCID1_LAST. */ 238*150812a8SEvalZero __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC Tag. Software can read 239*150812a8SEvalZero these values to populate NFCID1_3RD_LAST, 240*150812a8SEvalZero NFCID1_2ND_LAST and NFCID1_LAST. */ 241*150812a8SEvalZero __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC Tag. Software can read 242*150812a8SEvalZero these values to populate NFCID1_3RD_LAST, 243*150812a8SEvalZero NFCID1_2ND_LAST and NFCID1_LAST. */ 244*150812a8SEvalZero } FICR_NFC_Type; /*!< Size = 16 (0x10) */ 245*150812a8SEvalZero 246*150812a8SEvalZero 247*150812a8SEvalZero /** 248*150812a8SEvalZero * @brief POWER_RAM [RAM] (Unspecified) 249*150812a8SEvalZero */ 250*150812a8SEvalZero typedef struct { 251*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[0]: RAM0 power control register */ 252*150812a8SEvalZero __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[0]: RAM0 power control set 253*150812a8SEvalZero register */ 254*150812a8SEvalZero __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[0]: RAM0 power control clear 255*150812a8SEvalZero register */ 256*150812a8SEvalZero __IM uint32_t RESERVED; 257*150812a8SEvalZero } POWER_RAM_Type; /*!< Size = 16 (0x10) */ 258*150812a8SEvalZero 259*150812a8SEvalZero 260*150812a8SEvalZero /** 261*150812a8SEvalZero * @brief UARTE_PSEL [PSEL] (Unspecified) 262*150812a8SEvalZero */ 263*150812a8SEvalZero typedef struct { 264*150812a8SEvalZero __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 265*150812a8SEvalZero __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 266*150812a8SEvalZero __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 267*150812a8SEvalZero __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 268*150812a8SEvalZero } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 269*150812a8SEvalZero 270*150812a8SEvalZero 271*150812a8SEvalZero /** 272*150812a8SEvalZero * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 273*150812a8SEvalZero */ 274*150812a8SEvalZero typedef struct { 275*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 276*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 277*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 278*150812a8SEvalZero } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 279*150812a8SEvalZero 280*150812a8SEvalZero 281*150812a8SEvalZero /** 282*150812a8SEvalZero * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 283*150812a8SEvalZero */ 284*150812a8SEvalZero typedef struct { 285*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 286*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 287*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 288*150812a8SEvalZero } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 289*150812a8SEvalZero 290*150812a8SEvalZero 291*150812a8SEvalZero /** 292*150812a8SEvalZero * @brief SPIM_PSEL [PSEL] (Unspecified) 293*150812a8SEvalZero */ 294*150812a8SEvalZero typedef struct { 295*150812a8SEvalZero __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 296*150812a8SEvalZero __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 297*150812a8SEvalZero __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 298*150812a8SEvalZero } SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ 299*150812a8SEvalZero 300*150812a8SEvalZero 301*150812a8SEvalZero /** 302*150812a8SEvalZero * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 303*150812a8SEvalZero */ 304*150812a8SEvalZero typedef struct { 305*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 306*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 307*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 308*150812a8SEvalZero __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 309*150812a8SEvalZero } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 310*150812a8SEvalZero 311*150812a8SEvalZero 312*150812a8SEvalZero /** 313*150812a8SEvalZero * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 314*150812a8SEvalZero */ 315*150812a8SEvalZero typedef struct { 316*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 317*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 318*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 319*150812a8SEvalZero __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 320*150812a8SEvalZero } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 321*150812a8SEvalZero 322*150812a8SEvalZero 323*150812a8SEvalZero /** 324*150812a8SEvalZero * @brief SPIS_PSEL [PSEL] (Unspecified) 325*150812a8SEvalZero */ 326*150812a8SEvalZero typedef struct { 327*150812a8SEvalZero __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 328*150812a8SEvalZero __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 329*150812a8SEvalZero __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 330*150812a8SEvalZero __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 331*150812a8SEvalZero } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 332*150812a8SEvalZero 333*150812a8SEvalZero 334*150812a8SEvalZero /** 335*150812a8SEvalZero * @brief SPIS_RXD [RXD] (Unspecified) 336*150812a8SEvalZero */ 337*150812a8SEvalZero typedef struct { 338*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 339*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 340*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 341*150812a8SEvalZero } SPIS_RXD_Type; /*!< Size = 12 (0xc) */ 342*150812a8SEvalZero 343*150812a8SEvalZero 344*150812a8SEvalZero /** 345*150812a8SEvalZero * @brief SPIS_TXD [TXD] (Unspecified) 346*150812a8SEvalZero */ 347*150812a8SEvalZero typedef struct { 348*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 349*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 350*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 351*150812a8SEvalZero } SPIS_TXD_Type; /*!< Size = 12 (0xc) */ 352*150812a8SEvalZero 353*150812a8SEvalZero 354*150812a8SEvalZero /** 355*150812a8SEvalZero * @brief TWIM_PSEL [PSEL] (Unspecified) 356*150812a8SEvalZero */ 357*150812a8SEvalZero typedef struct { 358*150812a8SEvalZero __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 359*150812a8SEvalZero __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 360*150812a8SEvalZero } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 361*150812a8SEvalZero 362*150812a8SEvalZero 363*150812a8SEvalZero /** 364*150812a8SEvalZero * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 365*150812a8SEvalZero */ 366*150812a8SEvalZero typedef struct { 367*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 368*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 369*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 370*150812a8SEvalZero __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 371*150812a8SEvalZero } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 372*150812a8SEvalZero 373*150812a8SEvalZero 374*150812a8SEvalZero /** 375*150812a8SEvalZero * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 376*150812a8SEvalZero */ 377*150812a8SEvalZero typedef struct { 378*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 379*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 380*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 381*150812a8SEvalZero __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 382*150812a8SEvalZero } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 383*150812a8SEvalZero 384*150812a8SEvalZero 385*150812a8SEvalZero /** 386*150812a8SEvalZero * @brief TWIS_PSEL [PSEL] (Unspecified) 387*150812a8SEvalZero */ 388*150812a8SEvalZero typedef struct { 389*150812a8SEvalZero __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 390*150812a8SEvalZero __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 391*150812a8SEvalZero } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 392*150812a8SEvalZero 393*150812a8SEvalZero 394*150812a8SEvalZero /** 395*150812a8SEvalZero * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 396*150812a8SEvalZero */ 397*150812a8SEvalZero typedef struct { 398*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 399*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 400*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 401*150812a8SEvalZero } TWIS_RXD_Type; /*!< Size = 12 (0xc) */ 402*150812a8SEvalZero 403*150812a8SEvalZero 404*150812a8SEvalZero /** 405*150812a8SEvalZero * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 406*150812a8SEvalZero */ 407*150812a8SEvalZero typedef struct { 408*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 409*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 410*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 411*150812a8SEvalZero } TWIS_TXD_Type; /*!< Size = 12 (0xc) */ 412*150812a8SEvalZero 413*150812a8SEvalZero 414*150812a8SEvalZero /** 415*150812a8SEvalZero * @brief SPI_PSEL [PSEL] (Unspecified) 416*150812a8SEvalZero */ 417*150812a8SEvalZero typedef struct { 418*150812a8SEvalZero __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 419*150812a8SEvalZero __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI */ 420*150812a8SEvalZero __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO */ 421*150812a8SEvalZero } SPI_PSEL_Type; /*!< Size = 12 (0xc) */ 422*150812a8SEvalZero 423*150812a8SEvalZero 424*150812a8SEvalZero /** 425*150812a8SEvalZero * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) 426*150812a8SEvalZero */ 427*150812a8SEvalZero typedef struct { 428*150812a8SEvalZero __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frames */ 429*150812a8SEvalZero } NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ 430*150812a8SEvalZero 431*150812a8SEvalZero 432*150812a8SEvalZero /** 433*150812a8SEvalZero * @brief NFCT_TXD [TXD] (Unspecified) 434*150812a8SEvalZero */ 435*150812a8SEvalZero typedef struct { 436*150812a8SEvalZero __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ 437*150812a8SEvalZero __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ 438*150812a8SEvalZero } NFCT_TXD_Type; /*!< Size = 8 (0x8) */ 439*150812a8SEvalZero 440*150812a8SEvalZero 441*150812a8SEvalZero /** 442*150812a8SEvalZero * @brief NFCT_RXD [RXD] (Unspecified) 443*150812a8SEvalZero */ 444*150812a8SEvalZero typedef struct { 445*150812a8SEvalZero __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ 446*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ 447*150812a8SEvalZero } NFCT_RXD_Type; /*!< Size = 8 (0x8) */ 448*150812a8SEvalZero 449*150812a8SEvalZero 450*150812a8SEvalZero /** 451*150812a8SEvalZero * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified) 452*150812a8SEvalZero */ 453*150812a8SEvalZero typedef struct { 454*150812a8SEvalZero __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[0]: Last results is equal 455*150812a8SEvalZero or above CH[0].LIMIT.HIGH */ 456*150812a8SEvalZero __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[0]: Last results is equal 457*150812a8SEvalZero or below CH[0].LIMIT.LOW */ 458*150812a8SEvalZero } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 459*150812a8SEvalZero 460*150812a8SEvalZero 461*150812a8SEvalZero /** 462*150812a8SEvalZero * @brief SAADC_CH [CH] (Unspecified) 463*150812a8SEvalZero */ 464*150812a8SEvalZero typedef struct { 465*150812a8SEvalZero __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[0]: Input positive pin selection 466*150812a8SEvalZero for CH[0] */ 467*150812a8SEvalZero __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[0]: Input negative pin selection 468*150812a8SEvalZero for CH[0] */ 469*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[0]: Input configuration for 470*150812a8SEvalZero CH[0] */ 471*150812a8SEvalZero __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[0]: High/low limits for event 472*150812a8SEvalZero monitoring a channel */ 473*150812a8SEvalZero } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 474*150812a8SEvalZero 475*150812a8SEvalZero 476*150812a8SEvalZero /** 477*150812a8SEvalZero * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 478*150812a8SEvalZero */ 479*150812a8SEvalZero typedef struct { 480*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 481*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 482*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last 483*150812a8SEvalZero START */ 484*150812a8SEvalZero } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 485*150812a8SEvalZero 486*150812a8SEvalZero 487*150812a8SEvalZero /** 488*150812a8SEvalZero * @brief QDEC_PSEL [PSEL] (Unspecified) 489*150812a8SEvalZero */ 490*150812a8SEvalZero typedef struct { 491*150812a8SEvalZero __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ 492*150812a8SEvalZero __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ 493*150812a8SEvalZero __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ 494*150812a8SEvalZero } QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ 495*150812a8SEvalZero 496*150812a8SEvalZero 497*150812a8SEvalZero /** 498*150812a8SEvalZero * @brief PWM_SEQ [SEQ] (Unspecified) 499*150812a8SEvalZero */ 500*150812a8SEvalZero typedef struct { 501*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[0]: Beginning address in 502*150812a8SEvalZero Data RAM of this sequence */ 503*150812a8SEvalZero __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[0]: Amount of values (duty 504*150812a8SEvalZero cycles) in this sequence */ 505*150812a8SEvalZero __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[0]: Amount of additional 506*150812a8SEvalZero PWM periods between samples loaded into 507*150812a8SEvalZero compare register */ 508*150812a8SEvalZero __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[0]: Time added after the 509*150812a8SEvalZero sequence */ 510*150812a8SEvalZero __IM uint32_t RESERVED[4]; 511*150812a8SEvalZero } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 512*150812a8SEvalZero 513*150812a8SEvalZero 514*150812a8SEvalZero /** 515*150812a8SEvalZero * @brief PWM_PSEL [PSEL] (Unspecified) 516*150812a8SEvalZero */ 517*150812a8SEvalZero typedef struct { 518*150812a8SEvalZero __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[0]: Output pin select 519*150812a8SEvalZero for PWM channel 0 */ 520*150812a8SEvalZero } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 521*150812a8SEvalZero 522*150812a8SEvalZero 523*150812a8SEvalZero /** 524*150812a8SEvalZero * @brief PDM_PSEL [PSEL] (Unspecified) 525*150812a8SEvalZero */ 526*150812a8SEvalZero typedef struct { 527*150812a8SEvalZero __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 528*150812a8SEvalZero __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 529*150812a8SEvalZero } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 530*150812a8SEvalZero 531*150812a8SEvalZero 532*150812a8SEvalZero /** 533*150812a8SEvalZero * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 534*150812a8SEvalZero */ 535*150812a8SEvalZero typedef struct { 536*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 537*150812a8SEvalZero EasyDMA */ 538*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 539*150812a8SEvalZero mode */ 540*150812a8SEvalZero } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 541*150812a8SEvalZero 542*150812a8SEvalZero 543*150812a8SEvalZero /** 544*150812a8SEvalZero * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) 545*150812a8SEvalZero */ 546*150812a8SEvalZero typedef struct { 547*150812a8SEvalZero __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[0]: Enable channel group 548*150812a8SEvalZero 0 */ 549*150812a8SEvalZero __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[0]: Disable channel group 550*150812a8SEvalZero 0 */ 551*150812a8SEvalZero } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 552*150812a8SEvalZero 553*150812a8SEvalZero 554*150812a8SEvalZero /** 555*150812a8SEvalZero * @brief PPI_CH [CH] (PPI Channel) 556*150812a8SEvalZero */ 557*150812a8SEvalZero typedef struct { 558*150812a8SEvalZero __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[0]: Channel 0 event end-point */ 559*150812a8SEvalZero __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[0]: Channel 0 task end-point */ 560*150812a8SEvalZero } PPI_CH_Type; /*!< Size = 8 (0x8) */ 561*150812a8SEvalZero 562*150812a8SEvalZero 563*150812a8SEvalZero /** 564*150812a8SEvalZero * @brief PPI_FORK [FORK] (Fork) 565*150812a8SEvalZero */ 566*150812a8SEvalZero typedef struct { 567*150812a8SEvalZero __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[0]: Channel 0 task end-point */ 568*150812a8SEvalZero } PPI_FORK_Type; /*!< Size = 4 (0x4) */ 569*150812a8SEvalZero 570*150812a8SEvalZero 571*150812a8SEvalZero /** 572*150812a8SEvalZero * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Unspecified) 573*150812a8SEvalZero */ 574*150812a8SEvalZero typedef struct { 575*150812a8SEvalZero __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[0]: Write access to region 576*150812a8SEvalZero 0 detected */ 577*150812a8SEvalZero __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[0]: Read access to region 578*150812a8SEvalZero 0 detected */ 579*150812a8SEvalZero } MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ 580*150812a8SEvalZero 581*150812a8SEvalZero 582*150812a8SEvalZero /** 583*150812a8SEvalZero * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Unspecified) 584*150812a8SEvalZero */ 585*150812a8SEvalZero typedef struct { 586*150812a8SEvalZero __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[0]: Write access to peripheral 587*150812a8SEvalZero region 0 detected */ 588*150812a8SEvalZero __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[0]: Read access to peripheral 589*150812a8SEvalZero region 0 detected */ 590*150812a8SEvalZero } MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ 591*150812a8SEvalZero 592*150812a8SEvalZero 593*150812a8SEvalZero /** 594*150812a8SEvalZero * @brief MWU_PERREGION [PERREGION] (Unspecified) 595*150812a8SEvalZero */ 596*150812a8SEvalZero typedef struct { 597*150812a8SEvalZero __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster[0]: Source of event/interrupt 598*150812a8SEvalZero in region 0, write access detected while 599*150812a8SEvalZero corresponding subregion was enabled for 600*150812a8SEvalZero watching */ 601*150812a8SEvalZero __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster[0]: Source of event/interrupt 602*150812a8SEvalZero in region 0, read access detected while 603*150812a8SEvalZero corresponding subregion was enabled for 604*150812a8SEvalZero watching */ 605*150812a8SEvalZero } MWU_PERREGION_Type; /*!< Size = 8 (0x8) */ 606*150812a8SEvalZero 607*150812a8SEvalZero 608*150812a8SEvalZero /** 609*150812a8SEvalZero * @brief MWU_REGION [REGION] (Unspecified) 610*150812a8SEvalZero */ 611*150812a8SEvalZero typedef struct { 612*150812a8SEvalZero __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster[0]: Start address for region 613*150812a8SEvalZero 0 */ 614*150812a8SEvalZero __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster[0]: End address of region 615*150812a8SEvalZero 0 */ 616*150812a8SEvalZero __IM uint32_t RESERVED[2]; 617*150812a8SEvalZero } MWU_REGION_Type; /*!< Size = 16 (0x10) */ 618*150812a8SEvalZero 619*150812a8SEvalZero 620*150812a8SEvalZero /** 621*150812a8SEvalZero * @brief MWU_PREGION [PREGION] (Unspecified) 622*150812a8SEvalZero */ 623*150812a8SEvalZero typedef struct { 624*150812a8SEvalZero __IM uint32_t START; /*!< (@ 0x00000000) Description cluster[0]: Reserved for future use */ 625*150812a8SEvalZero __IM uint32_t END; /*!< (@ 0x00000004) Description cluster[0]: Reserved for future use */ 626*150812a8SEvalZero __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster[0]: Subregions of region 627*150812a8SEvalZero 0 */ 628*150812a8SEvalZero __IM uint32_t RESERVED; 629*150812a8SEvalZero } MWU_PREGION_Type; /*!< Size = 16 (0x10) */ 630*150812a8SEvalZero 631*150812a8SEvalZero 632*150812a8SEvalZero /** 633*150812a8SEvalZero * @brief I2S_CONFIG [CONFIG] (Unspecified) 634*150812a8SEvalZero */ 635*150812a8SEvalZero typedef struct { 636*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ 637*150812a8SEvalZero __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ 638*150812a8SEvalZero __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ 639*150812a8SEvalZero __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ 640*150812a8SEvalZero __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ 641*150812a8SEvalZero __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ 642*150812a8SEvalZero __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ 643*150812a8SEvalZero __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ 644*150812a8SEvalZero __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ 645*150812a8SEvalZero __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ 646*150812a8SEvalZero } I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ 647*150812a8SEvalZero 648*150812a8SEvalZero 649*150812a8SEvalZero /** 650*150812a8SEvalZero * @brief I2S_RXD [RXD] (Unspecified) 651*150812a8SEvalZero */ 652*150812a8SEvalZero typedef struct { 653*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ 654*150812a8SEvalZero } I2S_RXD_Type; /*!< Size = 4 (0x4) */ 655*150812a8SEvalZero 656*150812a8SEvalZero 657*150812a8SEvalZero /** 658*150812a8SEvalZero * @brief I2S_TXD [TXD] (Unspecified) 659*150812a8SEvalZero */ 660*150812a8SEvalZero typedef struct { 661*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ 662*150812a8SEvalZero } I2S_TXD_Type; /*!< Size = 4 (0x4) */ 663*150812a8SEvalZero 664*150812a8SEvalZero 665*150812a8SEvalZero /** 666*150812a8SEvalZero * @brief I2S_RXTXD [RXTXD] (Unspecified) 667*150812a8SEvalZero */ 668*150812a8SEvalZero typedef struct { 669*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ 670*150812a8SEvalZero } I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ 671*150812a8SEvalZero 672*150812a8SEvalZero 673*150812a8SEvalZero /** 674*150812a8SEvalZero * @brief I2S_PSEL [PSEL] (Unspecified) 675*150812a8SEvalZero */ 676*150812a8SEvalZero typedef struct { 677*150812a8SEvalZero __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ 678*150812a8SEvalZero __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ 679*150812a8SEvalZero __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ 680*150812a8SEvalZero __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ 681*150812a8SEvalZero __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ 682*150812a8SEvalZero } I2S_PSEL_Type; /*!< Size = 20 (0x14) */ 683*150812a8SEvalZero 684*150812a8SEvalZero 685*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_clusters */ 686*150812a8SEvalZero 687*150812a8SEvalZero 688*150812a8SEvalZero /* =========================================================================================================================== */ 689*150812a8SEvalZero /* ================ Device Specific Peripheral Section ================ */ 690*150812a8SEvalZero /* =========================================================================================================================== */ 691*150812a8SEvalZero 692*150812a8SEvalZero 693*150812a8SEvalZero /** @addtogroup Device_Peripheral_peripherals 694*150812a8SEvalZero * @{ 695*150812a8SEvalZero */ 696*150812a8SEvalZero 697*150812a8SEvalZero 698*150812a8SEvalZero 699*150812a8SEvalZero /* =========================================================================================================================== */ 700*150812a8SEvalZero /* ================ FICR ================ */ 701*150812a8SEvalZero /* =========================================================================================================================== */ 702*150812a8SEvalZero 703*150812a8SEvalZero 704*150812a8SEvalZero /** 705*150812a8SEvalZero * @brief Factory Information Configuration Registers (FICR) 706*150812a8SEvalZero */ 707*150812a8SEvalZero 708*150812a8SEvalZero typedef struct { /*!< (@ 0x10000000) FICR Structure */ 709*150812a8SEvalZero __IM uint32_t RESERVED[4]; 710*150812a8SEvalZero __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ 711*150812a8SEvalZero __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ 712*150812a8SEvalZero __IM uint32_t RESERVED1[18]; 713*150812a8SEvalZero __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[0]: Device identifier */ 714*150812a8SEvalZero __IM uint32_t RESERVED2[6]; 715*150812a8SEvalZero __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[0]: Encryption Root, word 716*150812a8SEvalZero 0 */ 717*150812a8SEvalZero __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[0]: Identity Root, word 718*150812a8SEvalZero 0 */ 719*150812a8SEvalZero __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ 720*150812a8SEvalZero __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[0]: Device address 0 */ 721*150812a8SEvalZero __IM uint32_t RESERVED3[21]; 722*150812a8SEvalZero __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ 723*150812a8SEvalZero __IM uint32_t RESERVED4[185]; 724*150812a8SEvalZero __IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization 725*150812a8SEvalZero coefficients */ 726*150812a8SEvalZero __IM uint32_t RESERVED5[2]; 727*150812a8SEvalZero __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ 728*150812a8SEvalZero } NRF_FICR_Type; /*!< Size = 1120 (0x460) */ 729*150812a8SEvalZero 730*150812a8SEvalZero 731*150812a8SEvalZero 732*150812a8SEvalZero /* =========================================================================================================================== */ 733*150812a8SEvalZero /* ================ UICR ================ */ 734*150812a8SEvalZero /* =========================================================================================================================== */ 735*150812a8SEvalZero 736*150812a8SEvalZero 737*150812a8SEvalZero /** 738*150812a8SEvalZero * @brief User Information Configuration Registers (UICR) 739*150812a8SEvalZero */ 740*150812a8SEvalZero 741*150812a8SEvalZero typedef struct { /*!< (@ 0x10001000) UICR Structure */ 742*150812a8SEvalZero __IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */ 743*150812a8SEvalZero __IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */ 744*150812a8SEvalZero __IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */ 745*150812a8SEvalZero __IM uint32_t RESERVED; 746*150812a8SEvalZero __IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */ 747*150812a8SEvalZero __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[0]: Reserved for Nordic 748*150812a8SEvalZero firmware design */ 749*150812a8SEvalZero __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[0]: Reserved for Nordic 750*150812a8SEvalZero hardware design */ 751*150812a8SEvalZero __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[0]: Reserved for customer */ 752*150812a8SEvalZero __IM uint32_t RESERVED1[64]; 753*150812a8SEvalZero __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[0]: Mapping of the nRESET 754*150812a8SEvalZero function (see POWER chapter for details) */ 755*150812a8SEvalZero __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access Port protection */ 756*150812a8SEvalZero __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: 757*150812a8SEvalZero NFC antenna or GPIO */ 758*150812a8SEvalZero } NRF_UICR_Type; /*!< Size = 528 (0x210) */ 759*150812a8SEvalZero 760*150812a8SEvalZero 761*150812a8SEvalZero 762*150812a8SEvalZero /* =========================================================================================================================== */ 763*150812a8SEvalZero /* ================ BPROT ================ */ 764*150812a8SEvalZero /* =========================================================================================================================== */ 765*150812a8SEvalZero 766*150812a8SEvalZero 767*150812a8SEvalZero /** 768*150812a8SEvalZero * @brief Block Protect (BPROT) 769*150812a8SEvalZero */ 770*150812a8SEvalZero 771*150812a8SEvalZero typedef struct { /*!< (@ 0x40000000) BPROT Structure */ 772*150812a8SEvalZero __IM uint32_t RESERVED[384]; 773*150812a8SEvalZero __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */ 774*150812a8SEvalZero __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */ 775*150812a8SEvalZero __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug interface 776*150812a8SEvalZero mode */ 777*150812a8SEvalZero __IOM uint32_t UNUSED0; /*!< (@ 0x0000060C) Unspecified */ 778*150812a8SEvalZero __IOM uint32_t CONFIG2; /*!< (@ 0x00000610) Block protect configuration register 2 */ 779*150812a8SEvalZero __IOM uint32_t CONFIG3; /*!< (@ 0x00000614) Block protect configuration register 3 */ 780*150812a8SEvalZero } NRF_BPROT_Type; /*!< Size = 1560 (0x618) */ 781*150812a8SEvalZero 782*150812a8SEvalZero 783*150812a8SEvalZero 784*150812a8SEvalZero /* =========================================================================================================================== */ 785*150812a8SEvalZero /* ================ POWER ================ */ 786*150812a8SEvalZero /* =========================================================================================================================== */ 787*150812a8SEvalZero 788*150812a8SEvalZero 789*150812a8SEvalZero /** 790*150812a8SEvalZero * @brief Power control (POWER) 791*150812a8SEvalZero */ 792*150812a8SEvalZero 793*150812a8SEvalZero typedef struct { /*!< (@ 0x40000000) POWER Structure */ 794*150812a8SEvalZero __IM uint32_t RESERVED[30]; 795*150812a8SEvalZero __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ 796*150812a8SEvalZero __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ 797*150812a8SEvalZero __IM uint32_t RESERVED1[34]; 798*150812a8SEvalZero __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 799*150812a8SEvalZero __IM uint32_t RESERVED2[2]; 800*150812a8SEvalZero __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 801*150812a8SEvalZero __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 802*150812a8SEvalZero __IM uint32_t RESERVED3[122]; 803*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 804*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 805*150812a8SEvalZero __IM uint32_t RESERVED4[61]; 806*150812a8SEvalZero __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 807*150812a8SEvalZero __IM uint32_t RESERVED5[9]; 808*150812a8SEvalZero __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ 809*150812a8SEvalZero __IM uint32_t RESERVED6[53]; 810*150812a8SEvalZero __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 811*150812a8SEvalZero __IM uint32_t RESERVED7[3]; 812*150812a8SEvalZero __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure comparator configuration */ 813*150812a8SEvalZero __IM uint32_t RESERVED8[2]; 814*150812a8SEvalZero __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ 815*150812a8SEvalZero __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ 816*150812a8SEvalZero __IOM uint32_t RAMON; /*!< (@ 0x00000524) Deprecated register - RAM on/off register (this 817*150812a8SEvalZero register is retained) */ 818*150812a8SEvalZero __IM uint32_t RESERVED9[11]; 819*150812a8SEvalZero __IOM uint32_t RAMONB; /*!< (@ 0x00000554) Deprecated register - RAM on/off register (this 820*150812a8SEvalZero register is retained) */ 821*150812a8SEvalZero __IM uint32_t RESERVED10[8]; 822*150812a8SEvalZero __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DC/DC enable register */ 823*150812a8SEvalZero __IM uint32_t RESERVED11[225]; 824*150812a8SEvalZero __IOM POWER_RAM_Type RAM[8]; /*!< (@ 0x00000900) Unspecified */ 825*150812a8SEvalZero } NRF_POWER_Type; /*!< Size = 2432 (0x980) */ 826*150812a8SEvalZero 827*150812a8SEvalZero 828*150812a8SEvalZero 829*150812a8SEvalZero /* =========================================================================================================================== */ 830*150812a8SEvalZero /* ================ CLOCK ================ */ 831*150812a8SEvalZero /* =========================================================================================================================== */ 832*150812a8SEvalZero 833*150812a8SEvalZero 834*150812a8SEvalZero /** 835*150812a8SEvalZero * @brief Clock control (CLOCK) 836*150812a8SEvalZero */ 837*150812a8SEvalZero 838*150812a8SEvalZero typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 839*150812a8SEvalZero __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */ 840*150812a8SEvalZero __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */ 841*150812a8SEvalZero __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ 842*150812a8SEvalZero __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 843*150812a8SEvalZero __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ 844*150812a8SEvalZero __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ 845*150812a8SEvalZero __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ 846*150812a8SEvalZero __IM uint32_t RESERVED[57]; 847*150812a8SEvalZero __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ 848*150812a8SEvalZero __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 849*150812a8SEvalZero __IM uint32_t RESERVED1; 850*150812a8SEvalZero __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */ 851*150812a8SEvalZero __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ 852*150812a8SEvalZero __IM uint32_t RESERVED2[124]; 853*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 854*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 855*150812a8SEvalZero __IM uint32_t RESERVED3[63]; 856*150812a8SEvalZero __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 857*150812a8SEvalZero triggered */ 858*150812a8SEvalZero __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ 859*150812a8SEvalZero __IM uint32_t RESERVED4; 860*150812a8SEvalZero __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 861*150812a8SEvalZero triggered */ 862*150812a8SEvalZero __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ 863*150812a8SEvalZero __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 864*150812a8SEvalZero task was triggered */ 865*150812a8SEvalZero __IM uint32_t RESERVED5[62]; 866*150812a8SEvalZero __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ 867*150812a8SEvalZero __IM uint32_t RESERVED6[7]; 868*150812a8SEvalZero __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ 869*150812a8SEvalZero __IM uint32_t RESERVED7[8]; 870*150812a8SEvalZero __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the Trace Port debug interface */ 871*150812a8SEvalZero } NRF_CLOCK_Type; /*!< Size = 1376 (0x560) */ 872*150812a8SEvalZero 873*150812a8SEvalZero 874*150812a8SEvalZero 875*150812a8SEvalZero /* =========================================================================================================================== */ 876*150812a8SEvalZero /* ================ RADIO ================ */ 877*150812a8SEvalZero /* =========================================================================================================================== */ 878*150812a8SEvalZero 879*150812a8SEvalZero 880*150812a8SEvalZero /** 881*150812a8SEvalZero * @brief 2.4 GHz Radio (RADIO) 882*150812a8SEvalZero */ 883*150812a8SEvalZero 884*150812a8SEvalZero typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 885*150812a8SEvalZero __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 886*150812a8SEvalZero __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 887*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 888*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 889*150812a8SEvalZero __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 890*150812a8SEvalZero __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 891*150812a8SEvalZero the receive signal strength. */ 892*150812a8SEvalZero __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 893*150812a8SEvalZero __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 894*150812a8SEvalZero __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 895*150812a8SEvalZero __IM uint32_t RESERVED[55]; 896*150812a8SEvalZero __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 897*150812a8SEvalZero __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 898*150812a8SEvalZero __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 899*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 900*150812a8SEvalZero __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 901*150812a8SEvalZero __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 902*150812a8SEvalZero packet */ 903*150812a8SEvalZero __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 904*150812a8SEvalZero received packet */ 905*150812a8SEvalZero __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete. */ 906*150812a8SEvalZero __IM uint32_t RESERVED1[2]; 907*150812a8SEvalZero __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value. */ 908*150812a8SEvalZero __IM uint32_t RESERVED2; 909*150812a8SEvalZero __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 910*150812a8SEvalZero __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 911*150812a8SEvalZero __IM uint32_t RESERVED3[50]; 912*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 913*150812a8SEvalZero __IM uint32_t RESERVED4[64]; 914*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 915*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 916*150812a8SEvalZero __IM uint32_t RESERVED5[61]; 917*150812a8SEvalZero __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 918*150812a8SEvalZero __IM uint32_t RESERVED6; 919*150812a8SEvalZero __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 920*150812a8SEvalZero __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 921*150812a8SEvalZero __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 922*150812a8SEvalZero __IM uint32_t RESERVED7[60]; 923*150812a8SEvalZero __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 924*150812a8SEvalZero __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 925*150812a8SEvalZero __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 926*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 927*150812a8SEvalZero __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 928*150812a8SEvalZero __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 929*150812a8SEvalZero __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 930*150812a8SEvalZero __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 931*150812a8SEvalZero __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 932*150812a8SEvalZero __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 933*150812a8SEvalZero __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 934*150812a8SEvalZero __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 935*150812a8SEvalZero __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 936*150812a8SEvalZero __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 937*150812a8SEvalZero __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 938*150812a8SEvalZero __IOM uint32_t UNUSED0; /*!< (@ 0x00000540) Unspecified */ 939*150812a8SEvalZero __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in us */ 940*150812a8SEvalZero __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 941*150812a8SEvalZero __IM uint32_t RESERVED8; 942*150812a8SEvalZero __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 943*150812a8SEvalZero __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 944*150812a8SEvalZero __IM uint32_t RESERVED9[2]; 945*150812a8SEvalZero __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 946*150812a8SEvalZero __IM uint32_t RESERVED10[39]; 947*150812a8SEvalZero __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[0]: Device address base 948*150812a8SEvalZero segment 0 */ 949*150812a8SEvalZero __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[0]: Device address prefix 950*150812a8SEvalZero 0 */ 951*150812a8SEvalZero __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 952*150812a8SEvalZero __IM uint32_t RESERVED11[3]; 953*150812a8SEvalZero __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 954*150812a8SEvalZero __IM uint32_t RESERVED12[618]; 955*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 956*150812a8SEvalZero } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 957*150812a8SEvalZero 958*150812a8SEvalZero 959*150812a8SEvalZero 960*150812a8SEvalZero /* =========================================================================================================================== */ 961*150812a8SEvalZero /* ================ UARTE0 ================ */ 962*150812a8SEvalZero /* =========================================================================================================================== */ 963*150812a8SEvalZero 964*150812a8SEvalZero 965*150812a8SEvalZero /** 966*150812a8SEvalZero * @brief UART with EasyDMA (UARTE0) 967*150812a8SEvalZero */ 968*150812a8SEvalZero 969*150812a8SEvalZero typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ 970*150812a8SEvalZero __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 971*150812a8SEvalZero __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 972*150812a8SEvalZero __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 973*150812a8SEvalZero __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 974*150812a8SEvalZero __IM uint32_t RESERVED[7]; 975*150812a8SEvalZero __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 976*150812a8SEvalZero __IM uint32_t RESERVED1[52]; 977*150812a8SEvalZero __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 978*150812a8SEvalZero __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 979*150812a8SEvalZero __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 980*150812a8SEvalZero transferred to Data RAM) */ 981*150812a8SEvalZero __IM uint32_t RESERVED2; 982*150812a8SEvalZero __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 983*150812a8SEvalZero __IM uint32_t RESERVED3[2]; 984*150812a8SEvalZero __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 985*150812a8SEvalZero __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 986*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 987*150812a8SEvalZero __IM uint32_t RESERVED4[7]; 988*150812a8SEvalZero __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 989*150812a8SEvalZero __IM uint32_t RESERVED5; 990*150812a8SEvalZero __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 991*150812a8SEvalZero __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 992*150812a8SEvalZero __IM uint32_t RESERVED6; 993*150812a8SEvalZero __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 994*150812a8SEvalZero __IM uint32_t RESERVED7[41]; 995*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 996*150812a8SEvalZero __IM uint32_t RESERVED8[63]; 997*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 998*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 999*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1000*150812a8SEvalZero __IM uint32_t RESERVED9[93]; 1001*150812a8SEvalZero __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 1002*150812a8SEvalZero __IM uint32_t RESERVED10[31]; 1003*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1004*150812a8SEvalZero __IM uint32_t RESERVED11; 1005*150812a8SEvalZero __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1006*150812a8SEvalZero __IM uint32_t RESERVED12[3]; 1007*150812a8SEvalZero __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1008*150812a8SEvalZero selected. */ 1009*150812a8SEvalZero __IM uint32_t RESERVED13[3]; 1010*150812a8SEvalZero __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1011*150812a8SEvalZero __IM uint32_t RESERVED14; 1012*150812a8SEvalZero __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1013*150812a8SEvalZero __IM uint32_t RESERVED15[7]; 1014*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1015*150812a8SEvalZero } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1016*150812a8SEvalZero 1017*150812a8SEvalZero 1018*150812a8SEvalZero 1019*150812a8SEvalZero /* =========================================================================================================================== */ 1020*150812a8SEvalZero /* ================ UART0 ================ */ 1021*150812a8SEvalZero /* =========================================================================================================================== */ 1022*150812a8SEvalZero 1023*150812a8SEvalZero 1024*150812a8SEvalZero /** 1025*150812a8SEvalZero * @brief Universal Asynchronous Receiver/Transmitter (UART0) 1026*150812a8SEvalZero */ 1027*150812a8SEvalZero 1028*150812a8SEvalZero typedef struct { /*!< (@ 0x40002000) UART0 Structure */ 1029*150812a8SEvalZero __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1030*150812a8SEvalZero __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1031*150812a8SEvalZero __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1032*150812a8SEvalZero __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1033*150812a8SEvalZero __IM uint32_t RESERVED[3]; 1034*150812a8SEvalZero __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ 1035*150812a8SEvalZero __IM uint32_t RESERVED1[56]; 1036*150812a8SEvalZero __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1037*150812a8SEvalZero __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1038*150812a8SEvalZero __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ 1039*150812a8SEvalZero __IM uint32_t RESERVED2[4]; 1040*150812a8SEvalZero __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1041*150812a8SEvalZero __IM uint32_t RESERVED3; 1042*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1043*150812a8SEvalZero __IM uint32_t RESERVED4[7]; 1044*150812a8SEvalZero __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1045*150812a8SEvalZero __IM uint32_t RESERVED5[46]; 1046*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1047*150812a8SEvalZero __IM uint32_t RESERVED6[64]; 1048*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1049*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1050*150812a8SEvalZero __IM uint32_t RESERVED7[93]; 1051*150812a8SEvalZero __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 1052*150812a8SEvalZero __IM uint32_t RESERVED8[31]; 1053*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1054*150812a8SEvalZero __IM uint32_t RESERVED9; 1055*150812a8SEvalZero __IOM uint32_t PSELRTS; /*!< (@ 0x00000508) Pin select for RTS */ 1056*150812a8SEvalZero __IOM uint32_t PSELTXD; /*!< (@ 0x0000050C) Pin select for TXD */ 1057*150812a8SEvalZero __IOM uint32_t PSELCTS; /*!< (@ 0x00000510) Pin select for CTS */ 1058*150812a8SEvalZero __IOM uint32_t PSELRXD; /*!< (@ 0x00000514) Pin select for RXD */ 1059*150812a8SEvalZero __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1060*150812a8SEvalZero __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1061*150812a8SEvalZero __IM uint32_t RESERVED10; 1062*150812a8SEvalZero __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate */ 1063*150812a8SEvalZero __IM uint32_t RESERVED11[17]; 1064*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1065*150812a8SEvalZero } NRF_UART_Type; /*!< Size = 1392 (0x570) */ 1066*150812a8SEvalZero 1067*150812a8SEvalZero 1068*150812a8SEvalZero 1069*150812a8SEvalZero /* =========================================================================================================================== */ 1070*150812a8SEvalZero /* ================ SPIM0 ================ */ 1071*150812a8SEvalZero /* =========================================================================================================================== */ 1072*150812a8SEvalZero 1073*150812a8SEvalZero 1074*150812a8SEvalZero /** 1075*150812a8SEvalZero * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) 1076*150812a8SEvalZero */ 1077*150812a8SEvalZero 1078*150812a8SEvalZero typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ 1079*150812a8SEvalZero __IM uint32_t RESERVED[4]; 1080*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1081*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1082*150812a8SEvalZero __IM uint32_t RESERVED1; 1083*150812a8SEvalZero __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1084*150812a8SEvalZero __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1085*150812a8SEvalZero __IM uint32_t RESERVED2[56]; 1086*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1087*150812a8SEvalZero __IM uint32_t RESERVED3[2]; 1088*150812a8SEvalZero __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1089*150812a8SEvalZero __IM uint32_t RESERVED4; 1090*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1091*150812a8SEvalZero __IM uint32_t RESERVED5; 1092*150812a8SEvalZero __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1093*150812a8SEvalZero __IM uint32_t RESERVED6[10]; 1094*150812a8SEvalZero __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1095*150812a8SEvalZero __IM uint32_t RESERVED7[44]; 1096*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1097*150812a8SEvalZero __IM uint32_t RESERVED8[64]; 1098*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1099*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1100*150812a8SEvalZero __IM uint32_t RESERVED9[125]; 1101*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1102*150812a8SEvalZero __IM uint32_t RESERVED10; 1103*150812a8SEvalZero __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1104*150812a8SEvalZero __IM uint32_t RESERVED11[4]; 1105*150812a8SEvalZero __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1106*150812a8SEvalZero source selected. */ 1107*150812a8SEvalZero __IM uint32_t RESERVED12[3]; 1108*150812a8SEvalZero __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1109*150812a8SEvalZero __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1110*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1111*150812a8SEvalZero __IM uint32_t RESERVED13[26]; 1112*150812a8SEvalZero __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in 1113*150812a8SEvalZero case and over-read of the TXD buffer. */ 1114*150812a8SEvalZero } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1115*150812a8SEvalZero 1116*150812a8SEvalZero 1117*150812a8SEvalZero 1118*150812a8SEvalZero /* =========================================================================================================================== */ 1119*150812a8SEvalZero /* ================ SPIS0 ================ */ 1120*150812a8SEvalZero /* =========================================================================================================================== */ 1121*150812a8SEvalZero 1122*150812a8SEvalZero 1123*150812a8SEvalZero /** 1124*150812a8SEvalZero * @brief SPI Slave 0 (SPIS0) 1125*150812a8SEvalZero */ 1126*150812a8SEvalZero 1127*150812a8SEvalZero typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ 1128*150812a8SEvalZero __IM uint32_t RESERVED[9]; 1129*150812a8SEvalZero __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1130*150812a8SEvalZero __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1131*150812a8SEvalZero to acquire it */ 1132*150812a8SEvalZero __IM uint32_t RESERVED1[54]; 1133*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1134*150812a8SEvalZero __IM uint32_t RESERVED2[2]; 1135*150812a8SEvalZero __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1136*150812a8SEvalZero __IM uint32_t RESERVED3[5]; 1137*150812a8SEvalZero __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1138*150812a8SEvalZero __IM uint32_t RESERVED4[53]; 1139*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1140*150812a8SEvalZero __IM uint32_t RESERVED5[64]; 1141*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1142*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1143*150812a8SEvalZero __IM uint32_t RESERVED6[61]; 1144*150812a8SEvalZero __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1145*150812a8SEvalZero __IM uint32_t RESERVED7[15]; 1146*150812a8SEvalZero __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1147*150812a8SEvalZero __IM uint32_t RESERVED8[47]; 1148*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1149*150812a8SEvalZero __IM uint32_t RESERVED9; 1150*150812a8SEvalZero __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1151*150812a8SEvalZero __IM uint32_t RESERVED10[7]; 1152*150812a8SEvalZero __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1153*150812a8SEvalZero __IM uint32_t RESERVED11; 1154*150812a8SEvalZero __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1155*150812a8SEvalZero __IM uint32_t RESERVED12; 1156*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1157*150812a8SEvalZero __IM uint32_t RESERVED13; 1158*150812a8SEvalZero __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1159*150812a8SEvalZero of an ignored transaction. */ 1160*150812a8SEvalZero __IM uint32_t RESERVED14[24]; 1161*150812a8SEvalZero __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1162*150812a8SEvalZero } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1163*150812a8SEvalZero 1164*150812a8SEvalZero 1165*150812a8SEvalZero 1166*150812a8SEvalZero /* =========================================================================================================================== */ 1167*150812a8SEvalZero /* ================ TWIM0 ================ */ 1168*150812a8SEvalZero /* =========================================================================================================================== */ 1169*150812a8SEvalZero 1170*150812a8SEvalZero 1171*150812a8SEvalZero /** 1172*150812a8SEvalZero * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) 1173*150812a8SEvalZero */ 1174*150812a8SEvalZero 1175*150812a8SEvalZero typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ 1176*150812a8SEvalZero __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1177*150812a8SEvalZero __IM uint32_t RESERVED; 1178*150812a8SEvalZero __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1179*150812a8SEvalZero __IM uint32_t RESERVED1[2]; 1180*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1181*150812a8SEvalZero TWI master is not suspended. */ 1182*150812a8SEvalZero __IM uint32_t RESERVED2; 1183*150812a8SEvalZero __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1184*150812a8SEvalZero __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1185*150812a8SEvalZero __IM uint32_t RESERVED3[56]; 1186*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1187*150812a8SEvalZero __IM uint32_t RESERVED4[7]; 1188*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1189*150812a8SEvalZero __IM uint32_t RESERVED5[8]; 1190*150812a8SEvalZero __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND 1191*150812a8SEvalZero task has been issued, TWI traffic is now 1192*150812a8SEvalZero suspended. */ 1193*150812a8SEvalZero __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1194*150812a8SEvalZero __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1195*150812a8SEvalZero __IM uint32_t RESERVED6[2]; 1196*150812a8SEvalZero __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1197*150812a8SEvalZero __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1198*150812a8SEvalZero byte */ 1199*150812a8SEvalZero __IM uint32_t RESERVED7[39]; 1200*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1201*150812a8SEvalZero __IM uint32_t RESERVED8[63]; 1202*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1203*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1204*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1205*150812a8SEvalZero __IM uint32_t RESERVED9[110]; 1206*150812a8SEvalZero __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1207*150812a8SEvalZero __IM uint32_t RESERVED10[14]; 1208*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1209*150812a8SEvalZero __IM uint32_t RESERVED11; 1210*150812a8SEvalZero __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1211*150812a8SEvalZero __IM uint32_t RESERVED12[5]; 1212*150812a8SEvalZero __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */ 1213*150812a8SEvalZero __IM uint32_t RESERVED13[3]; 1214*150812a8SEvalZero __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1215*150812a8SEvalZero __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1216*150812a8SEvalZero __IM uint32_t RESERVED14[13]; 1217*150812a8SEvalZero __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1218*150812a8SEvalZero } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1219*150812a8SEvalZero 1220*150812a8SEvalZero 1221*150812a8SEvalZero 1222*150812a8SEvalZero /* =========================================================================================================================== */ 1223*150812a8SEvalZero /* ================ TWIS0 ================ */ 1224*150812a8SEvalZero /* =========================================================================================================================== */ 1225*150812a8SEvalZero 1226*150812a8SEvalZero 1227*150812a8SEvalZero /** 1228*150812a8SEvalZero * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) 1229*150812a8SEvalZero */ 1230*150812a8SEvalZero 1231*150812a8SEvalZero typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ 1232*150812a8SEvalZero __IM uint32_t RESERVED[5]; 1233*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1234*150812a8SEvalZero __IM uint32_t RESERVED1; 1235*150812a8SEvalZero __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1236*150812a8SEvalZero __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1237*150812a8SEvalZero __IM uint32_t RESERVED2[3]; 1238*150812a8SEvalZero __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1239*150812a8SEvalZero __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1240*150812a8SEvalZero __IM uint32_t RESERVED3[51]; 1241*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1242*150812a8SEvalZero __IM uint32_t RESERVED4[7]; 1243*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1244*150812a8SEvalZero __IM uint32_t RESERVED5[9]; 1245*150812a8SEvalZero __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1246*150812a8SEvalZero __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1247*150812a8SEvalZero __IM uint32_t RESERVED6[4]; 1248*150812a8SEvalZero __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1249*150812a8SEvalZero __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1250*150812a8SEvalZero __IM uint32_t RESERVED7[37]; 1251*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1252*150812a8SEvalZero __IM uint32_t RESERVED8[63]; 1253*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1254*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1255*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1256*150812a8SEvalZero __IM uint32_t RESERVED9[113]; 1257*150812a8SEvalZero __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1258*150812a8SEvalZero __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1259*150812a8SEvalZero a match */ 1260*150812a8SEvalZero __IM uint32_t RESERVED10[10]; 1261*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1262*150812a8SEvalZero __IM uint32_t RESERVED11; 1263*150812a8SEvalZero __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1264*150812a8SEvalZero __IM uint32_t RESERVED12[9]; 1265*150812a8SEvalZero __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1266*150812a8SEvalZero __IM uint32_t RESERVED13; 1267*150812a8SEvalZero __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1268*150812a8SEvalZero __IM uint32_t RESERVED14[14]; 1269*150812a8SEvalZero __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[0]: TWI slave address 1270*150812a8SEvalZero 0 */ 1271*150812a8SEvalZero __IM uint32_t RESERVED15; 1272*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1273*150812a8SEvalZero mechanism */ 1274*150812a8SEvalZero __IM uint32_t RESERVED16[10]; 1275*150812a8SEvalZero __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1276*150812a8SEvalZero of an over-read of the transmit buffer. */ 1277*150812a8SEvalZero } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1278*150812a8SEvalZero 1279*150812a8SEvalZero 1280*150812a8SEvalZero 1281*150812a8SEvalZero /* =========================================================================================================================== */ 1282*150812a8SEvalZero /* ================ SPI0 ================ */ 1283*150812a8SEvalZero /* =========================================================================================================================== */ 1284*150812a8SEvalZero 1285*150812a8SEvalZero 1286*150812a8SEvalZero /** 1287*150812a8SEvalZero * @brief Serial Peripheral Interface 0 (SPI0) 1288*150812a8SEvalZero */ 1289*150812a8SEvalZero 1290*150812a8SEvalZero typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ 1291*150812a8SEvalZero __IM uint32_t RESERVED[66]; 1292*150812a8SEvalZero __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ 1293*150812a8SEvalZero __IM uint32_t RESERVED1[126]; 1294*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1295*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1296*150812a8SEvalZero __IM uint32_t RESERVED2[125]; 1297*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ 1298*150812a8SEvalZero __IM uint32_t RESERVED3; 1299*150812a8SEvalZero __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1300*150812a8SEvalZero __IM uint32_t RESERVED4; 1301*150812a8SEvalZero __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1302*150812a8SEvalZero __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1303*150812a8SEvalZero __IM uint32_t RESERVED5; 1304*150812a8SEvalZero __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency */ 1305*150812a8SEvalZero __IM uint32_t RESERVED6[11]; 1306*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1307*150812a8SEvalZero } NRF_SPI_Type; /*!< Size = 1368 (0x558) */ 1308*150812a8SEvalZero 1309*150812a8SEvalZero 1310*150812a8SEvalZero 1311*150812a8SEvalZero /* =========================================================================================================================== */ 1312*150812a8SEvalZero /* ================ TWI0 ================ */ 1313*150812a8SEvalZero /* =========================================================================================================================== */ 1314*150812a8SEvalZero 1315*150812a8SEvalZero 1316*150812a8SEvalZero /** 1317*150812a8SEvalZero * @brief I2C compatible Two-Wire Interface 0 (TWI0) 1318*150812a8SEvalZero */ 1319*150812a8SEvalZero 1320*150812a8SEvalZero typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ 1321*150812a8SEvalZero __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1322*150812a8SEvalZero __IM uint32_t RESERVED; 1323*150812a8SEvalZero __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1324*150812a8SEvalZero __IM uint32_t RESERVED1[2]; 1325*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1326*150812a8SEvalZero __IM uint32_t RESERVED2; 1327*150812a8SEvalZero __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1328*150812a8SEvalZero __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1329*150812a8SEvalZero __IM uint32_t RESERVED3[56]; 1330*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1331*150812a8SEvalZero __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ 1332*150812a8SEvalZero __IM uint32_t RESERVED4[4]; 1333*150812a8SEvalZero __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ 1334*150812a8SEvalZero __IM uint32_t RESERVED5; 1335*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1336*150812a8SEvalZero __IM uint32_t RESERVED6[4]; 1337*150812a8SEvalZero __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte 1338*150812a8SEvalZero that is sent or received */ 1339*150812a8SEvalZero __IM uint32_t RESERVED7[3]; 1340*150812a8SEvalZero __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ 1341*150812a8SEvalZero __IM uint32_t RESERVED8[45]; 1342*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1343*150812a8SEvalZero __IM uint32_t RESERVED9[64]; 1344*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1345*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1346*150812a8SEvalZero __IM uint32_t RESERVED10[110]; 1347*150812a8SEvalZero __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1348*150812a8SEvalZero __IM uint32_t RESERVED11[14]; 1349*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ 1350*150812a8SEvalZero __IM uint32_t RESERVED12; 1351*150812a8SEvalZero __IOM uint32_t PSELSCL; /*!< (@ 0x00000508) Pin select for SCL */ 1352*150812a8SEvalZero __IOM uint32_t PSELSDA; /*!< (@ 0x0000050C) Pin select for SDA */ 1353*150812a8SEvalZero __IM uint32_t RESERVED13[2]; 1354*150812a8SEvalZero __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1355*150812a8SEvalZero __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1356*150812a8SEvalZero __IM uint32_t RESERVED14; 1357*150812a8SEvalZero __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */ 1358*150812a8SEvalZero __IM uint32_t RESERVED15[24]; 1359*150812a8SEvalZero __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1360*150812a8SEvalZero } NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ 1361*150812a8SEvalZero 1362*150812a8SEvalZero 1363*150812a8SEvalZero 1364*150812a8SEvalZero /* =========================================================================================================================== */ 1365*150812a8SEvalZero /* ================ NFCT ================ */ 1366*150812a8SEvalZero /* =========================================================================================================================== */ 1367*150812a8SEvalZero 1368*150812a8SEvalZero 1369*150812a8SEvalZero /** 1370*150812a8SEvalZero * @brief NFC-A compatible radio (NFCT) 1371*150812a8SEvalZero */ 1372*150812a8SEvalZero 1373*150812a8SEvalZero typedef struct { /*!< (@ 0x40005000) NFCT Structure */ 1374*150812a8SEvalZero __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFC peripheral for incoming and outgoing 1375*150812a8SEvalZero frames, change state to activated */ 1376*150812a8SEvalZero __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFC peripheral */ 1377*150812a8SEvalZero __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to 1378*150812a8SEvalZero sense mode */ 1379*150812a8SEvalZero __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of a outgoing frame, change 1380*150812a8SEvalZero state to transmit */ 1381*150812a8SEvalZero __IM uint32_t RESERVED[3]; 1382*150812a8SEvalZero __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ 1383*150812a8SEvalZero __IM uint32_t RESERVED1; 1384*150812a8SEvalZero __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ 1385*150812a8SEvalZero __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ 1386*150812a8SEvalZero __IM uint32_t RESERVED2[53]; 1387*150812a8SEvalZero __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFC peripheral is ready to receive and send 1388*150812a8SEvalZero frames */ 1389*150812a8SEvalZero __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ 1390*150812a8SEvalZero __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ 1391*150812a8SEvalZero __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted 1392*150812a8SEvalZero frame */ 1393*150812a8SEvalZero __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air 1394*150812a8SEvalZero symbol of a frame */ 1395*150812a8SEvalZero __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received 1396*150812a8SEvalZero frame */ 1397*150812a8SEvalZero __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data have been checked (CRC, parity) 1398*150812a8SEvalZero and transferred to RAM, and EasyDMA has 1399*150812a8SEvalZero ended accessing the RX buffer */ 1400*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register 1401*150812a8SEvalZero contains details on the source of the error. */ 1402*150812a8SEvalZero __IM uint32_t RESERVED3[2]; 1403*150812a8SEvalZero __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX 1404*150812a8SEvalZero register contains details on the source 1405*150812a8SEvalZero of the error. */ 1406*150812a8SEvalZero __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) 1407*150812a8SEvalZero in Data RAM full. */ 1408*150812a8SEvalZero __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA 1409*150812a8SEvalZero has ended accessing the TX buffer */ 1410*150812a8SEvalZero __IM uint32_t RESERVED4; 1411*150812a8SEvalZero __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ 1412*150812a8SEvalZero __IM uint32_t RESERVED5[3]; 1413*150812a8SEvalZero __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC Auto collision resolution error reported. */ 1414*150812a8SEvalZero __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC Auto collision resolution successfully completed */ 1415*150812a8SEvalZero __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ 1416*150812a8SEvalZero __IM uint32_t RESERVED6[43]; 1417*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1418*150812a8SEvalZero __IM uint32_t RESERVED7[63]; 1419*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1420*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1421*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1422*150812a8SEvalZero __IM uint32_t RESERVED8[62]; 1423*150812a8SEvalZero __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ 1424*150812a8SEvalZero __IM uint32_t RESERVED9; 1425*150812a8SEvalZero __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ 1426*150812a8SEvalZero __IM uint32_t RESERVED10[8]; 1427*150812a8SEvalZero __IM uint32_t CURRENTLOADCTRL; /*!< (@ 0x00000430) Current value driven to the NFC Load Control */ 1428*150812a8SEvalZero __IM uint32_t RESERVED11[2]; 1429*150812a8SEvalZero __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ 1430*150812a8SEvalZero __IM uint32_t RESERVED12[49]; 1431*150812a8SEvalZero __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ 1432*150812a8SEvalZero __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ 1433*150812a8SEvalZero __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ 1434*150812a8SEvalZero __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in 1435*150812a8SEvalZero Data RAM */ 1436*150812a8SEvalZero __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of allocated for TXD and RXD data storage 1437*150812a8SEvalZero buffer in Data RAM */ 1438*150812a8SEvalZero __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ 1439*150812a8SEvalZero __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ 1440*150812a8SEvalZero __IM uint32_t RESERVED13[26]; 1441*150812a8SEvalZero __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ 1442*150812a8SEvalZero __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ 1443*150812a8SEvalZero __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ 1444*150812a8SEvalZero __IM uint32_t RESERVED14; 1445*150812a8SEvalZero __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ 1446*150812a8SEvalZero __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ 1447*150812a8SEvalZero } NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ 1448*150812a8SEvalZero 1449*150812a8SEvalZero 1450*150812a8SEvalZero 1451*150812a8SEvalZero /* =========================================================================================================================== */ 1452*150812a8SEvalZero /* ================ GPIOTE ================ */ 1453*150812a8SEvalZero /* =========================================================================================================================== */ 1454*150812a8SEvalZero 1455*150812a8SEvalZero 1456*150812a8SEvalZero /** 1457*150812a8SEvalZero * @brief GPIO Tasks and Events (GPIOTE) 1458*150812a8SEvalZero */ 1459*150812a8SEvalZero 1460*150812a8SEvalZero typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 1461*150812a8SEvalZero __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[0]: Task for writing to 1462*150812a8SEvalZero pin specified in CONFIG[0].PSEL. Action 1463*150812a8SEvalZero on pin is configured in CONFIG[0].POLARITY. */ 1464*150812a8SEvalZero __IM uint32_t RESERVED[4]; 1465*150812a8SEvalZero __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[0]: Task for writing to 1466*150812a8SEvalZero pin specified in CONFIG[0].PSEL. Action 1467*150812a8SEvalZero on pin is to set it high. */ 1468*150812a8SEvalZero __IM uint32_t RESERVED1[4]; 1469*150812a8SEvalZero __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[0]: Task for writing to 1470*150812a8SEvalZero pin specified in CONFIG[0].PSEL. Action 1471*150812a8SEvalZero on pin is to set it low. */ 1472*150812a8SEvalZero __IM uint32_t RESERVED2[32]; 1473*150812a8SEvalZero __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[0]: Event generated from 1474*150812a8SEvalZero pin specified in CONFIG[0].PSEL */ 1475*150812a8SEvalZero __IM uint32_t RESERVED3[23]; 1476*150812a8SEvalZero __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1477*150812a8SEvalZero with SENSE mechanism enabled */ 1478*150812a8SEvalZero __IM uint32_t RESERVED4[97]; 1479*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1480*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1481*150812a8SEvalZero __IM uint32_t RESERVED5[129]; 1482*150812a8SEvalZero __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[0]: Configuration for 1483*150812a8SEvalZero OUT[n], SET[n] and CLR[n] tasks and IN[n] 1484*150812a8SEvalZero event */ 1485*150812a8SEvalZero } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1486*150812a8SEvalZero 1487*150812a8SEvalZero 1488*150812a8SEvalZero 1489*150812a8SEvalZero /* =========================================================================================================================== */ 1490*150812a8SEvalZero /* ================ SAADC ================ */ 1491*150812a8SEvalZero /* =========================================================================================================================== */ 1492*150812a8SEvalZero 1493*150812a8SEvalZero 1494*150812a8SEvalZero /** 1495*150812a8SEvalZero * @brief Analog to Digital Converter (SAADC) 1496*150812a8SEvalZero */ 1497*150812a8SEvalZero 1498*150812a8SEvalZero typedef struct { /*!< (@ 0x40007000) SAADC Structure */ 1499*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in 1500*150812a8SEvalZero RAM */ 1501*150812a8SEvalZero __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels 1502*150812a8SEvalZero are sampled */ 1503*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ 1504*150812a8SEvalZero __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1505*150812a8SEvalZero __IM uint32_t RESERVED[60]; 1506*150812a8SEvalZero __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ 1507*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ 1508*150812a8SEvalZero __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1509*150812a8SEvalZero on the mode, multiple conversions might 1510*150812a8SEvalZero be needed for a result to be transferred 1511*150812a8SEvalZero to RAM. */ 1512*150812a8SEvalZero __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ 1513*150812a8SEvalZero __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1514*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ 1515*150812a8SEvalZero __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */ 1516*150812a8SEvalZero __IM uint32_t RESERVED1[106]; 1517*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1518*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1519*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1520*150812a8SEvalZero __IM uint32_t RESERVED2[61]; 1521*150812a8SEvalZero __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1522*150812a8SEvalZero __IM uint32_t RESERVED3[63]; 1523*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ 1524*150812a8SEvalZero __IM uint32_t RESERVED4[3]; 1525*150812a8SEvalZero __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1526*150812a8SEvalZero __IM uint32_t RESERVED5[24]; 1527*150812a8SEvalZero __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1528*150812a8SEvalZero __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should 1529*150812a8SEvalZero not be combined with SCAN. The RESOLUTION 1530*150812a8SEvalZero is applied before averaging, thus for high 1531*150812a8SEvalZero OVERSAMPLE a higher RESOLUTION should be 1532*150812a8SEvalZero used. */ 1533*150812a8SEvalZero __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1534*150812a8SEvalZero __IM uint32_t RESERVED6[12]; 1535*150812a8SEvalZero __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1536*150812a8SEvalZero } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1537*150812a8SEvalZero 1538*150812a8SEvalZero 1539*150812a8SEvalZero 1540*150812a8SEvalZero /* =========================================================================================================================== */ 1541*150812a8SEvalZero /* ================ TIMER0 ================ */ 1542*150812a8SEvalZero /* =========================================================================================================================== */ 1543*150812a8SEvalZero 1544*150812a8SEvalZero 1545*150812a8SEvalZero /** 1546*150812a8SEvalZero * @brief Timer/Counter 0 (TIMER0) 1547*150812a8SEvalZero */ 1548*150812a8SEvalZero 1549*150812a8SEvalZero typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 1550*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1551*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1552*150812a8SEvalZero __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1553*150812a8SEvalZero __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1554*150812a8SEvalZero __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1555*150812a8SEvalZero __IM uint32_t RESERVED[11]; 1556*150812a8SEvalZero __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[0]: Capture Timer value 1557*150812a8SEvalZero to CC[0] register */ 1558*150812a8SEvalZero __IM uint32_t RESERVED1[58]; 1559*150812a8SEvalZero __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[0]: Compare event on CC[0] 1560*150812a8SEvalZero match */ 1561*150812a8SEvalZero __IM uint32_t RESERVED2[42]; 1562*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1563*150812a8SEvalZero __IM uint32_t RESERVED3[64]; 1564*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1565*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1566*150812a8SEvalZero __IM uint32_t RESERVED4[126]; 1567*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1568*150812a8SEvalZero __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1569*150812a8SEvalZero __IM uint32_t RESERVED5; 1570*150812a8SEvalZero __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1571*150812a8SEvalZero __IM uint32_t RESERVED6[11]; 1572*150812a8SEvalZero __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[0]: Capture/Compare register 1573*150812a8SEvalZero 0 */ 1574*150812a8SEvalZero } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1575*150812a8SEvalZero 1576*150812a8SEvalZero 1577*150812a8SEvalZero 1578*150812a8SEvalZero /* =========================================================================================================================== */ 1579*150812a8SEvalZero /* ================ RTC0 ================ */ 1580*150812a8SEvalZero /* =========================================================================================================================== */ 1581*150812a8SEvalZero 1582*150812a8SEvalZero 1583*150812a8SEvalZero /** 1584*150812a8SEvalZero * @brief Real time counter 0 (RTC0) 1585*150812a8SEvalZero */ 1586*150812a8SEvalZero 1587*150812a8SEvalZero typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 1588*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ 1589*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ 1590*150812a8SEvalZero __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ 1591*150812a8SEvalZero __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ 1592*150812a8SEvalZero __IM uint32_t RESERVED[60]; 1593*150812a8SEvalZero __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ 1594*150812a8SEvalZero __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ 1595*150812a8SEvalZero __IM uint32_t RESERVED1[14]; 1596*150812a8SEvalZero __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[0]: Compare event on CC[0] 1597*150812a8SEvalZero match */ 1598*150812a8SEvalZero __IM uint32_t RESERVED2[109]; 1599*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1600*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1601*150812a8SEvalZero __IM uint32_t RESERVED3[13]; 1602*150812a8SEvalZero __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1603*150812a8SEvalZero __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1604*150812a8SEvalZero __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1605*150812a8SEvalZero __IM uint32_t RESERVED4[110]; 1606*150812a8SEvalZero __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ 1607*150812a8SEvalZero __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu 1608*150812a8SEvalZero t be written when RTC is stopped */ 1609*150812a8SEvalZero __IM uint32_t RESERVED5[13]; 1610*150812a8SEvalZero __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[0]: Compare register 0 */ 1611*150812a8SEvalZero } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1612*150812a8SEvalZero 1613*150812a8SEvalZero 1614*150812a8SEvalZero 1615*150812a8SEvalZero /* =========================================================================================================================== */ 1616*150812a8SEvalZero /* ================ TEMP ================ */ 1617*150812a8SEvalZero /* =========================================================================================================================== */ 1618*150812a8SEvalZero 1619*150812a8SEvalZero 1620*150812a8SEvalZero /** 1621*150812a8SEvalZero * @brief Temperature Sensor (TEMP) 1622*150812a8SEvalZero */ 1623*150812a8SEvalZero 1624*150812a8SEvalZero typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 1625*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 1626*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 1627*150812a8SEvalZero __IM uint32_t RESERVED[62]; 1628*150812a8SEvalZero __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 1629*150812a8SEvalZero __IM uint32_t RESERVED1[128]; 1630*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1631*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1632*150812a8SEvalZero __IM uint32_t RESERVED2[127]; 1633*150812a8SEvalZero __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 1634*150812a8SEvalZero __IM uint32_t RESERVED3[5]; 1635*150812a8SEvalZero __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ 1636*150812a8SEvalZero __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ 1637*150812a8SEvalZero __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ 1638*150812a8SEvalZero __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ 1639*150812a8SEvalZero __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ 1640*150812a8SEvalZero __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ 1641*150812a8SEvalZero __IM uint32_t RESERVED4[2]; 1642*150812a8SEvalZero __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ 1643*150812a8SEvalZero __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ 1644*150812a8SEvalZero __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ 1645*150812a8SEvalZero __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ 1646*150812a8SEvalZero __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ 1647*150812a8SEvalZero __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ 1648*150812a8SEvalZero __IM uint32_t RESERVED5[2]; 1649*150812a8SEvalZero __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ 1650*150812a8SEvalZero __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ 1651*150812a8SEvalZero __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ 1652*150812a8SEvalZero __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ 1653*150812a8SEvalZero __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ 1654*150812a8SEvalZero } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 1655*150812a8SEvalZero 1656*150812a8SEvalZero 1657*150812a8SEvalZero 1658*150812a8SEvalZero /* =========================================================================================================================== */ 1659*150812a8SEvalZero /* ================ RNG ================ */ 1660*150812a8SEvalZero /* =========================================================================================================================== */ 1661*150812a8SEvalZero 1662*150812a8SEvalZero 1663*150812a8SEvalZero /** 1664*150812a8SEvalZero * @brief Random Number Generator (RNG) 1665*150812a8SEvalZero */ 1666*150812a8SEvalZero 1667*150812a8SEvalZero typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 1668*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 1669*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 1670*150812a8SEvalZero __IM uint32_t RESERVED[62]; 1671*150812a8SEvalZero __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 1672*150812a8SEvalZero written to the VALUE register */ 1673*150812a8SEvalZero __IM uint32_t RESERVED1[63]; 1674*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1675*150812a8SEvalZero __IM uint32_t RESERVED2[64]; 1676*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1677*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1678*150812a8SEvalZero __IM uint32_t RESERVED3[126]; 1679*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1680*150812a8SEvalZero __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 1681*150812a8SEvalZero } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 1682*150812a8SEvalZero 1683*150812a8SEvalZero 1684*150812a8SEvalZero 1685*150812a8SEvalZero /* =========================================================================================================================== */ 1686*150812a8SEvalZero /* ================ ECB ================ */ 1687*150812a8SEvalZero /* =========================================================================================================================== */ 1688*150812a8SEvalZero 1689*150812a8SEvalZero 1690*150812a8SEvalZero /** 1691*150812a8SEvalZero * @brief AES ECB Mode Encryption (ECB) 1692*150812a8SEvalZero */ 1693*150812a8SEvalZero 1694*150812a8SEvalZero typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 1695*150812a8SEvalZero __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1696*150812a8SEvalZero __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1697*150812a8SEvalZero __IM uint32_t RESERVED[62]; 1698*150812a8SEvalZero __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1699*150812a8SEvalZero __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1700*150812a8SEvalZero task or due to an error */ 1701*150812a8SEvalZero __IM uint32_t RESERVED1[127]; 1702*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1703*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1704*150812a8SEvalZero __IM uint32_t RESERVED2[126]; 1705*150812a8SEvalZero __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1706*150812a8SEvalZero } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1707*150812a8SEvalZero 1708*150812a8SEvalZero 1709*150812a8SEvalZero 1710*150812a8SEvalZero /* =========================================================================================================================== */ 1711*150812a8SEvalZero /* ================ CCM ================ */ 1712*150812a8SEvalZero /* =========================================================================================================================== */ 1713*150812a8SEvalZero 1714*150812a8SEvalZero 1715*150812a8SEvalZero /** 1716*150812a8SEvalZero * @brief AES CCM Mode Encryption (CCM) 1717*150812a8SEvalZero */ 1718*150812a8SEvalZero 1719*150812a8SEvalZero typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 1720*150812a8SEvalZero __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation 1721*150812a8SEvalZero will stop by itself when completed. */ 1722*150812a8SEvalZero __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 1723*150812a8SEvalZero stop by itself when completed. */ 1724*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 1725*150812a8SEvalZero __IM uint32_t RESERVED[61]; 1726*150812a8SEvalZero __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ 1727*150812a8SEvalZero __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 1728*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) CCM error event */ 1729*150812a8SEvalZero __IM uint32_t RESERVED1[61]; 1730*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1731*150812a8SEvalZero __IM uint32_t RESERVED2[64]; 1732*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1733*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1734*150812a8SEvalZero __IM uint32_t RESERVED3[61]; 1735*150812a8SEvalZero __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 1736*150812a8SEvalZero __IM uint32_t RESERVED4[63]; 1737*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 1738*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 1739*150812a8SEvalZero __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and 1740*150812a8SEvalZero NONCE vector */ 1741*150812a8SEvalZero __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 1742*150812a8SEvalZero __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 1743*150812a8SEvalZero __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1744*150812a8SEvalZero } NRF_CCM_Type; /*!< Size = 1304 (0x518) */ 1745*150812a8SEvalZero 1746*150812a8SEvalZero 1747*150812a8SEvalZero 1748*150812a8SEvalZero /* =========================================================================================================================== */ 1749*150812a8SEvalZero /* ================ AAR ================ */ 1750*150812a8SEvalZero /* =========================================================================================================================== */ 1751*150812a8SEvalZero 1752*150812a8SEvalZero 1753*150812a8SEvalZero /** 1754*150812a8SEvalZero * @brief Accelerated Address Resolver (AAR) 1755*150812a8SEvalZero */ 1756*150812a8SEvalZero 1757*150812a8SEvalZero typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 1758*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 1759*150812a8SEvalZero in the IRK data structure */ 1760*150812a8SEvalZero __IM uint32_t RESERVED; 1761*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 1762*150812a8SEvalZero __IM uint32_t RESERVED1[61]; 1763*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 1764*150812a8SEvalZero __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 1765*150812a8SEvalZero __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 1766*150812a8SEvalZero __IM uint32_t RESERVED2[126]; 1767*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1768*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1769*150812a8SEvalZero __IM uint32_t RESERVED3[61]; 1770*150812a8SEvalZero __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 1771*150812a8SEvalZero __IM uint32_t RESERVED4[63]; 1772*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 1773*150812a8SEvalZero __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 1774*150812a8SEvalZero __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 1775*150812a8SEvalZero __IM uint32_t RESERVED5; 1776*150812a8SEvalZero __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 1777*150812a8SEvalZero __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1778*150812a8SEvalZero } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 1779*150812a8SEvalZero 1780*150812a8SEvalZero 1781*150812a8SEvalZero 1782*150812a8SEvalZero /* =========================================================================================================================== */ 1783*150812a8SEvalZero /* ================ WDT ================ */ 1784*150812a8SEvalZero /* =========================================================================================================================== */ 1785*150812a8SEvalZero 1786*150812a8SEvalZero 1787*150812a8SEvalZero /** 1788*150812a8SEvalZero * @brief Watchdog Timer (WDT) 1789*150812a8SEvalZero */ 1790*150812a8SEvalZero 1791*150812a8SEvalZero typedef struct { /*!< (@ 0x40010000) WDT Structure */ 1792*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 1793*150812a8SEvalZero __IM uint32_t RESERVED[63]; 1794*150812a8SEvalZero __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 1795*150812a8SEvalZero __IM uint32_t RESERVED1[128]; 1796*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1797*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1798*150812a8SEvalZero __IM uint32_t RESERVED2[61]; 1799*150812a8SEvalZero __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 1800*150812a8SEvalZero __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 1801*150812a8SEvalZero __IM uint32_t RESERVED3[63]; 1802*150812a8SEvalZero __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 1803*150812a8SEvalZero __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 1804*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 1805*150812a8SEvalZero __IM uint32_t RESERVED4[60]; 1806*150812a8SEvalZero __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[0]: Reload request 0 */ 1807*150812a8SEvalZero } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 1808*150812a8SEvalZero 1809*150812a8SEvalZero 1810*150812a8SEvalZero 1811*150812a8SEvalZero /* =========================================================================================================================== */ 1812*150812a8SEvalZero /* ================ QDEC ================ */ 1813*150812a8SEvalZero /* =========================================================================================================================== */ 1814*150812a8SEvalZero 1815*150812a8SEvalZero 1816*150812a8SEvalZero /** 1817*150812a8SEvalZero * @brief Quadrature Decoder (QDEC) 1818*150812a8SEvalZero */ 1819*150812a8SEvalZero 1820*150812a8SEvalZero typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 1821*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ 1822*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ 1823*150812a8SEvalZero __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ 1824*150812a8SEvalZero __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ 1825*150812a8SEvalZero __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ 1826*150812a8SEvalZero __IM uint32_t RESERVED[59]; 1827*150812a8SEvalZero __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value 1828*150812a8SEvalZero written to the SAMPLE register */ 1829*150812a8SEvalZero __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ 1830*150812a8SEvalZero __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ 1831*150812a8SEvalZero __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ 1832*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ 1833*150812a8SEvalZero __IM uint32_t RESERVED1[59]; 1834*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1835*150812a8SEvalZero __IM uint32_t RESERVED2[64]; 1836*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1837*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1838*150812a8SEvalZero __IM uint32_t RESERVED3[125]; 1839*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ 1840*150812a8SEvalZero __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ 1841*150812a8SEvalZero __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ 1842*150812a8SEvalZero __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ 1843*150812a8SEvalZero __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY 1844*150812a8SEvalZero and DBLRDY events can be generated */ 1845*150812a8SEvalZero __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ 1846*150812a8SEvalZero __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the 1847*150812a8SEvalZero READCLRACC or RDCLRACC task */ 1848*150812a8SEvalZero __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ 1849*150812a8SEvalZero __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ 1850*150812a8SEvalZero __IM uint32_t RESERVED4[5]; 1851*150812a8SEvalZero __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ 1852*150812a8SEvalZero __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected 1853*150812a8SEvalZero double transitions */ 1854*150812a8SEvalZero __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC 1855*150812a8SEvalZero or RDCLRDBL task */ 1856*150812a8SEvalZero } NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ 1857*150812a8SEvalZero 1858*150812a8SEvalZero 1859*150812a8SEvalZero 1860*150812a8SEvalZero /* =========================================================================================================================== */ 1861*150812a8SEvalZero /* ================ COMP ================ */ 1862*150812a8SEvalZero /* =========================================================================================================================== */ 1863*150812a8SEvalZero 1864*150812a8SEvalZero 1865*150812a8SEvalZero /** 1866*150812a8SEvalZero * @brief Comparator (COMP) 1867*150812a8SEvalZero */ 1868*150812a8SEvalZero 1869*150812a8SEvalZero typedef struct { /*!< (@ 0x40013000) COMP Structure */ 1870*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 1871*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 1872*150812a8SEvalZero __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 1873*150812a8SEvalZero __IM uint32_t RESERVED[61]; 1874*150812a8SEvalZero __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ 1875*150812a8SEvalZero __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 1876*150812a8SEvalZero __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 1877*150812a8SEvalZero __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 1878*150812a8SEvalZero __IM uint32_t RESERVED1[60]; 1879*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1880*150812a8SEvalZero __IM uint32_t RESERVED2[63]; 1881*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1882*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1883*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1884*150812a8SEvalZero __IM uint32_t RESERVED3[61]; 1885*150812a8SEvalZero __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 1886*150812a8SEvalZero __IM uint32_t RESERVED4[63]; 1887*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ 1888*150812a8SEvalZero __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ 1889*150812a8SEvalZero __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ 1890*150812a8SEvalZero __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 1891*150812a8SEvalZero __IM uint32_t RESERVED5[8]; 1892*150812a8SEvalZero __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ 1893*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ 1894*150812a8SEvalZero __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 1895*150812a8SEvalZero __IOM uint32_t ISOURCE; /*!< (@ 0x0000053C) Current source select on analog input */ 1896*150812a8SEvalZero } NRF_COMP_Type; /*!< Size = 1344 (0x540) */ 1897*150812a8SEvalZero 1898*150812a8SEvalZero 1899*150812a8SEvalZero 1900*150812a8SEvalZero /* =========================================================================================================================== */ 1901*150812a8SEvalZero /* ================ LPCOMP ================ */ 1902*150812a8SEvalZero /* =========================================================================================================================== */ 1903*150812a8SEvalZero 1904*150812a8SEvalZero 1905*150812a8SEvalZero /** 1906*150812a8SEvalZero * @brief Low Power Comparator (LPCOMP) 1907*150812a8SEvalZero */ 1908*150812a8SEvalZero 1909*150812a8SEvalZero typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ 1910*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 1911*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 1912*150812a8SEvalZero __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 1913*150812a8SEvalZero __IM uint32_t RESERVED[61]; 1914*150812a8SEvalZero __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ 1915*150812a8SEvalZero __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 1916*150812a8SEvalZero __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 1917*150812a8SEvalZero __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 1918*150812a8SEvalZero __IM uint32_t RESERVED1[60]; 1919*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1920*150812a8SEvalZero __IM uint32_t RESERVED2[64]; 1921*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1922*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1923*150812a8SEvalZero __IM uint32_t RESERVED3[61]; 1924*150812a8SEvalZero __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 1925*150812a8SEvalZero __IM uint32_t RESERVED4[63]; 1926*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ 1927*150812a8SEvalZero __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ 1928*150812a8SEvalZero __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ 1929*150812a8SEvalZero __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 1930*150812a8SEvalZero __IM uint32_t RESERVED5[4]; 1931*150812a8SEvalZero __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ 1932*150812a8SEvalZero __IM uint32_t RESERVED6[5]; 1933*150812a8SEvalZero __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 1934*150812a8SEvalZero } NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ 1935*150812a8SEvalZero 1936*150812a8SEvalZero 1937*150812a8SEvalZero 1938*150812a8SEvalZero /* =========================================================================================================================== */ 1939*150812a8SEvalZero /* ================ SWI0 ================ */ 1940*150812a8SEvalZero /* =========================================================================================================================== */ 1941*150812a8SEvalZero 1942*150812a8SEvalZero 1943*150812a8SEvalZero /** 1944*150812a8SEvalZero * @brief Software interrupt 0 (SWI0) 1945*150812a8SEvalZero */ 1946*150812a8SEvalZero 1947*150812a8SEvalZero typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ 1948*150812a8SEvalZero __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1949*150812a8SEvalZero } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 1950*150812a8SEvalZero 1951*150812a8SEvalZero 1952*150812a8SEvalZero 1953*150812a8SEvalZero /* =========================================================================================================================== */ 1954*150812a8SEvalZero /* ================ EGU0 ================ */ 1955*150812a8SEvalZero /* =========================================================================================================================== */ 1956*150812a8SEvalZero 1957*150812a8SEvalZero 1958*150812a8SEvalZero /** 1959*150812a8SEvalZero * @brief Event Generator Unit 0 (EGU0) 1960*150812a8SEvalZero */ 1961*150812a8SEvalZero 1962*150812a8SEvalZero typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ 1963*150812a8SEvalZero __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[0]: Trigger 0 for triggering 1964*150812a8SEvalZero the corresponding TRIGGERED[0] event */ 1965*150812a8SEvalZero __IM uint32_t RESERVED[48]; 1966*150812a8SEvalZero __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[0]: Event number 0 generated 1967*150812a8SEvalZero by triggering the corresponding TRIGGER[0] 1968*150812a8SEvalZero task */ 1969*150812a8SEvalZero __IM uint32_t RESERVED1[112]; 1970*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1971*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1972*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1973*150812a8SEvalZero } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1974*150812a8SEvalZero 1975*150812a8SEvalZero 1976*150812a8SEvalZero 1977*150812a8SEvalZero /* =========================================================================================================================== */ 1978*150812a8SEvalZero /* ================ PWM0 ================ */ 1979*150812a8SEvalZero /* =========================================================================================================================== */ 1980*150812a8SEvalZero 1981*150812a8SEvalZero 1982*150812a8SEvalZero /** 1983*150812a8SEvalZero * @brief Pulse Width Modulation Unit 0 (PWM0) 1984*150812a8SEvalZero */ 1985*150812a8SEvalZero 1986*150812a8SEvalZero typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ 1987*150812a8SEvalZero __IM uint32_t RESERVED; 1988*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 1989*150812a8SEvalZero the end of current PWM period, and stops 1990*150812a8SEvalZero sequence playback */ 1991*150812a8SEvalZero __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[0]: Loads the first PWM 1992*150812a8SEvalZero value on all enabled channels from sequence 1993*150812a8SEvalZero 0, and starts playing that sequence at the 1994*150812a8SEvalZero rate defined in SEQ[0]REFRESH and/or DECODER.MODE. 1995*150812a8SEvalZero Causes PWM generation to start it was not 1996*150812a8SEvalZero running. */ 1997*150812a8SEvalZero __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 1998*150812a8SEvalZero all enabled channels if DECODER.MODE=NextStep. 1999*150812a8SEvalZero Does not cause PWM generation to start it 2000*150812a8SEvalZero was not running. */ 2001*150812a8SEvalZero __IM uint32_t RESERVED1[60]; 2002*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 2003*150812a8SEvalZero are no longer generated */ 2004*150812a8SEvalZero __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[0]: First PWM period started 2005*150812a8SEvalZero on sequence 0 */ 2006*150812a8SEvalZero __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[0]: Emitted at end of 2007*150812a8SEvalZero every sequence 0, when last value from RAM 2008*150812a8SEvalZero has been applied to wave counter */ 2009*150812a8SEvalZero __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 2010*150812a8SEvalZero __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 2011*150812a8SEvalZero of times defined in LOOP.CNT */ 2012*150812a8SEvalZero __IM uint32_t RESERVED2[56]; 2013*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 2014*150812a8SEvalZero __IM uint32_t RESERVED3[63]; 2015*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2016*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2017*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2018*150812a8SEvalZero __IM uint32_t RESERVED4[125]; 2019*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 2020*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 2021*150812a8SEvalZero __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 2022*150812a8SEvalZero counts */ 2023*150812a8SEvalZero __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 2024*150812a8SEvalZero __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 2025*150812a8SEvalZero __IOM uint32_t LOOP; /*!< (@ 0x00000514) Amount of playback of a loop */ 2026*150812a8SEvalZero __IM uint32_t RESERVED5[2]; 2027*150812a8SEvalZero __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 2028*150812a8SEvalZero __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2029*150812a8SEvalZero } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 2030*150812a8SEvalZero 2031*150812a8SEvalZero 2032*150812a8SEvalZero 2033*150812a8SEvalZero /* =========================================================================================================================== */ 2034*150812a8SEvalZero /* ================ PDM ================ */ 2035*150812a8SEvalZero /* =========================================================================================================================== */ 2036*150812a8SEvalZero 2037*150812a8SEvalZero 2038*150812a8SEvalZero /** 2039*150812a8SEvalZero * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) 2040*150812a8SEvalZero */ 2041*150812a8SEvalZero 2042*150812a8SEvalZero typedef struct { /*!< (@ 0x4001D000) PDM Structure */ 2043*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 2044*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 2045*150812a8SEvalZero __IM uint32_t RESERVED[62]; 2046*150812a8SEvalZero __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 2047*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 2048*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 2049*150812a8SEvalZero by SAMPLE.MAXCNT (or the last sample after 2050*150812a8SEvalZero a STOP task has been received) to Data RAM */ 2051*150812a8SEvalZero __IM uint32_t RESERVED1[125]; 2052*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2053*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2054*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2055*150812a8SEvalZero __IM uint32_t RESERVED2[125]; 2056*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 2057*150812a8SEvalZero __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 2058*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 2059*150812a8SEvalZero signals */ 2060*150812a8SEvalZero __IM uint32_t RESERVED3[3]; 2061*150812a8SEvalZero __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 2062*150812a8SEvalZero __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 2063*150812a8SEvalZero __IM uint32_t RESERVED4[8]; 2064*150812a8SEvalZero __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 2065*150812a8SEvalZero __IM uint32_t RESERVED5[6]; 2066*150812a8SEvalZero __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 2067*150812a8SEvalZero } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 2068*150812a8SEvalZero 2069*150812a8SEvalZero 2070*150812a8SEvalZero 2071*150812a8SEvalZero /* =========================================================================================================================== */ 2072*150812a8SEvalZero /* ================ NVMC ================ */ 2073*150812a8SEvalZero /* =========================================================================================================================== */ 2074*150812a8SEvalZero 2075*150812a8SEvalZero 2076*150812a8SEvalZero /** 2077*150812a8SEvalZero * @brief Non Volatile Memory Controller (NVMC) 2078*150812a8SEvalZero */ 2079*150812a8SEvalZero 2080*150812a8SEvalZero typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 2081*150812a8SEvalZero __IM uint32_t RESERVED[256]; 2082*150812a8SEvalZero __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 2083*150812a8SEvalZero __IM uint32_t RESERVED1[64]; 2084*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 2085*150812a8SEvalZero 2086*150812a8SEvalZero union { 2087*150812a8SEvalZero __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in Code area */ 2088*150812a8SEvalZero __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a 2089*150812a8SEvalZero page in Code area. Equivalent to ERASEPAGE. */ 2090*150812a8SEvalZero }; 2091*150812a8SEvalZero __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 2092*150812a8SEvalZero __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a 2093*150812a8SEvalZero page in Code area. Equivalent to ERASEPAGE. */ 2094*150812a8SEvalZero __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing User Information Configuration 2095*150812a8SEvalZero Registers */ 2096*150812a8SEvalZero __IM uint32_t RESERVED2[10]; 2097*150812a8SEvalZero __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-Code cache configuration register. */ 2098*150812a8SEvalZero __IM uint32_t RESERVED3; 2099*150812a8SEvalZero __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-Code cache hit counter. */ 2100*150812a8SEvalZero __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-Code cache miss counter. */ 2101*150812a8SEvalZero } NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ 2102*150812a8SEvalZero 2103*150812a8SEvalZero 2104*150812a8SEvalZero 2105*150812a8SEvalZero /* =========================================================================================================================== */ 2106*150812a8SEvalZero /* ================ PPI ================ */ 2107*150812a8SEvalZero /* =========================================================================================================================== */ 2108*150812a8SEvalZero 2109*150812a8SEvalZero 2110*150812a8SEvalZero /** 2111*150812a8SEvalZero * @brief Programmable Peripheral Interconnect (PPI) 2112*150812a8SEvalZero */ 2113*150812a8SEvalZero 2114*150812a8SEvalZero typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 2115*150812a8SEvalZero __IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 2116*150812a8SEvalZero __IM uint32_t RESERVED[308]; 2117*150812a8SEvalZero __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 2118*150812a8SEvalZero __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 2119*150812a8SEvalZero __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 2120*150812a8SEvalZero __IM uint32_t RESERVED1; 2121*150812a8SEvalZero __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ 2122*150812a8SEvalZero __IM uint32_t RESERVED2[148]; 2123*150812a8SEvalZero __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[0]: Channel group 0 */ 2124*150812a8SEvalZero __IM uint32_t RESERVED3[62]; 2125*150812a8SEvalZero __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ 2126*150812a8SEvalZero } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ 2127*150812a8SEvalZero 2128*150812a8SEvalZero 2129*150812a8SEvalZero 2130*150812a8SEvalZero /* =========================================================================================================================== */ 2131*150812a8SEvalZero /* ================ MWU ================ */ 2132*150812a8SEvalZero /* =========================================================================================================================== */ 2133*150812a8SEvalZero 2134*150812a8SEvalZero 2135*150812a8SEvalZero /** 2136*150812a8SEvalZero * @brief Memory Watch Unit (MWU) 2137*150812a8SEvalZero */ 2138*150812a8SEvalZero 2139*150812a8SEvalZero typedef struct { /*!< (@ 0x40020000) MWU Structure */ 2140*150812a8SEvalZero __IM uint32_t RESERVED[64]; 2141*150812a8SEvalZero __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Unspecified */ 2142*150812a8SEvalZero __IM uint32_t RESERVED1[16]; 2143*150812a8SEvalZero __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Unspecified */ 2144*150812a8SEvalZero __IM uint32_t RESERVED2[100]; 2145*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2146*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2147*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2148*150812a8SEvalZero __IM uint32_t RESERVED3[5]; 2149*150812a8SEvalZero __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable non-maskable interrupt */ 2150*150812a8SEvalZero __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable non-maskable interrupt */ 2151*150812a8SEvalZero __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable non-maskable interrupt */ 2152*150812a8SEvalZero __IM uint32_t RESERVED4[53]; 2153*150812a8SEvalZero __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ 2154*150812a8SEvalZero __IM uint32_t RESERVED5[64]; 2155*150812a8SEvalZero __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */ 2156*150812a8SEvalZero __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */ 2157*150812a8SEvalZero __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */ 2158*150812a8SEvalZero __IM uint32_t RESERVED6[57]; 2159*150812a8SEvalZero __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */ 2160*150812a8SEvalZero __IM uint32_t RESERVED7[32]; 2161*150812a8SEvalZero __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */ 2162*150812a8SEvalZero } NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */ 2163*150812a8SEvalZero 2164*150812a8SEvalZero 2165*150812a8SEvalZero 2166*150812a8SEvalZero /* =========================================================================================================================== */ 2167*150812a8SEvalZero /* ================ I2S ================ */ 2168*150812a8SEvalZero /* =========================================================================================================================== */ 2169*150812a8SEvalZero 2170*150812a8SEvalZero 2171*150812a8SEvalZero /** 2172*150812a8SEvalZero * @brief Inter-IC Sound (I2S) 2173*150812a8SEvalZero */ 2174*150812a8SEvalZero 2175*150812a8SEvalZero typedef struct { /*!< (@ 0x40025000) I2S Structure */ 2176*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK 2177*150812a8SEvalZero generator when this is enabled. */ 2178*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. 2179*150812a8SEvalZero Triggering this task will cause the {event:STOPPED} 2180*150812a8SEvalZero event to be generated. */ 2181*150812a8SEvalZero __IM uint32_t RESERVED[63]; 2182*150812a8SEvalZero __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal 2183*150812a8SEvalZero double-buffers. When the I2S module is started 2184*150812a8SEvalZero and RX is enabled, this event will be generated 2185*150812a8SEvalZero for every RXTXD.MAXCNT words that are received 2186*150812a8SEvalZero on the SDIN pin. */ 2187*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ 2188*150812a8SEvalZero __IM uint32_t RESERVED1[2]; 2189*150812a8SEvalZero __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal 2190*150812a8SEvalZero double-buffers. When the I2S module is started 2191*150812a8SEvalZero and TX is enabled, this event will be generated 2192*150812a8SEvalZero for every RXTXD.MAXCNT words that are sent 2193*150812a8SEvalZero on the SDOUT pin. */ 2194*150812a8SEvalZero __IM uint32_t RESERVED2[122]; 2195*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2196*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2197*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2198*150812a8SEvalZero __IM uint32_t RESERVED3[125]; 2199*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ 2200*150812a8SEvalZero __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ 2201*150812a8SEvalZero __IM uint32_t RESERVED4[3]; 2202*150812a8SEvalZero __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ 2203*150812a8SEvalZero __IM uint32_t RESERVED5; 2204*150812a8SEvalZero __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ 2205*150812a8SEvalZero __IM uint32_t RESERVED6[3]; 2206*150812a8SEvalZero __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ 2207*150812a8SEvalZero __IM uint32_t RESERVED7[3]; 2208*150812a8SEvalZero __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2209*150812a8SEvalZero } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ 2210*150812a8SEvalZero 2211*150812a8SEvalZero 2212*150812a8SEvalZero 2213*150812a8SEvalZero /* =========================================================================================================================== */ 2214*150812a8SEvalZero /* ================ FPU ================ */ 2215*150812a8SEvalZero /* =========================================================================================================================== */ 2216*150812a8SEvalZero 2217*150812a8SEvalZero 2218*150812a8SEvalZero /** 2219*150812a8SEvalZero * @brief FPU (FPU) 2220*150812a8SEvalZero */ 2221*150812a8SEvalZero 2222*150812a8SEvalZero typedef struct { /*!< (@ 0x40026000) FPU Structure */ 2223*150812a8SEvalZero __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 2224*150812a8SEvalZero } NRF_FPU_Type; /*!< Size = 4 (0x4) */ 2225*150812a8SEvalZero 2226*150812a8SEvalZero 2227*150812a8SEvalZero 2228*150812a8SEvalZero /* =========================================================================================================================== */ 2229*150812a8SEvalZero /* ================ P0 ================ */ 2230*150812a8SEvalZero /* =========================================================================================================================== */ 2231*150812a8SEvalZero 2232*150812a8SEvalZero 2233*150812a8SEvalZero /** 2234*150812a8SEvalZero * @brief GPIO Port 1 (P0) 2235*150812a8SEvalZero */ 2236*150812a8SEvalZero 2237*150812a8SEvalZero typedef struct { /*!< (@ 0x50000000) P0 Structure */ 2238*150812a8SEvalZero __IM uint32_t RESERVED[321]; 2239*150812a8SEvalZero __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ 2240*150812a8SEvalZero __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ 2241*150812a8SEvalZero __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ 2242*150812a8SEvalZero __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ 2243*150812a8SEvalZero __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ 2244*150812a8SEvalZero __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ 2245*150812a8SEvalZero __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ 2246*150812a8SEvalZero __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that 2247*150812a8SEvalZero have met the criteria set in the PIN_CNF[n].SENSE 2248*150812a8SEvalZero registers */ 2249*150812a8SEvalZero __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour 2250*150812a8SEvalZero and LDETECT mode */ 2251*150812a8SEvalZero __IM uint32_t RESERVED1[118]; 2252*150812a8SEvalZero __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[0]: Configuration of GPIO 2253*150812a8SEvalZero pins */ 2254*150812a8SEvalZero } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 2255*150812a8SEvalZero 2256*150812a8SEvalZero 2257*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_peripherals */ 2258*150812a8SEvalZero 2259*150812a8SEvalZero 2260*150812a8SEvalZero /* =========================================================================================================================== */ 2261*150812a8SEvalZero /* ================ Device Specific Peripheral Address Map ================ */ 2262*150812a8SEvalZero /* =========================================================================================================================== */ 2263*150812a8SEvalZero 2264*150812a8SEvalZero 2265*150812a8SEvalZero /** @addtogroup Device_Peripheral_peripheralAddr 2266*150812a8SEvalZero * @{ 2267*150812a8SEvalZero */ 2268*150812a8SEvalZero 2269*150812a8SEvalZero #define NRF_FICR_BASE 0x10000000UL 2270*150812a8SEvalZero #define NRF_UICR_BASE 0x10001000UL 2271*150812a8SEvalZero #define NRF_BPROT_BASE 0x40000000UL 2272*150812a8SEvalZero #define NRF_POWER_BASE 0x40000000UL 2273*150812a8SEvalZero #define NRF_CLOCK_BASE 0x40000000UL 2274*150812a8SEvalZero #define NRF_RADIO_BASE 0x40001000UL 2275*150812a8SEvalZero #define NRF_UARTE0_BASE 0x40002000UL 2276*150812a8SEvalZero #define NRF_UART0_BASE 0x40002000UL 2277*150812a8SEvalZero #define NRF_SPIM0_BASE 0x40003000UL 2278*150812a8SEvalZero #define NRF_SPIS0_BASE 0x40003000UL 2279*150812a8SEvalZero #define NRF_TWIM0_BASE 0x40003000UL 2280*150812a8SEvalZero #define NRF_TWIS0_BASE 0x40003000UL 2281*150812a8SEvalZero #define NRF_SPI0_BASE 0x40003000UL 2282*150812a8SEvalZero #define NRF_TWI0_BASE 0x40003000UL 2283*150812a8SEvalZero #define NRF_SPIM1_BASE 0x40004000UL 2284*150812a8SEvalZero #define NRF_SPIS1_BASE 0x40004000UL 2285*150812a8SEvalZero #define NRF_TWIM1_BASE 0x40004000UL 2286*150812a8SEvalZero #define NRF_TWIS1_BASE 0x40004000UL 2287*150812a8SEvalZero #define NRF_SPI1_BASE 0x40004000UL 2288*150812a8SEvalZero #define NRF_TWI1_BASE 0x40004000UL 2289*150812a8SEvalZero #define NRF_NFCT_BASE 0x40005000UL 2290*150812a8SEvalZero #define NRF_GPIOTE_BASE 0x40006000UL 2291*150812a8SEvalZero #define NRF_SAADC_BASE 0x40007000UL 2292*150812a8SEvalZero #define NRF_TIMER0_BASE 0x40008000UL 2293*150812a8SEvalZero #define NRF_TIMER1_BASE 0x40009000UL 2294*150812a8SEvalZero #define NRF_TIMER2_BASE 0x4000A000UL 2295*150812a8SEvalZero #define NRF_RTC0_BASE 0x4000B000UL 2296*150812a8SEvalZero #define NRF_TEMP_BASE 0x4000C000UL 2297*150812a8SEvalZero #define NRF_RNG_BASE 0x4000D000UL 2298*150812a8SEvalZero #define NRF_ECB_BASE 0x4000E000UL 2299*150812a8SEvalZero #define NRF_CCM_BASE 0x4000F000UL 2300*150812a8SEvalZero #define NRF_AAR_BASE 0x4000F000UL 2301*150812a8SEvalZero #define NRF_WDT_BASE 0x40010000UL 2302*150812a8SEvalZero #define NRF_RTC1_BASE 0x40011000UL 2303*150812a8SEvalZero #define NRF_QDEC_BASE 0x40012000UL 2304*150812a8SEvalZero #define NRF_COMP_BASE 0x40013000UL 2305*150812a8SEvalZero #define NRF_LPCOMP_BASE 0x40013000UL 2306*150812a8SEvalZero #define NRF_SWI0_BASE 0x40014000UL 2307*150812a8SEvalZero #define NRF_EGU0_BASE 0x40014000UL 2308*150812a8SEvalZero #define NRF_SWI1_BASE 0x40015000UL 2309*150812a8SEvalZero #define NRF_EGU1_BASE 0x40015000UL 2310*150812a8SEvalZero #define NRF_SWI2_BASE 0x40016000UL 2311*150812a8SEvalZero #define NRF_EGU2_BASE 0x40016000UL 2312*150812a8SEvalZero #define NRF_SWI3_BASE 0x40017000UL 2313*150812a8SEvalZero #define NRF_EGU3_BASE 0x40017000UL 2314*150812a8SEvalZero #define NRF_SWI4_BASE 0x40018000UL 2315*150812a8SEvalZero #define NRF_EGU4_BASE 0x40018000UL 2316*150812a8SEvalZero #define NRF_SWI5_BASE 0x40019000UL 2317*150812a8SEvalZero #define NRF_EGU5_BASE 0x40019000UL 2318*150812a8SEvalZero #define NRF_TIMER3_BASE 0x4001A000UL 2319*150812a8SEvalZero #define NRF_TIMER4_BASE 0x4001B000UL 2320*150812a8SEvalZero #define NRF_PWM0_BASE 0x4001C000UL 2321*150812a8SEvalZero #define NRF_PDM_BASE 0x4001D000UL 2322*150812a8SEvalZero #define NRF_NVMC_BASE 0x4001E000UL 2323*150812a8SEvalZero #define NRF_PPI_BASE 0x4001F000UL 2324*150812a8SEvalZero #define NRF_MWU_BASE 0x40020000UL 2325*150812a8SEvalZero #define NRF_PWM1_BASE 0x40021000UL 2326*150812a8SEvalZero #define NRF_PWM2_BASE 0x40022000UL 2327*150812a8SEvalZero #define NRF_SPIM2_BASE 0x40023000UL 2328*150812a8SEvalZero #define NRF_SPIS2_BASE 0x40023000UL 2329*150812a8SEvalZero #define NRF_SPI2_BASE 0x40023000UL 2330*150812a8SEvalZero #define NRF_RTC2_BASE 0x40024000UL 2331*150812a8SEvalZero #define NRF_I2S_BASE 0x40025000UL 2332*150812a8SEvalZero #define NRF_FPU_BASE 0x40026000UL 2333*150812a8SEvalZero #define NRF_P0_BASE 0x50000000UL 2334*150812a8SEvalZero 2335*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 2336*150812a8SEvalZero 2337*150812a8SEvalZero 2338*150812a8SEvalZero /* =========================================================================================================================== */ 2339*150812a8SEvalZero /* ================ Peripheral declaration ================ */ 2340*150812a8SEvalZero /* =========================================================================================================================== */ 2341*150812a8SEvalZero 2342*150812a8SEvalZero 2343*150812a8SEvalZero /** @addtogroup Device_Peripheral_declaration 2344*150812a8SEvalZero * @{ 2345*150812a8SEvalZero */ 2346*150812a8SEvalZero 2347*150812a8SEvalZero #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 2348*150812a8SEvalZero #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 2349*150812a8SEvalZero #define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) 2350*150812a8SEvalZero #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 2351*150812a8SEvalZero #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 2352*150812a8SEvalZero #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 2353*150812a8SEvalZero #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) 2354*150812a8SEvalZero #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) 2355*150812a8SEvalZero #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) 2356*150812a8SEvalZero #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) 2357*150812a8SEvalZero #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) 2358*150812a8SEvalZero #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) 2359*150812a8SEvalZero #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) 2360*150812a8SEvalZero #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) 2361*150812a8SEvalZero #define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) 2362*150812a8SEvalZero #define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) 2363*150812a8SEvalZero #define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) 2364*150812a8SEvalZero #define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) 2365*150812a8SEvalZero #define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) 2366*150812a8SEvalZero #define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) 2367*150812a8SEvalZero #define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) 2368*150812a8SEvalZero #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 2369*150812a8SEvalZero #define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) 2370*150812a8SEvalZero #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 2371*150812a8SEvalZero #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 2372*150812a8SEvalZero #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 2373*150812a8SEvalZero #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 2374*150812a8SEvalZero #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 2375*150812a8SEvalZero #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 2376*150812a8SEvalZero #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 2377*150812a8SEvalZero #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 2378*150812a8SEvalZero #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 2379*150812a8SEvalZero #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 2380*150812a8SEvalZero #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 2381*150812a8SEvalZero #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 2382*150812a8SEvalZero #define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) 2383*150812a8SEvalZero #define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) 2384*150812a8SEvalZero #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) 2385*150812a8SEvalZero #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) 2386*150812a8SEvalZero #define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) 2387*150812a8SEvalZero #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) 2388*150812a8SEvalZero #define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) 2389*150812a8SEvalZero #define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) 2390*150812a8SEvalZero #define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) 2391*150812a8SEvalZero #define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) 2392*150812a8SEvalZero #define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) 2393*150812a8SEvalZero #define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) 2394*150812a8SEvalZero #define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) 2395*150812a8SEvalZero #define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) 2396*150812a8SEvalZero #define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) 2397*150812a8SEvalZero #define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) 2398*150812a8SEvalZero #define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) 2399*150812a8SEvalZero #define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) 2400*150812a8SEvalZero #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 2401*150812a8SEvalZero #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 2402*150812a8SEvalZero #define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) 2403*150812a8SEvalZero #define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) 2404*150812a8SEvalZero #define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) 2405*150812a8SEvalZero #define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) 2406*150812a8SEvalZero #define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) 2407*150812a8SEvalZero #define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) 2408*150812a8SEvalZero #define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) 2409*150812a8SEvalZero #define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) 2410*150812a8SEvalZero #define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) 2411*150812a8SEvalZero #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) 2412*150812a8SEvalZero 2413*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_declaration */ 2414*150812a8SEvalZero 2415*150812a8SEvalZero 2416*150812a8SEvalZero /* ========================================= End of section using anonymous unions ========================================= */ 2417*150812a8SEvalZero #if defined (__CC_ARM) 2418*150812a8SEvalZero #pragma pop 2419*150812a8SEvalZero #elif defined (__ICCARM__) 2420*150812a8SEvalZero /* leave anonymous unions enabled */ 2421*150812a8SEvalZero #elif (__ARMCC_VERSION >= 6010050) 2422*150812a8SEvalZero #pragma clang diagnostic pop 2423*150812a8SEvalZero #elif defined (__GNUC__) 2424*150812a8SEvalZero /* anonymous unions are enabled by default */ 2425*150812a8SEvalZero #elif defined (__TMS470__) 2426*150812a8SEvalZero /* anonymous unions are enabled by default */ 2427*150812a8SEvalZero #elif defined (__TASKING__) 2428*150812a8SEvalZero #pragma warning restore 2429*150812a8SEvalZero #elif defined (__CSMC__) 2430*150812a8SEvalZero /* anonymous unions are enabled by default */ 2431*150812a8SEvalZero #endif 2432*150812a8SEvalZero 2433*150812a8SEvalZero 2434*150812a8SEvalZero #ifdef __cplusplus 2435*150812a8SEvalZero } 2436*150812a8SEvalZero #endif 2437*150812a8SEvalZero 2438*150812a8SEvalZero #endif /* NRF52_H */ 2439*150812a8SEvalZero 2440*150812a8SEvalZero 2441*150812a8SEvalZero /** @} */ /* End of group nrf52 */ 2442*150812a8SEvalZero 2443*150812a8SEvalZero /** @} */ /* End of group Nordic Semiconductor */ 2444