1*150812a8SEvalZero /* 2*150812a8SEvalZero * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. 3*150812a8SEvalZero * 4*150812a8SEvalZero * Redistribution and use in source and binary forms, with or without 5*150812a8SEvalZero * modification, are permitted provided that the following conditions are met: 6*150812a8SEvalZero * 7*150812a8SEvalZero * 1. Redistributions of source code must retain the above copyright notice, this 8*150812a8SEvalZero * list of conditions and the following disclaimer. 9*150812a8SEvalZero * 10*150812a8SEvalZero * 2. Redistributions in binary form must reproduce the above copyright 11*150812a8SEvalZero * notice, this list of conditions and the following disclaimer in the 12*150812a8SEvalZero * documentation and/or other materials provided with the distribution. 13*150812a8SEvalZero * 14*150812a8SEvalZero * 3. Neither the name of Nordic Semiconductor ASA nor the names of its 15*150812a8SEvalZero * contributors may be used to endorse or promote products derived from this 16*150812a8SEvalZero * software without specific prior written permission. 17*150812a8SEvalZero * 18*150812a8SEvalZero * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*150812a8SEvalZero * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*150812a8SEvalZero * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 21*150812a8SEvalZero * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 22*150812a8SEvalZero * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*150812a8SEvalZero * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*150812a8SEvalZero * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*150812a8SEvalZero * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*150812a8SEvalZero * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*150812a8SEvalZero * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*150812a8SEvalZero * POSSIBILITY OF SUCH DAMAGE. 29*150812a8SEvalZero * 30*150812a8SEvalZero * @file nrf9160.h 31*150812a8SEvalZero * @brief CMSIS HeaderFile 32*150812a8SEvalZero * @version 1 33*150812a8SEvalZero * @date 03. December 2018 34*150812a8SEvalZero * @note Generated by SVDConv V3.3.18 on Monday, 03.12.2018 11:18:26 35*150812a8SEvalZero * from File 'nrf9160.svd', 36*150812a8SEvalZero * last modified on Monday, 03.12.2018 10:18:21 37*150812a8SEvalZero */ 38*150812a8SEvalZero 39*150812a8SEvalZero 40*150812a8SEvalZero 41*150812a8SEvalZero /** @addtogroup Nordic Semiconductor 42*150812a8SEvalZero * @{ 43*150812a8SEvalZero */ 44*150812a8SEvalZero 45*150812a8SEvalZero 46*150812a8SEvalZero /** @addtogroup nrf9160 47*150812a8SEvalZero * @{ 48*150812a8SEvalZero */ 49*150812a8SEvalZero 50*150812a8SEvalZero 51*150812a8SEvalZero #ifndef NRF9160_H 52*150812a8SEvalZero #define NRF9160_H 53*150812a8SEvalZero 54*150812a8SEvalZero #ifdef __cplusplus 55*150812a8SEvalZero extern "C" { 56*150812a8SEvalZero #endif 57*150812a8SEvalZero 58*150812a8SEvalZero 59*150812a8SEvalZero /** @addtogroup Configuration_of_CMSIS 60*150812a8SEvalZero * @{ 61*150812a8SEvalZero */ 62*150812a8SEvalZero 63*150812a8SEvalZero 64*150812a8SEvalZero 65*150812a8SEvalZero /* =========================================================================================================================== */ 66*150812a8SEvalZero /* ================ Interrupt Number Definition ================ */ 67*150812a8SEvalZero /* =========================================================================================================================== */ 68*150812a8SEvalZero 69*150812a8SEvalZero typedef enum { 70*150812a8SEvalZero /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ 71*150812a8SEvalZero Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 72*150812a8SEvalZero NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 73*150812a8SEvalZero HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 74*150812a8SEvalZero MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 75*150812a8SEvalZero and No Match */ 76*150812a8SEvalZero BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 77*150812a8SEvalZero related Fault */ 78*150812a8SEvalZero UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 79*150812a8SEvalZero SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ 80*150812a8SEvalZero SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 81*150812a8SEvalZero DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 82*150812a8SEvalZero PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 83*150812a8SEvalZero SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 84*150812a8SEvalZero /* ========================================== nrf9160 Specific Interrupt Numbers =========================================== */ 85*150812a8SEvalZero SPU_IRQn = 3, /*!< 3 SPU */ 86*150812a8SEvalZero CLOCK_POWER_IRQn = 5, /*!< 5 CLOCK_POWER */ 87*150812a8SEvalZero UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQn= 8, /*!< 8 UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 */ 88*150812a8SEvalZero UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQn= 9, /*!< 9 UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 */ 89*150812a8SEvalZero UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQn= 10, /*!< 10 UARTE2_SPIM2_SPIS2_TWIM2_TWIS2 */ 90*150812a8SEvalZero UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQn= 11, /*!< 11 UARTE3_SPIM3_SPIS3_TWIM3_TWIS3 */ 91*150812a8SEvalZero GPIOTE0_IRQn = 13, /*!< 13 GPIOTE0 */ 92*150812a8SEvalZero SAADC_IRQn = 14, /*!< 14 SAADC */ 93*150812a8SEvalZero TIMER0_IRQn = 15, /*!< 15 TIMER0 */ 94*150812a8SEvalZero TIMER1_IRQn = 16, /*!< 16 TIMER1 */ 95*150812a8SEvalZero TIMER2_IRQn = 17, /*!< 17 TIMER2 */ 96*150812a8SEvalZero RTC0_IRQn = 20, /*!< 20 RTC0 */ 97*150812a8SEvalZero RTC1_IRQn = 21, /*!< 21 RTC1 */ 98*150812a8SEvalZero WDT_IRQn = 24, /*!< 24 WDT */ 99*150812a8SEvalZero EGU0_IRQn = 27, /*!< 27 EGU0 */ 100*150812a8SEvalZero EGU1_IRQn = 28, /*!< 28 EGU1 */ 101*150812a8SEvalZero EGU2_IRQn = 29, /*!< 29 EGU2 */ 102*150812a8SEvalZero EGU3_IRQn = 30, /*!< 30 EGU3 */ 103*150812a8SEvalZero EGU4_IRQn = 31, /*!< 31 EGU4 */ 104*150812a8SEvalZero EGU5_IRQn = 32, /*!< 32 EGU5 */ 105*150812a8SEvalZero PWM0_IRQn = 33, /*!< 33 PWM0 */ 106*150812a8SEvalZero PWM1_IRQn = 34, /*!< 34 PWM1 */ 107*150812a8SEvalZero PWM2_IRQn = 35, /*!< 35 PWM2 */ 108*150812a8SEvalZero PWM3_IRQn = 36, /*!< 36 PWM3 */ 109*150812a8SEvalZero PDM_IRQn = 38, /*!< 38 PDM */ 110*150812a8SEvalZero I2S_IRQn = 40, /*!< 40 I2S */ 111*150812a8SEvalZero IPC_IRQn = 42, /*!< 42 IPC */ 112*150812a8SEvalZero FPU_IRQn = 44, /*!< 44 FPU */ 113*150812a8SEvalZero GPIOTE1_IRQn = 49, /*!< 49 GPIOTE1 */ 114*150812a8SEvalZero KMU_IRQn = 57, /*!< 57 KMU */ 115*150812a8SEvalZero CRYPTOCELL_IRQn = 64 /*!< 64 CRYPTOCELL */ 116*150812a8SEvalZero } IRQn_Type; 117*150812a8SEvalZero 118*150812a8SEvalZero 119*150812a8SEvalZero 120*150812a8SEvalZero /* =========================================================================================================================== */ 121*150812a8SEvalZero /* ================ Processor and Core Peripheral Section ================ */ 122*150812a8SEvalZero /* =========================================================================================================================== */ 123*150812a8SEvalZero 124*150812a8SEvalZero /* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ 125*150812a8SEvalZero #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ 126*150812a8SEvalZero #define __DSP_PRESENT 1 /*!< DSP present or not */ 127*150812a8SEvalZero #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 128*150812a8SEvalZero #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 129*150812a8SEvalZero #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 130*150812a8SEvalZero #define __MPU_PRESENT 1 /*!< MPU present or not */ 131*150812a8SEvalZero #define __FPU_PRESENT 1 /*!< FPU present or not */ 132*150812a8SEvalZero #define __FPU_DP 0 /*!< Double Precision FPU */ 133*150812a8SEvalZero #define __SAU_REGION_PRESENT 0 /*!< SAU present or not */ 134*150812a8SEvalZero 135*150812a8SEvalZero 136*150812a8SEvalZero /** @} */ /* End of group Configuration_of_CMSIS */ 137*150812a8SEvalZero 138*150812a8SEvalZero #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ 139*150812a8SEvalZero #include "system_nrf9160.h" /*!< nrf9160 System */ 140*150812a8SEvalZero 141*150812a8SEvalZero #ifndef __IM /*!< Fallback for older CMSIS versions */ 142*150812a8SEvalZero #define __IM __I 143*150812a8SEvalZero #endif 144*150812a8SEvalZero #ifndef __OM /*!< Fallback for older CMSIS versions */ 145*150812a8SEvalZero #define __OM __O 146*150812a8SEvalZero #endif 147*150812a8SEvalZero #ifndef __IOM /*!< Fallback for older CMSIS versions */ 148*150812a8SEvalZero #define __IOM __IO 149*150812a8SEvalZero #endif 150*150812a8SEvalZero 151*150812a8SEvalZero 152*150812a8SEvalZero /* =========================================================================================================================== */ 153*150812a8SEvalZero /* ================ Device Specific Cluster Section ================ */ 154*150812a8SEvalZero /* =========================================================================================================================== */ 155*150812a8SEvalZero 156*150812a8SEvalZero 157*150812a8SEvalZero /** @addtogroup Device_Peripheral_clusters 158*150812a8SEvalZero * @{ 159*150812a8SEvalZero */ 160*150812a8SEvalZero 161*150812a8SEvalZero 162*150812a8SEvalZero /** 163*150812a8SEvalZero * @brief FICR_INFO [INFO] (Device info) 164*150812a8SEvalZero */ 165*150812a8SEvalZero typedef struct { 166*150812a8SEvalZero __IM uint32_t RESERVED; 167*150812a8SEvalZero __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Description collection: Device identifier */ 168*150812a8SEvalZero __IM uint32_t PART; /*!< (@ 0x0000000C) Part code */ 169*150812a8SEvalZero __IM uint32_t VARIANT; /*!< (@ 0x00000010) Part Variant, Hardware version and Production 170*150812a8SEvalZero configuration */ 171*150812a8SEvalZero __IM uint32_t PACKAGE; /*!< (@ 0x00000014) Package option */ 172*150812a8SEvalZero __IM uint32_t RAM; /*!< (@ 0x00000018) RAM variant */ 173*150812a8SEvalZero __IM uint32_t FLASH; /*!< (@ 0x0000001C) Flash variant */ 174*150812a8SEvalZero __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000020) Code memory page size */ 175*150812a8SEvalZero __IM uint32_t CODESIZE; /*!< (@ 0x00000024) Code memory size */ 176*150812a8SEvalZero __IM uint32_t DEVICETYPE; /*!< (@ 0x00000028) Device type */ 177*150812a8SEvalZero } FICR_INFO_Type; /*!< Size = 44 (0x2c) */ 178*150812a8SEvalZero 179*150812a8SEvalZero 180*150812a8SEvalZero /** 181*150812a8SEvalZero * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified) 182*150812a8SEvalZero */ 183*150812a8SEvalZero typedef struct { 184*150812a8SEvalZero __IM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Address */ 185*150812a8SEvalZero __IM uint32_t DATA; /*!< (@ 0x00000004) Description cluster: Data */ 186*150812a8SEvalZero } FICR_TRIMCNF_Type; /*!< Size = 8 (0x8) */ 187*150812a8SEvalZero 188*150812a8SEvalZero 189*150812a8SEvalZero /** 190*150812a8SEvalZero * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) 191*150812a8SEvalZero */ 192*150812a8SEvalZero typedef struct { 193*150812a8SEvalZero __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ 194*150812a8SEvalZero __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ 195*150812a8SEvalZero __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ 196*150812a8SEvalZero __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ 197*150812a8SEvalZero __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ 198*150812a8SEvalZero __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ 199*150812a8SEvalZero __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ 200*150812a8SEvalZero __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ 201*150812a8SEvalZero } FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ 202*150812a8SEvalZero 203*150812a8SEvalZero 204*150812a8SEvalZero /** 205*150812a8SEvalZero * @brief UICR_KEYSLOT_CONFIG [CONFIG] (Unspecified) 206*150812a8SEvalZero */ 207*150812a8SEvalZero typedef struct { 208*150812a8SEvalZero __IOM uint32_t DEST; /*!< (@ 0x00000000) Description cluster: Destination address where 209*150812a8SEvalZero content of the key value registers (KEYSLOT.KEYn.VALUE[0-3 210*150812a8SEvalZero ) will be pushed by KMU. Note that this 211*150812a8SEvalZero address MUST match that of a peripherals 212*150812a8SEvalZero APB mapped write-only key registers, else 213*150812a8SEvalZero the KMU can push this key value into an 214*150812a8SEvalZero address range which the CPU can potentially 215*150812a8SEvalZero read! */ 216*150812a8SEvalZero __IOM uint32_t PERM; /*!< (@ 0x00000004) Description cluster: Define permissions for the 217*150812a8SEvalZero key slot with ID=n+1. Bits 0-15 and 16-31 218*150812a8SEvalZero can only be written once. */ 219*150812a8SEvalZero } UICR_KEYSLOT_CONFIG_Type; /*!< Size = 8 (0x8) */ 220*150812a8SEvalZero 221*150812a8SEvalZero 222*150812a8SEvalZero /** 223*150812a8SEvalZero * @brief UICR_KEYSLOT_KEY [KEY] (Unspecified) 224*150812a8SEvalZero */ 225*150812a8SEvalZero typedef struct { 226*150812a8SEvalZero __IOM uint32_t VALUE[4]; /*!< (@ 0x00000000) Description collection: Define bits [31+o*32:0+o*32] 227*150812a8SEvalZero of value assigned to KMU key slot ID=n+1 */ 228*150812a8SEvalZero } UICR_KEYSLOT_KEY_Type; /*!< Size = 16 (0x10) */ 229*150812a8SEvalZero 230*150812a8SEvalZero 231*150812a8SEvalZero /** 232*150812a8SEvalZero * @brief UICR_KEYSLOT [KEYSLOT] (Unspecified) 233*150812a8SEvalZero */ 234*150812a8SEvalZero typedef struct { 235*150812a8SEvalZero __IOM UICR_KEYSLOT_CONFIG_Type CONFIG[128]; /*!< (@ 0x00000000) Unspecified */ 236*150812a8SEvalZero __IOM UICR_KEYSLOT_KEY_Type KEY[128]; /*!< (@ 0x00000400) Unspecified */ 237*150812a8SEvalZero } UICR_KEYSLOT_Type; /*!< Size = 3072 (0xc00) */ 238*150812a8SEvalZero 239*150812a8SEvalZero 240*150812a8SEvalZero /** 241*150812a8SEvalZero * @brief TAD_PSEL [PSEL] (Unspecified) 242*150812a8SEvalZero */ 243*150812a8SEvalZero typedef struct { 244*150812a8SEvalZero __IOM uint32_t TRACECLK; /*!< (@ 0x00000000) Pin number configuration for TRACECLK */ 245*150812a8SEvalZero __IOM uint32_t TRACEDATA0; /*!< (@ 0x00000004) Pin number configuration for TRACEDATA[0] */ 246*150812a8SEvalZero __IOM uint32_t TRACEDATA1; /*!< (@ 0x00000008) Pin number configuration for TRACEDATA[1] */ 247*150812a8SEvalZero __IOM uint32_t TRACEDATA2; /*!< (@ 0x0000000C) Pin number configuration for TRACEDATA[2] */ 248*150812a8SEvalZero __IOM uint32_t TRACEDATA3; /*!< (@ 0x00000010) Pin number configuration for TRACEDATA[3] */ 249*150812a8SEvalZero } TAD_PSEL_Type; /*!< Size = 20 (0x14) */ 250*150812a8SEvalZero 251*150812a8SEvalZero 252*150812a8SEvalZero /** 253*150812a8SEvalZero * @brief SPU_EXTDOMAIN [EXTDOMAIN] (Unspecified) 254*150812a8SEvalZero */ 255*150812a8SEvalZero typedef struct { 256*150812a8SEvalZero __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access for bus access generated 257*150812a8SEvalZero from the external domain n List capabilities 258*150812a8SEvalZero of the external domain n */ 259*150812a8SEvalZero } SPU_EXTDOMAIN_Type; /*!< Size = 4 (0x4) */ 260*150812a8SEvalZero 261*150812a8SEvalZero 262*150812a8SEvalZero /** 263*150812a8SEvalZero * @brief SPU_DPPI [DPPI] (Unspecified) 264*150812a8SEvalZero */ 265*150812a8SEvalZero typedef struct { 266*150812a8SEvalZero __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and 267*150812a8SEvalZero non-secure attribute for the DPPI channels. */ 268*150812a8SEvalZero __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification 269*150812a8SEvalZero of the corresponding PERM register */ 270*150812a8SEvalZero } SPU_DPPI_Type; /*!< Size = 8 (0x8) */ 271*150812a8SEvalZero 272*150812a8SEvalZero 273*150812a8SEvalZero /** 274*150812a8SEvalZero * @brief SPU_GPIOPORT [GPIOPORT] (Unspecified) 275*150812a8SEvalZero */ 276*150812a8SEvalZero typedef struct { 277*150812a8SEvalZero __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and 278*150812a8SEvalZero non-secure attribute for pins 0 to 31 of 279*150812a8SEvalZero port n. */ 280*150812a8SEvalZero __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification 281*150812a8SEvalZero of the corresponding PERM register */ 282*150812a8SEvalZero } SPU_GPIOPORT_Type; /*!< Size = 8 (0x8) */ 283*150812a8SEvalZero 284*150812a8SEvalZero 285*150812a8SEvalZero /** 286*150812a8SEvalZero * @brief SPU_FLASHNSC [FLASHNSC] (Unspecified) 287*150812a8SEvalZero */ 288*150812a8SEvalZero typedef struct { 289*150812a8SEvalZero __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which flash region 290*150812a8SEvalZero can contain the non-secure callable (NSC) 291*150812a8SEvalZero region n */ 292*150812a8SEvalZero __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure 293*150812a8SEvalZero callable (NSC) region n */ 294*150812a8SEvalZero } SPU_FLASHNSC_Type; /*!< Size = 8 (0x8) */ 295*150812a8SEvalZero 296*150812a8SEvalZero 297*150812a8SEvalZero /** 298*150812a8SEvalZero * @brief SPU_RAMNSC [RAMNSC] (Unspecified) 299*150812a8SEvalZero */ 300*150812a8SEvalZero typedef struct { 301*150812a8SEvalZero __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which RAM region 302*150812a8SEvalZero can contain the non-secure callable (NSC) 303*150812a8SEvalZero region n */ 304*150812a8SEvalZero __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure 305*150812a8SEvalZero callable (NSC) region n */ 306*150812a8SEvalZero } SPU_RAMNSC_Type; /*!< Size = 8 (0x8) */ 307*150812a8SEvalZero 308*150812a8SEvalZero 309*150812a8SEvalZero /** 310*150812a8SEvalZero * @brief SPU_FLASHREGION [FLASHREGION] (Unspecified) 311*150812a8SEvalZero */ 312*150812a8SEvalZero typedef struct { 313*150812a8SEvalZero __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for flash 314*150812a8SEvalZero region n */ 315*150812a8SEvalZero } SPU_FLASHREGION_Type; /*!< Size = 4 (0x4) */ 316*150812a8SEvalZero 317*150812a8SEvalZero 318*150812a8SEvalZero /** 319*150812a8SEvalZero * @brief SPU_RAMREGION [RAMREGION] (Unspecified) 320*150812a8SEvalZero */ 321*150812a8SEvalZero typedef struct { 322*150812a8SEvalZero __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for RAM 323*150812a8SEvalZero region n */ 324*150812a8SEvalZero } SPU_RAMREGION_Type; /*!< Size = 4 (0x4) */ 325*150812a8SEvalZero 326*150812a8SEvalZero 327*150812a8SEvalZero /** 328*150812a8SEvalZero * @brief SPU_PERIPHID [PERIPHID] (Unspecified) 329*150812a8SEvalZero */ 330*150812a8SEvalZero typedef struct { 331*150812a8SEvalZero __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: List capabilities and access 332*150812a8SEvalZero permissions for the peripheral with ID n */ 333*150812a8SEvalZero } SPU_PERIPHID_Type; /*!< Size = 4 (0x4) */ 334*150812a8SEvalZero 335*150812a8SEvalZero 336*150812a8SEvalZero /** 337*150812a8SEvalZero * @brief CTRLAPPERI_MAILBOX [MAILBOX] (Unspecified) 338*150812a8SEvalZero */ 339*150812a8SEvalZero typedef struct { 340*150812a8SEvalZero __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU */ 341*150812a8SEvalZero __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) Status to indicate if data sent from the debugger 342*150812a8SEvalZero to the CPU has been read */ 343*150812a8SEvalZero __IM uint32_t RESERVED[30]; 344*150812a8SEvalZero __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger */ 345*150812a8SEvalZero __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) Status to indicate if data sent from the CPU 346*150812a8SEvalZero to the debugger status has been read */ 347*150812a8SEvalZero } CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x88) */ 348*150812a8SEvalZero 349*150812a8SEvalZero 350*150812a8SEvalZero /** 351*150812a8SEvalZero * @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified) 352*150812a8SEvalZero */ 353*150812a8SEvalZero typedef struct { 354*150812a8SEvalZero __IOM uint32_t LOCK; /*!< (@ 0x00000000) Lock ERASEALL mechanism */ 355*150812a8SEvalZero __IOM uint32_t DISABLE; /*!< (@ 0x00000004) Unlock ERASEPROTECT and perform ERASEALL */ 356*150812a8SEvalZero } CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x8) */ 357*150812a8SEvalZero 358*150812a8SEvalZero 359*150812a8SEvalZero /** 360*150812a8SEvalZero * @brief SPIM_PSEL [PSEL] (Unspecified) 361*150812a8SEvalZero */ 362*150812a8SEvalZero typedef struct { 363*150812a8SEvalZero __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 364*150812a8SEvalZero __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 365*150812a8SEvalZero __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 366*150812a8SEvalZero } SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ 367*150812a8SEvalZero 368*150812a8SEvalZero 369*150812a8SEvalZero /** 370*150812a8SEvalZero * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 371*150812a8SEvalZero */ 372*150812a8SEvalZero typedef struct { 373*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 374*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 375*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 376*150812a8SEvalZero __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 377*150812a8SEvalZero } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 378*150812a8SEvalZero 379*150812a8SEvalZero 380*150812a8SEvalZero /** 381*150812a8SEvalZero * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 382*150812a8SEvalZero */ 383*150812a8SEvalZero typedef struct { 384*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 385*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 386*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 387*150812a8SEvalZero __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 388*150812a8SEvalZero } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 389*150812a8SEvalZero 390*150812a8SEvalZero 391*150812a8SEvalZero /** 392*150812a8SEvalZero * @brief SPIS_PSEL [PSEL] (Unspecified) 393*150812a8SEvalZero */ 394*150812a8SEvalZero typedef struct { 395*150812a8SEvalZero __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 396*150812a8SEvalZero __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 397*150812a8SEvalZero __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 398*150812a8SEvalZero __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 399*150812a8SEvalZero } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 400*150812a8SEvalZero 401*150812a8SEvalZero 402*150812a8SEvalZero /** 403*150812a8SEvalZero * @brief SPIS_RXD [RXD] (Unspecified) 404*150812a8SEvalZero */ 405*150812a8SEvalZero typedef struct { 406*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 407*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 408*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 409*150812a8SEvalZero } SPIS_RXD_Type; /*!< Size = 12 (0xc) */ 410*150812a8SEvalZero 411*150812a8SEvalZero 412*150812a8SEvalZero /** 413*150812a8SEvalZero * @brief SPIS_TXD [TXD] (Unspecified) 414*150812a8SEvalZero */ 415*150812a8SEvalZero typedef struct { 416*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 417*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 418*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 419*150812a8SEvalZero } SPIS_TXD_Type; /*!< Size = 12 (0xc) */ 420*150812a8SEvalZero 421*150812a8SEvalZero 422*150812a8SEvalZero /** 423*150812a8SEvalZero * @brief TWIM_PSEL [PSEL] (Unspecified) 424*150812a8SEvalZero */ 425*150812a8SEvalZero typedef struct { 426*150812a8SEvalZero __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 427*150812a8SEvalZero __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 428*150812a8SEvalZero } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 429*150812a8SEvalZero 430*150812a8SEvalZero 431*150812a8SEvalZero /** 432*150812a8SEvalZero * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 433*150812a8SEvalZero */ 434*150812a8SEvalZero typedef struct { 435*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 436*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 437*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 438*150812a8SEvalZero __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 439*150812a8SEvalZero } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 440*150812a8SEvalZero 441*150812a8SEvalZero 442*150812a8SEvalZero /** 443*150812a8SEvalZero * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 444*150812a8SEvalZero */ 445*150812a8SEvalZero typedef struct { 446*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 447*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 448*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 449*150812a8SEvalZero __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 450*150812a8SEvalZero } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 451*150812a8SEvalZero 452*150812a8SEvalZero 453*150812a8SEvalZero /** 454*150812a8SEvalZero * @brief TWIS_PSEL [PSEL] (Unspecified) 455*150812a8SEvalZero */ 456*150812a8SEvalZero typedef struct { 457*150812a8SEvalZero __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 458*150812a8SEvalZero __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 459*150812a8SEvalZero } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 460*150812a8SEvalZero 461*150812a8SEvalZero 462*150812a8SEvalZero /** 463*150812a8SEvalZero * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 464*150812a8SEvalZero */ 465*150812a8SEvalZero typedef struct { 466*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 467*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 468*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 469*150812a8SEvalZero } TWIS_RXD_Type; /*!< Size = 12 (0xc) */ 470*150812a8SEvalZero 471*150812a8SEvalZero 472*150812a8SEvalZero /** 473*150812a8SEvalZero * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 474*150812a8SEvalZero */ 475*150812a8SEvalZero typedef struct { 476*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 477*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 478*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 479*150812a8SEvalZero } TWIS_TXD_Type; /*!< Size = 12 (0xc) */ 480*150812a8SEvalZero 481*150812a8SEvalZero 482*150812a8SEvalZero /** 483*150812a8SEvalZero * @brief UARTE_PSEL [PSEL] (Unspecified) 484*150812a8SEvalZero */ 485*150812a8SEvalZero typedef struct { 486*150812a8SEvalZero __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 487*150812a8SEvalZero __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 488*150812a8SEvalZero __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 489*150812a8SEvalZero __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 490*150812a8SEvalZero } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 491*150812a8SEvalZero 492*150812a8SEvalZero 493*150812a8SEvalZero /** 494*150812a8SEvalZero * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 495*150812a8SEvalZero */ 496*150812a8SEvalZero typedef struct { 497*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 498*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 499*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 500*150812a8SEvalZero } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 501*150812a8SEvalZero 502*150812a8SEvalZero 503*150812a8SEvalZero /** 504*150812a8SEvalZero * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 505*150812a8SEvalZero */ 506*150812a8SEvalZero typedef struct { 507*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 508*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 509*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 510*150812a8SEvalZero } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 511*150812a8SEvalZero 512*150812a8SEvalZero 513*150812a8SEvalZero /** 514*150812a8SEvalZero * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) 515*150812a8SEvalZero */ 516*150812a8SEvalZero typedef struct { 517*150812a8SEvalZero __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or 518*150812a8SEvalZero above CH[n].LIMIT.HIGH */ 519*150812a8SEvalZero __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or 520*150812a8SEvalZero below CH[n].LIMIT.LOW */ 521*150812a8SEvalZero } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 522*150812a8SEvalZero 523*150812a8SEvalZero 524*150812a8SEvalZero /** 525*150812a8SEvalZero * @brief SAADC_PUBLISH_CH [PUBLISH_CH] (Publish configuration for events) 526*150812a8SEvalZero */ 527*150812a8SEvalZero typedef struct { 528*150812a8SEvalZero __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Publish configuration for 529*150812a8SEvalZero event CH[n].LIMITH */ 530*150812a8SEvalZero __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Publish configuration for 531*150812a8SEvalZero event CH[n].LIMITL */ 532*150812a8SEvalZero } SAADC_PUBLISH_CH_Type; /*!< Size = 8 (0x8) */ 533*150812a8SEvalZero 534*150812a8SEvalZero 535*150812a8SEvalZero /** 536*150812a8SEvalZero * @brief SAADC_CH [CH] (Unspecified) 537*150812a8SEvalZero */ 538*150812a8SEvalZero typedef struct { 539*150812a8SEvalZero __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection 540*150812a8SEvalZero for CH[n] */ 541*150812a8SEvalZero __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection 542*150812a8SEvalZero for CH[n] */ 543*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for 544*150812a8SEvalZero CH[n] */ 545*150812a8SEvalZero __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event 546*150812a8SEvalZero monitoring a channel */ 547*150812a8SEvalZero } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 548*150812a8SEvalZero 549*150812a8SEvalZero 550*150812a8SEvalZero /** 551*150812a8SEvalZero * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 552*150812a8SEvalZero */ 553*150812a8SEvalZero typedef struct { 554*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 555*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 556*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last 557*150812a8SEvalZero START */ 558*150812a8SEvalZero } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 559*150812a8SEvalZero 560*150812a8SEvalZero 561*150812a8SEvalZero /** 562*150812a8SEvalZero * @brief DPPIC_TASKS_CHG [TASKS_CHG] (Channel group tasks) 563*150812a8SEvalZero */ 564*150812a8SEvalZero typedef struct { 565*150812a8SEvalZero __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 566*150812a8SEvalZero __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 567*150812a8SEvalZero } DPPIC_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 568*150812a8SEvalZero 569*150812a8SEvalZero 570*150812a8SEvalZero /** 571*150812a8SEvalZero * @brief DPPIC_SUBSCRIBE_CHG [SUBSCRIBE_CHG] (Subscribe configuration for tasks) 572*150812a8SEvalZero */ 573*150812a8SEvalZero typedef struct { 574*150812a8SEvalZero __IOM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Subscribe configuration 575*150812a8SEvalZero for task CHG[n].EN */ 576*150812a8SEvalZero __IOM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Subscribe configuration 577*150812a8SEvalZero for task CHG[n].DIS */ 578*150812a8SEvalZero } DPPIC_SUBSCRIBE_CHG_Type; /*!< Size = 8 (0x8) */ 579*150812a8SEvalZero 580*150812a8SEvalZero 581*150812a8SEvalZero /** 582*150812a8SEvalZero * @brief PWM_SEQ [SEQ] (Unspecified) 583*150812a8SEvalZero */ 584*150812a8SEvalZero typedef struct { 585*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM 586*150812a8SEvalZero of this sequence */ 587*150812a8SEvalZero __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) 588*150812a8SEvalZero in this sequence */ 589*150812a8SEvalZero __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM 590*150812a8SEvalZero periods between samples loaded into compare 591*150812a8SEvalZero register */ 592*150812a8SEvalZero __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ 593*150812a8SEvalZero __IM uint32_t RESERVED[4]; 594*150812a8SEvalZero } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 595*150812a8SEvalZero 596*150812a8SEvalZero 597*150812a8SEvalZero /** 598*150812a8SEvalZero * @brief PWM_PSEL [PSEL] (Unspecified) 599*150812a8SEvalZero */ 600*150812a8SEvalZero typedef struct { 601*150812a8SEvalZero __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for 602*150812a8SEvalZero PWM channel n */ 603*150812a8SEvalZero } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 604*150812a8SEvalZero 605*150812a8SEvalZero 606*150812a8SEvalZero /** 607*150812a8SEvalZero * @brief PDM_PSEL [PSEL] (Unspecified) 608*150812a8SEvalZero */ 609*150812a8SEvalZero typedef struct { 610*150812a8SEvalZero __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 611*150812a8SEvalZero __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 612*150812a8SEvalZero } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 613*150812a8SEvalZero 614*150812a8SEvalZero 615*150812a8SEvalZero /** 616*150812a8SEvalZero * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 617*150812a8SEvalZero */ 618*150812a8SEvalZero typedef struct { 619*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 620*150812a8SEvalZero EasyDMA */ 621*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 622*150812a8SEvalZero mode */ 623*150812a8SEvalZero } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 624*150812a8SEvalZero 625*150812a8SEvalZero 626*150812a8SEvalZero /** 627*150812a8SEvalZero * @brief I2S_CONFIG [CONFIG] (Unspecified) 628*150812a8SEvalZero */ 629*150812a8SEvalZero typedef struct { 630*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ 631*150812a8SEvalZero __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ 632*150812a8SEvalZero __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ 633*150812a8SEvalZero __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ 634*150812a8SEvalZero __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ 635*150812a8SEvalZero __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ 636*150812a8SEvalZero __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ 637*150812a8SEvalZero __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ 638*150812a8SEvalZero __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ 639*150812a8SEvalZero __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ 640*150812a8SEvalZero } I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ 641*150812a8SEvalZero 642*150812a8SEvalZero 643*150812a8SEvalZero /** 644*150812a8SEvalZero * @brief I2S_RXD [RXD] (Unspecified) 645*150812a8SEvalZero */ 646*150812a8SEvalZero typedef struct { 647*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ 648*150812a8SEvalZero } I2S_RXD_Type; /*!< Size = 4 (0x4) */ 649*150812a8SEvalZero 650*150812a8SEvalZero 651*150812a8SEvalZero /** 652*150812a8SEvalZero * @brief I2S_TXD [TXD] (Unspecified) 653*150812a8SEvalZero */ 654*150812a8SEvalZero typedef struct { 655*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ 656*150812a8SEvalZero } I2S_TXD_Type; /*!< Size = 4 (0x4) */ 657*150812a8SEvalZero 658*150812a8SEvalZero 659*150812a8SEvalZero /** 660*150812a8SEvalZero * @brief I2S_RXTXD [RXTXD] (Unspecified) 661*150812a8SEvalZero */ 662*150812a8SEvalZero typedef struct { 663*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ 664*150812a8SEvalZero } I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ 665*150812a8SEvalZero 666*150812a8SEvalZero 667*150812a8SEvalZero /** 668*150812a8SEvalZero * @brief I2S_PSEL [PSEL] (Unspecified) 669*150812a8SEvalZero */ 670*150812a8SEvalZero typedef struct { 671*150812a8SEvalZero __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ 672*150812a8SEvalZero __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ 673*150812a8SEvalZero __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ 674*150812a8SEvalZero __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ 675*150812a8SEvalZero __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ 676*150812a8SEvalZero } I2S_PSEL_Type; /*!< Size = 20 (0x14) */ 677*150812a8SEvalZero 678*150812a8SEvalZero 679*150812a8SEvalZero /** 680*150812a8SEvalZero * @brief VMC_RAM [RAM] (Unspecified) 681*150812a8SEvalZero */ 682*150812a8SEvalZero typedef struct { 683*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ 684*150812a8SEvalZero __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ 685*150812a8SEvalZero __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear 686*150812a8SEvalZero register */ 687*150812a8SEvalZero __IM uint32_t RESERVED; 688*150812a8SEvalZero } VMC_RAM_Type; /*!< Size = 16 (0x10) */ 689*150812a8SEvalZero 690*150812a8SEvalZero 691*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_clusters */ 692*150812a8SEvalZero 693*150812a8SEvalZero 694*150812a8SEvalZero /* =========================================================================================================================== */ 695*150812a8SEvalZero /* ================ Device Specific Peripheral Section ================ */ 696*150812a8SEvalZero /* =========================================================================================================================== */ 697*150812a8SEvalZero 698*150812a8SEvalZero 699*150812a8SEvalZero /** @addtogroup Device_Peripheral_peripherals 700*150812a8SEvalZero * @{ 701*150812a8SEvalZero */ 702*150812a8SEvalZero 703*150812a8SEvalZero 704*150812a8SEvalZero 705*150812a8SEvalZero /* =========================================================================================================================== */ 706*150812a8SEvalZero /* ================ FICR_S ================ */ 707*150812a8SEvalZero /* =========================================================================================================================== */ 708*150812a8SEvalZero 709*150812a8SEvalZero 710*150812a8SEvalZero /** 711*150812a8SEvalZero * @brief Factory Information Configuration Registers (FICR_S) 712*150812a8SEvalZero */ 713*150812a8SEvalZero 714*150812a8SEvalZero typedef struct { /*!< (@ 0x00FF0000) FICR_S Structure */ 715*150812a8SEvalZero __IM uint32_t RESERVED[128]; 716*150812a8SEvalZero __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */ 717*150812a8SEvalZero __IM uint32_t RESERVED1[53]; 718*150812a8SEvalZero __IOM FICR_TRIMCNF_Type TRIMCNF[256]; /*!< (@ 0x00000300) Unspecified */ 719*150812a8SEvalZero __IM uint32_t RESERVED2[64]; 720*150812a8SEvalZero __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ 721*150812a8SEvalZero } NRF_FICR_Type; /*!< Size = 3104 (0xc20) */ 722*150812a8SEvalZero 723*150812a8SEvalZero 724*150812a8SEvalZero 725*150812a8SEvalZero /* =========================================================================================================================== */ 726*150812a8SEvalZero /* ================ UICR_S ================ */ 727*150812a8SEvalZero /* =========================================================================================================================== */ 728*150812a8SEvalZero 729*150812a8SEvalZero 730*150812a8SEvalZero /** 731*150812a8SEvalZero * @brief User information configuration registers User information configuration registers (UICR_S) 732*150812a8SEvalZero */ 733*150812a8SEvalZero 734*150812a8SEvalZero typedef struct { /*!< (@ 0x00FF8000) UICR_S Structure */ 735*150812a8SEvalZero __IOM uint32_t APPROTECT; /*!< (@ 0x00000000) Access port protection */ 736*150812a8SEvalZero __IM uint32_t RESERVED[4]; 737*150812a8SEvalZero __IOM uint32_t XOSC32M; /*!< (@ 0x00000014) Oscillator control */ 738*150812a8SEvalZero __IM uint32_t RESERVED1; 739*150812a8SEvalZero __IOM uint32_t HFXOSRC; /*!< (@ 0x0000001C) HFXO clock source selection */ 740*150812a8SEvalZero __IOM uint32_t HFXOCNT; /*!< (@ 0x00000020) HFXO startup counter */ 741*150812a8SEvalZero __IM uint32_t RESERVED2[2]; 742*150812a8SEvalZero __IOM uint32_t SECUREAPPROTECT; /*!< (@ 0x0000002C) Secure access port protection */ 743*150812a8SEvalZero __IOM uint32_t ERASEPROTECT; /*!< (@ 0x00000030) Erase protection */ 744*150812a8SEvalZero __IM uint32_t RESERVED3[53]; 745*150812a8SEvalZero __IOM uint32_t OTP[190]; /*!< (@ 0x00000108) Description collection: OTP bits [31+n*32:0+n*32]. */ 746*150812a8SEvalZero __IOM UICR_KEYSLOT_Type KEYSLOT; /*!< (@ 0x00000400) Unspecified */ 747*150812a8SEvalZero } NRF_UICR_Type; /*!< Size = 4096 (0x1000) */ 748*150812a8SEvalZero 749*150812a8SEvalZero 750*150812a8SEvalZero 751*150812a8SEvalZero /* =========================================================================================================================== */ 752*150812a8SEvalZero /* ================ TAD_S ================ */ 753*150812a8SEvalZero /* =========================================================================================================================== */ 754*150812a8SEvalZero 755*150812a8SEvalZero 756*150812a8SEvalZero /** 757*150812a8SEvalZero * @brief Trace and debug control (TAD_S) 758*150812a8SEvalZero */ 759*150812a8SEvalZero 760*150812a8SEvalZero typedef struct { /*!< (@ 0xE0080000) TAD_S Structure */ 761*150812a8SEvalZero __IM uint32_t RESERVED[320]; 762*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable debug domain and aquire selected GPIOs */ 763*150812a8SEvalZero __IOM TAD_PSEL_Type PSEL; /*!< (@ 0x00000504) Unspecified */ 764*150812a8SEvalZero __IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface */ 765*150812a8SEvalZero } NRF_TAD_Type; /*!< Size = 1308 (0x51c) */ 766*150812a8SEvalZero 767*150812a8SEvalZero 768*150812a8SEvalZero 769*150812a8SEvalZero /* =========================================================================================================================== */ 770*150812a8SEvalZero /* ================ SPU_S ================ */ 771*150812a8SEvalZero /* =========================================================================================================================== */ 772*150812a8SEvalZero 773*150812a8SEvalZero 774*150812a8SEvalZero /** 775*150812a8SEvalZero * @brief System protection unit (SPU_S) 776*150812a8SEvalZero */ 777*150812a8SEvalZero 778*150812a8SEvalZero typedef struct { /*!< (@ 0x50003000) SPU_S Structure */ 779*150812a8SEvalZero __IM uint32_t RESERVED[64]; 780*150812a8SEvalZero __IOM uint32_t EVENTS_RAMACCERR; /*!< (@ 0x00000100) A security violation has been detected for the 781*150812a8SEvalZero RAM memory space */ 782*150812a8SEvalZero __IOM uint32_t EVENTS_FLASHACCERR; /*!< (@ 0x00000104) A security violation has been detected for the 783*150812a8SEvalZero flash memory space */ 784*150812a8SEvalZero __IOM uint32_t EVENTS_PERIPHACCERR; /*!< (@ 0x00000108) A security violation has been detected on one 785*150812a8SEvalZero or several peripherals */ 786*150812a8SEvalZero __IM uint32_t RESERVED1[29]; 787*150812a8SEvalZero __IOM uint32_t PUBLISH_RAMACCERR; /*!< (@ 0x00000180) Publish configuration for event RAMACCERR */ 788*150812a8SEvalZero __IOM uint32_t PUBLISH_FLASHACCERR; /*!< (@ 0x00000184) Publish configuration for event FLASHACCERR */ 789*150812a8SEvalZero __IOM uint32_t PUBLISH_PERIPHACCERR; /*!< (@ 0x00000188) Publish configuration for event PERIPHACCERR */ 790*150812a8SEvalZero __IM uint32_t RESERVED2[93]; 791*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 792*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 793*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 794*150812a8SEvalZero __IM uint32_t RESERVED3[61]; 795*150812a8SEvalZero __IM uint32_t CAP; /*!< (@ 0x00000400) Show implemented features for the current device */ 796*150812a8SEvalZero __IM uint32_t RESERVED4[15]; 797*150812a8SEvalZero __IOM SPU_EXTDOMAIN_Type EXTDOMAIN[1]; /*!< (@ 0x00000440) Unspecified */ 798*150812a8SEvalZero __IM uint32_t RESERVED5[15]; 799*150812a8SEvalZero __IOM SPU_DPPI_Type DPPI[1]; /*!< (@ 0x00000480) Unspecified */ 800*150812a8SEvalZero __IM uint32_t RESERVED6[14]; 801*150812a8SEvalZero __IOM SPU_GPIOPORT_Type GPIOPORT[1]; /*!< (@ 0x000004C0) Unspecified */ 802*150812a8SEvalZero __IM uint32_t RESERVED7[14]; 803*150812a8SEvalZero __IOM SPU_FLASHNSC_Type FLASHNSC[2]; /*!< (@ 0x00000500) Unspecified */ 804*150812a8SEvalZero __IM uint32_t RESERVED8[12]; 805*150812a8SEvalZero __IOM SPU_RAMNSC_Type RAMNSC[2]; /*!< (@ 0x00000540) Unspecified */ 806*150812a8SEvalZero __IM uint32_t RESERVED9[44]; 807*150812a8SEvalZero __IOM SPU_FLASHREGION_Type FLASHREGION[32]; /*!< (@ 0x00000600) Unspecified */ 808*150812a8SEvalZero __IM uint32_t RESERVED10[32]; 809*150812a8SEvalZero __IOM SPU_RAMREGION_Type RAMREGION[32]; /*!< (@ 0x00000700) Unspecified */ 810*150812a8SEvalZero __IM uint32_t RESERVED11[32]; 811*150812a8SEvalZero __IOM SPU_PERIPHID_Type PERIPHID[67]; /*!< (@ 0x00000800) Unspecified */ 812*150812a8SEvalZero } NRF_SPU_Type; /*!< Size = 2316 (0x90c) */ 813*150812a8SEvalZero 814*150812a8SEvalZero 815*150812a8SEvalZero 816*150812a8SEvalZero /* =========================================================================================================================== */ 817*150812a8SEvalZero /* ================ REGULATORS_NS ================ */ 818*150812a8SEvalZero /* =========================================================================================================================== */ 819*150812a8SEvalZero 820*150812a8SEvalZero 821*150812a8SEvalZero /** 822*150812a8SEvalZero * @brief Voltage regulators control 0 (REGULATORS_NS) 823*150812a8SEvalZero */ 824*150812a8SEvalZero 825*150812a8SEvalZero typedef struct { /*!< (@ 0x40004000) REGULATORS_NS Structure */ 826*150812a8SEvalZero __IM uint32_t RESERVED[320]; 827*150812a8SEvalZero __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 828*150812a8SEvalZero __IM uint32_t RESERVED1[3]; 829*150812a8SEvalZero __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power-fail comparator configuration */ 830*150812a8SEvalZero __IM uint32_t RESERVED2[25]; 831*150812a8SEvalZero __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC mode of the main voltage regulator */ 832*150812a8SEvalZero } NRF_REGULATORS_Type; /*!< Size = 1404 (0x57c) */ 833*150812a8SEvalZero 834*150812a8SEvalZero 835*150812a8SEvalZero 836*150812a8SEvalZero /* =========================================================================================================================== */ 837*150812a8SEvalZero /* ================ CLOCK_NS ================ */ 838*150812a8SEvalZero /* =========================================================================================================================== */ 839*150812a8SEvalZero 840*150812a8SEvalZero 841*150812a8SEvalZero /** 842*150812a8SEvalZero * @brief Clock management 0 (CLOCK_NS) 843*150812a8SEvalZero */ 844*150812a8SEvalZero 845*150812a8SEvalZero typedef struct { /*!< (@ 0x40005000) CLOCK_NS Structure */ 846*150812a8SEvalZero __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */ 847*150812a8SEvalZero __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */ 848*150812a8SEvalZero __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ 849*150812a8SEvalZero __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 850*150812a8SEvalZero __IM uint32_t RESERVED[28]; 851*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_HFCLKSTART; /*!< (@ 0x00000080) Subscribe configuration for task HFCLKSTART */ 852*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_HFCLKSTOP; /*!< (@ 0x00000084) Subscribe configuration for task HFCLKSTOP */ 853*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_LFCLKSTART; /*!< (@ 0x00000088) Subscribe configuration for task LFCLKSTART */ 854*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_LFCLKSTOP; /*!< (@ 0x0000008C) Subscribe configuration for task LFCLKSTOP */ 855*150812a8SEvalZero __IM uint32_t RESERVED1[28]; 856*150812a8SEvalZero __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ 857*150812a8SEvalZero __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 858*150812a8SEvalZero __IM uint32_t RESERVED2[30]; 859*150812a8SEvalZero __IOM uint32_t PUBLISH_HFCLKSTARTED; /*!< (@ 0x00000180) Publish configuration for event HFCLKSTARTED */ 860*150812a8SEvalZero __IOM uint32_t PUBLISH_LFCLKSTARTED; /*!< (@ 0x00000184) Publish configuration for event LFCLKSTARTED */ 861*150812a8SEvalZero __IM uint32_t RESERVED3[94]; 862*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 863*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 864*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 865*150812a8SEvalZero __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 866*150812a8SEvalZero __IM uint32_t RESERVED4[62]; 867*150812a8SEvalZero __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 868*150812a8SEvalZero triggered */ 869*150812a8SEvalZero __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) The register shows if HFXO has been requested 870*150812a8SEvalZero by triggering HFCLKSTART task and if it 871*150812a8SEvalZero has been started (STATE) */ 872*150812a8SEvalZero __IM uint32_t RESERVED5; 873*150812a8SEvalZero __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 874*150812a8SEvalZero triggered */ 875*150812a8SEvalZero __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) The register shows which LFCLK source has been 876*150812a8SEvalZero requested (SRC) when triggering LFCLKSTART 877*150812a8SEvalZero task and if the source has been started 878*150812a8SEvalZero (STATE) */ 879*150812a8SEvalZero __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set after LFCLKSTART 880*150812a8SEvalZero task has been triggered */ 881*150812a8SEvalZero __IM uint32_t RESERVED6[62]; 882*150812a8SEvalZero __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK. LFCLKSTART task starts 883*150812a8SEvalZero starts a clock source selected with this 884*150812a8SEvalZero register. */ 885*150812a8SEvalZero } NRF_CLOCK_Type; /*!< Size = 1308 (0x51c) */ 886*150812a8SEvalZero 887*150812a8SEvalZero 888*150812a8SEvalZero 889*150812a8SEvalZero /* =========================================================================================================================== */ 890*150812a8SEvalZero /* ================ POWER_NS ================ */ 891*150812a8SEvalZero /* =========================================================================================================================== */ 892*150812a8SEvalZero 893*150812a8SEvalZero 894*150812a8SEvalZero /** 895*150812a8SEvalZero * @brief Power control 0 (POWER_NS) 896*150812a8SEvalZero */ 897*150812a8SEvalZero 898*150812a8SEvalZero typedef struct { /*!< (@ 0x40005000) POWER_NS Structure */ 899*150812a8SEvalZero __IM uint32_t RESERVED[30]; 900*150812a8SEvalZero __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode. */ 901*150812a8SEvalZero __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ 902*150812a8SEvalZero __IM uint32_t RESERVED1[30]; 903*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_CONSTLAT; /*!< (@ 0x000000F8) Subscribe configuration for task CONSTLAT */ 904*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_LOWPWR; /*!< (@ 0x000000FC) Subscribe configuration for task LOWPWR */ 905*150812a8SEvalZero __IM uint32_t RESERVED2[2]; 906*150812a8SEvalZero __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 907*150812a8SEvalZero __IM uint32_t RESERVED3[2]; 908*150812a8SEvalZero __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 909*150812a8SEvalZero __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 910*150812a8SEvalZero __IM uint32_t RESERVED4[27]; 911*150812a8SEvalZero __IOM uint32_t PUBLISH_POFWARN; /*!< (@ 0x00000188) Publish configuration for event POFWARN */ 912*150812a8SEvalZero __IM uint32_t RESERVED5[2]; 913*150812a8SEvalZero __IOM uint32_t PUBLISH_SLEEPENTER; /*!< (@ 0x00000194) Publish configuration for event SLEEPENTER */ 914*150812a8SEvalZero __IOM uint32_t PUBLISH_SLEEPEXIT; /*!< (@ 0x00000198) Publish configuration for event SLEEPEXIT */ 915*150812a8SEvalZero __IM uint32_t RESERVED6[89]; 916*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 917*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 918*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 919*150812a8SEvalZero __IM uint32_t RESERVED7[61]; 920*150812a8SEvalZero __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 921*150812a8SEvalZero __IM uint32_t RESERVED8[15]; 922*150812a8SEvalZero __IM uint32_t POWERSTATUS; /*!< (@ 0x00000440) Modem domain power status */ 923*150812a8SEvalZero __IM uint32_t RESERVED9[54]; 924*150812a8SEvalZero __IOM uint32_t GPREGRET[2]; /*!< (@ 0x0000051C) Description collection: General purpose retention 925*150812a8SEvalZero register */ 926*150812a8SEvalZero } NRF_POWER_Type; /*!< Size = 1316 (0x524) */ 927*150812a8SEvalZero 928*150812a8SEvalZero 929*150812a8SEvalZero 930*150812a8SEvalZero /* =========================================================================================================================== */ 931*150812a8SEvalZero /* ================ CTRL_AP_PERI_S ================ */ 932*150812a8SEvalZero /* =========================================================================================================================== */ 933*150812a8SEvalZero 934*150812a8SEvalZero 935*150812a8SEvalZero /** 936*150812a8SEvalZero * @brief Control access port (CTRL_AP_PERI_S) 937*150812a8SEvalZero */ 938*150812a8SEvalZero 939*150812a8SEvalZero typedef struct { /*!< (@ 0x50006000) CTRL_AP_PERI_S Structure */ 940*150812a8SEvalZero __IM uint32_t RESERVED[256]; 941*150812a8SEvalZero __IOM CTRLAPPERI_MAILBOX_Type MAILBOX; /*!< (@ 0x00000400) Unspecified */ 942*150812a8SEvalZero __IM uint32_t RESERVED1[30]; 943*150812a8SEvalZero __IOM CTRLAPPERI_ERASEPROTECT_Type ERASEPROTECT;/*!< (@ 0x00000500) Unspecified */ 944*150812a8SEvalZero } NRF_CTRLAPPERI_Type; /*!< Size = 1288 (0x508) */ 945*150812a8SEvalZero 946*150812a8SEvalZero 947*150812a8SEvalZero 948*150812a8SEvalZero /* =========================================================================================================================== */ 949*150812a8SEvalZero /* ================ SPIM0_NS ================ */ 950*150812a8SEvalZero /* =========================================================================================================================== */ 951*150812a8SEvalZero 952*150812a8SEvalZero 953*150812a8SEvalZero /** 954*150812a8SEvalZero * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0_NS) 955*150812a8SEvalZero */ 956*150812a8SEvalZero 957*150812a8SEvalZero typedef struct { /*!< (@ 0x40008000) SPIM0_NS Structure */ 958*150812a8SEvalZero __IM uint32_t RESERVED[4]; 959*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 960*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 961*150812a8SEvalZero __IM uint32_t RESERVED1; 962*150812a8SEvalZero __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 963*150812a8SEvalZero __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 964*150812a8SEvalZero __IM uint32_t RESERVED2[27]; 965*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000090) Subscribe configuration for task START */ 966*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 967*150812a8SEvalZero __IM uint32_t RESERVED3; 968*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 969*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 970*150812a8SEvalZero __IM uint32_t RESERVED4[24]; 971*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 972*150812a8SEvalZero __IM uint32_t RESERVED5[2]; 973*150812a8SEvalZero __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 974*150812a8SEvalZero __IM uint32_t RESERVED6; 975*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 976*150812a8SEvalZero __IM uint32_t RESERVED7; 977*150812a8SEvalZero __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 978*150812a8SEvalZero __IM uint32_t RESERVED8[10]; 979*150812a8SEvalZero __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 980*150812a8SEvalZero __IM uint32_t RESERVED9[13]; 981*150812a8SEvalZero __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 982*150812a8SEvalZero __IM uint32_t RESERVED10[2]; 983*150812a8SEvalZero __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 984*150812a8SEvalZero __IM uint32_t RESERVED11; 985*150812a8SEvalZero __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000198) Publish configuration for event END */ 986*150812a8SEvalZero __IM uint32_t RESERVED12; 987*150812a8SEvalZero __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 988*150812a8SEvalZero __IM uint32_t RESERVED13[10]; 989*150812a8SEvalZero __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x000001CC) Publish configuration for event STARTED */ 990*150812a8SEvalZero __IM uint32_t RESERVED14[12]; 991*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 992*150812a8SEvalZero __IM uint32_t RESERVED15[64]; 993*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 994*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 995*150812a8SEvalZero __IM uint32_t RESERVED16[125]; 996*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 997*150812a8SEvalZero __IM uint32_t RESERVED17; 998*150812a8SEvalZero __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 999*150812a8SEvalZero __IM uint32_t RESERVED18[4]; 1000*150812a8SEvalZero __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1001*150812a8SEvalZero source selected. */ 1002*150812a8SEvalZero __IM uint32_t RESERVED19[3]; 1003*150812a8SEvalZero __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1004*150812a8SEvalZero __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1005*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1006*150812a8SEvalZero __IM uint32_t RESERVED20[26]; 1007*150812a8SEvalZero __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in 1008*150812a8SEvalZero case and over-read of the TXD buffer. */ 1009*150812a8SEvalZero } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1010*150812a8SEvalZero 1011*150812a8SEvalZero 1012*150812a8SEvalZero 1013*150812a8SEvalZero /* =========================================================================================================================== */ 1014*150812a8SEvalZero /* ================ SPIS0_NS ================ */ 1015*150812a8SEvalZero /* =========================================================================================================================== */ 1016*150812a8SEvalZero 1017*150812a8SEvalZero 1018*150812a8SEvalZero /** 1019*150812a8SEvalZero * @brief SPI Slave 0 (SPIS0_NS) 1020*150812a8SEvalZero */ 1021*150812a8SEvalZero 1022*150812a8SEvalZero typedef struct { /*!< (@ 0x40008000) SPIS0_NS Structure */ 1023*150812a8SEvalZero __IM uint32_t RESERVED[9]; 1024*150812a8SEvalZero __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1025*150812a8SEvalZero __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1026*150812a8SEvalZero to acquire it */ 1027*150812a8SEvalZero __IM uint32_t RESERVED1[30]; 1028*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_ACQUIRE; /*!< (@ 0x000000A4) Subscribe configuration for task ACQUIRE */ 1029*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_RELEASE; /*!< (@ 0x000000A8) Subscribe configuration for task RELEASE */ 1030*150812a8SEvalZero __IM uint32_t RESERVED2[22]; 1031*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1032*150812a8SEvalZero __IM uint32_t RESERVED3[2]; 1033*150812a8SEvalZero __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1034*150812a8SEvalZero __IM uint32_t RESERVED4[5]; 1035*150812a8SEvalZero __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1036*150812a8SEvalZero __IM uint32_t RESERVED5[22]; 1037*150812a8SEvalZero __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 1038*150812a8SEvalZero __IM uint32_t RESERVED6[2]; 1039*150812a8SEvalZero __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1040*150812a8SEvalZero __IM uint32_t RESERVED7[5]; 1041*150812a8SEvalZero __IOM uint32_t PUBLISH_ACQUIRED; /*!< (@ 0x000001A8) Publish configuration for event ACQUIRED */ 1042*150812a8SEvalZero __IM uint32_t RESERVED8[21]; 1043*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1044*150812a8SEvalZero __IM uint32_t RESERVED9[64]; 1045*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1046*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1047*150812a8SEvalZero __IM uint32_t RESERVED10[61]; 1048*150812a8SEvalZero __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1049*150812a8SEvalZero __IM uint32_t RESERVED11[15]; 1050*150812a8SEvalZero __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1051*150812a8SEvalZero __IM uint32_t RESERVED12[47]; 1052*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1053*150812a8SEvalZero __IM uint32_t RESERVED13; 1054*150812a8SEvalZero __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1055*150812a8SEvalZero __IM uint32_t RESERVED14[7]; 1056*150812a8SEvalZero __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1057*150812a8SEvalZero __IM uint32_t RESERVED15; 1058*150812a8SEvalZero __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1059*150812a8SEvalZero __IM uint32_t RESERVED16; 1060*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1061*150812a8SEvalZero __IM uint32_t RESERVED17; 1062*150812a8SEvalZero __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1063*150812a8SEvalZero of an ignored transaction. */ 1064*150812a8SEvalZero __IM uint32_t RESERVED18[24]; 1065*150812a8SEvalZero __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1066*150812a8SEvalZero } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1067*150812a8SEvalZero 1068*150812a8SEvalZero 1069*150812a8SEvalZero 1070*150812a8SEvalZero /* =========================================================================================================================== */ 1071*150812a8SEvalZero /* ================ TWIM0_NS ================ */ 1072*150812a8SEvalZero /* =========================================================================================================================== */ 1073*150812a8SEvalZero 1074*150812a8SEvalZero 1075*150812a8SEvalZero /** 1076*150812a8SEvalZero * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0_NS) 1077*150812a8SEvalZero */ 1078*150812a8SEvalZero 1079*150812a8SEvalZero typedef struct { /*!< (@ 0x40008000) TWIM0_NS Structure */ 1080*150812a8SEvalZero __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1081*150812a8SEvalZero __IM uint32_t RESERVED; 1082*150812a8SEvalZero __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1083*150812a8SEvalZero __IM uint32_t RESERVED1[2]; 1084*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1085*150812a8SEvalZero TWI master is not suspended. */ 1086*150812a8SEvalZero __IM uint32_t RESERVED2; 1087*150812a8SEvalZero __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1088*150812a8SEvalZero __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1089*150812a8SEvalZero __IM uint32_t RESERVED3[23]; 1090*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1091*150812a8SEvalZero __IM uint32_t RESERVED4; 1092*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1093*150812a8SEvalZero __IM uint32_t RESERVED5[2]; 1094*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1095*150812a8SEvalZero __IM uint32_t RESERVED6; 1096*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1097*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1098*150812a8SEvalZero __IM uint32_t RESERVED7[24]; 1099*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1100*150812a8SEvalZero __IM uint32_t RESERVED8[7]; 1101*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1102*150812a8SEvalZero __IM uint32_t RESERVED9[8]; 1103*150812a8SEvalZero __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND 1104*150812a8SEvalZero task has been issued, TWI traffic is now 1105*150812a8SEvalZero suspended. */ 1106*150812a8SEvalZero __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1107*150812a8SEvalZero __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1108*150812a8SEvalZero __IM uint32_t RESERVED10[2]; 1109*150812a8SEvalZero __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1110*150812a8SEvalZero __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1111*150812a8SEvalZero byte */ 1112*150812a8SEvalZero __IM uint32_t RESERVED11[8]; 1113*150812a8SEvalZero __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1114*150812a8SEvalZero __IM uint32_t RESERVED12[7]; 1115*150812a8SEvalZero __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1116*150812a8SEvalZero __IM uint32_t RESERVED13[8]; 1117*150812a8SEvalZero __IOM uint32_t PUBLISH_SUSPENDED; /*!< (@ 0x000001C8) Publish configuration for event SUSPENDED */ 1118*150812a8SEvalZero __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1119*150812a8SEvalZero __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1120*150812a8SEvalZero __IM uint32_t RESERVED14[2]; 1121*150812a8SEvalZero __IOM uint32_t PUBLISH_LASTRX; /*!< (@ 0x000001DC) Publish configuration for event LASTRX */ 1122*150812a8SEvalZero __IOM uint32_t PUBLISH_LASTTX; /*!< (@ 0x000001E0) Publish configuration for event LASTTX */ 1123*150812a8SEvalZero __IM uint32_t RESERVED15[7]; 1124*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1125*150812a8SEvalZero __IM uint32_t RESERVED16[63]; 1126*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1127*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1128*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1129*150812a8SEvalZero __IM uint32_t RESERVED17[110]; 1130*150812a8SEvalZero __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1131*150812a8SEvalZero __IM uint32_t RESERVED18[14]; 1132*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1133*150812a8SEvalZero __IM uint32_t RESERVED19; 1134*150812a8SEvalZero __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1135*150812a8SEvalZero __IM uint32_t RESERVED20[5]; 1136*150812a8SEvalZero __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1137*150812a8SEvalZero source selected. */ 1138*150812a8SEvalZero __IM uint32_t RESERVED21[3]; 1139*150812a8SEvalZero __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1140*150812a8SEvalZero __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1141*150812a8SEvalZero __IM uint32_t RESERVED22[13]; 1142*150812a8SEvalZero __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1143*150812a8SEvalZero } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1144*150812a8SEvalZero 1145*150812a8SEvalZero 1146*150812a8SEvalZero 1147*150812a8SEvalZero /* =========================================================================================================================== */ 1148*150812a8SEvalZero /* ================ TWIS0_NS ================ */ 1149*150812a8SEvalZero /* =========================================================================================================================== */ 1150*150812a8SEvalZero 1151*150812a8SEvalZero 1152*150812a8SEvalZero /** 1153*150812a8SEvalZero * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0_NS) 1154*150812a8SEvalZero */ 1155*150812a8SEvalZero 1156*150812a8SEvalZero typedef struct { /*!< (@ 0x40008000) TWIS0_NS Structure */ 1157*150812a8SEvalZero __IM uint32_t RESERVED[5]; 1158*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1159*150812a8SEvalZero __IM uint32_t RESERVED1; 1160*150812a8SEvalZero __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1161*150812a8SEvalZero __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1162*150812a8SEvalZero __IM uint32_t RESERVED2[3]; 1163*150812a8SEvalZero __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1164*150812a8SEvalZero __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1165*150812a8SEvalZero __IM uint32_t RESERVED3[23]; 1166*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1167*150812a8SEvalZero __IM uint32_t RESERVED4; 1168*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1169*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1170*150812a8SEvalZero __IM uint32_t RESERVED5[3]; 1171*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_PREPARERX; /*!< (@ 0x000000B0) Subscribe configuration for task PREPARERX */ 1172*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_PREPARETX; /*!< (@ 0x000000B4) Subscribe configuration for task PREPARETX */ 1173*150812a8SEvalZero __IM uint32_t RESERVED6[19]; 1174*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1175*150812a8SEvalZero __IM uint32_t RESERVED7[7]; 1176*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1177*150812a8SEvalZero __IM uint32_t RESERVED8[9]; 1178*150812a8SEvalZero __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1179*150812a8SEvalZero __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1180*150812a8SEvalZero __IM uint32_t RESERVED9[4]; 1181*150812a8SEvalZero __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1182*150812a8SEvalZero __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1183*150812a8SEvalZero __IM uint32_t RESERVED10[6]; 1184*150812a8SEvalZero __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1185*150812a8SEvalZero __IM uint32_t RESERVED11[7]; 1186*150812a8SEvalZero __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1187*150812a8SEvalZero __IM uint32_t RESERVED12[9]; 1188*150812a8SEvalZero __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1189*150812a8SEvalZero __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1190*150812a8SEvalZero __IM uint32_t RESERVED13[4]; 1191*150812a8SEvalZero __IOM uint32_t PUBLISH_WRITE; /*!< (@ 0x000001E4) Publish configuration for event WRITE */ 1192*150812a8SEvalZero __IOM uint32_t PUBLISH_READ; /*!< (@ 0x000001E8) Publish configuration for event READ */ 1193*150812a8SEvalZero __IM uint32_t RESERVED14[5]; 1194*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1195*150812a8SEvalZero __IM uint32_t RESERVED15[63]; 1196*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1197*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1198*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1199*150812a8SEvalZero __IM uint32_t RESERVED16[113]; 1200*150812a8SEvalZero __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1201*150812a8SEvalZero __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1202*150812a8SEvalZero a match */ 1203*150812a8SEvalZero __IM uint32_t RESERVED17[10]; 1204*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1205*150812a8SEvalZero __IM uint32_t RESERVED18; 1206*150812a8SEvalZero __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1207*150812a8SEvalZero __IM uint32_t RESERVED19[9]; 1208*150812a8SEvalZero __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1209*150812a8SEvalZero __IM uint32_t RESERVED20; 1210*150812a8SEvalZero __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1211*150812a8SEvalZero __IM uint32_t RESERVED21[14]; 1212*150812a8SEvalZero __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1213*150812a8SEvalZero __IM uint32_t RESERVED22; 1214*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1215*150812a8SEvalZero mechanism */ 1216*150812a8SEvalZero __IM uint32_t RESERVED23[10]; 1217*150812a8SEvalZero __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1218*150812a8SEvalZero of an over-read of the transmit buffer. */ 1219*150812a8SEvalZero } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1220*150812a8SEvalZero 1221*150812a8SEvalZero 1222*150812a8SEvalZero 1223*150812a8SEvalZero /* =========================================================================================================================== */ 1224*150812a8SEvalZero /* ================ UARTE0_NS ================ */ 1225*150812a8SEvalZero /* =========================================================================================================================== */ 1226*150812a8SEvalZero 1227*150812a8SEvalZero 1228*150812a8SEvalZero /** 1229*150812a8SEvalZero * @brief UART with EasyDMA 0 (UARTE0_NS) 1230*150812a8SEvalZero */ 1231*150812a8SEvalZero 1232*150812a8SEvalZero typedef struct { /*!< (@ 0x40008000) UARTE0_NS Structure */ 1233*150812a8SEvalZero __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1234*150812a8SEvalZero __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1235*150812a8SEvalZero __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1236*150812a8SEvalZero __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1237*150812a8SEvalZero __IM uint32_t RESERVED[7]; 1238*150812a8SEvalZero __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 1239*150812a8SEvalZero __IM uint32_t RESERVED1[20]; 1240*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1241*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_STOPRX; /*!< (@ 0x00000084) Subscribe configuration for task STOPRX */ 1242*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1243*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_STOPTX; /*!< (@ 0x0000008C) Subscribe configuration for task STOPTX */ 1244*150812a8SEvalZero __IM uint32_t RESERVED2[7]; 1245*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_FLUSHRX; /*!< (@ 0x000000AC) Subscribe configuration for task FLUSHRX */ 1246*150812a8SEvalZero __IM uint32_t RESERVED3[20]; 1247*150812a8SEvalZero __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1248*150812a8SEvalZero __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1249*150812a8SEvalZero __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 1250*150812a8SEvalZero transferred to Data RAM) */ 1251*150812a8SEvalZero __IM uint32_t RESERVED4; 1252*150812a8SEvalZero __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 1253*150812a8SEvalZero __IM uint32_t RESERVED5[2]; 1254*150812a8SEvalZero __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1255*150812a8SEvalZero __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 1256*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1257*150812a8SEvalZero __IM uint32_t RESERVED6[7]; 1258*150812a8SEvalZero __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1259*150812a8SEvalZero __IM uint32_t RESERVED7; 1260*150812a8SEvalZero __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 1261*150812a8SEvalZero __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 1262*150812a8SEvalZero __IM uint32_t RESERVED8; 1263*150812a8SEvalZero __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 1264*150812a8SEvalZero __IM uint32_t RESERVED9[9]; 1265*150812a8SEvalZero __IOM uint32_t PUBLISH_CTS; /*!< (@ 0x00000180) Publish configuration for event CTS */ 1266*150812a8SEvalZero __IOM uint32_t PUBLISH_NCTS; /*!< (@ 0x00000184) Publish configuration for event NCTS */ 1267*150812a8SEvalZero __IOM uint32_t PUBLISH_RXDRDY; /*!< (@ 0x00000188) Publish configuration for event RXDRDY */ 1268*150812a8SEvalZero __IM uint32_t RESERVED10; 1269*150812a8SEvalZero __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1270*150812a8SEvalZero __IM uint32_t RESERVED11[2]; 1271*150812a8SEvalZero __IOM uint32_t PUBLISH_TXDRDY; /*!< (@ 0x0000019C) Publish configuration for event TXDRDY */ 1272*150812a8SEvalZero __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 1273*150812a8SEvalZero __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1274*150812a8SEvalZero __IM uint32_t RESERVED12[7]; 1275*150812a8SEvalZero __IOM uint32_t PUBLISH_RXTO; /*!< (@ 0x000001C4) Publish configuration for event RXTO */ 1276*150812a8SEvalZero __IM uint32_t RESERVED13; 1277*150812a8SEvalZero __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1278*150812a8SEvalZero __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1279*150812a8SEvalZero __IM uint32_t RESERVED14; 1280*150812a8SEvalZero __IOM uint32_t PUBLISH_TXSTOPPED; /*!< (@ 0x000001D8) Publish configuration for event TXSTOPPED */ 1281*150812a8SEvalZero __IM uint32_t RESERVED15[9]; 1282*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1283*150812a8SEvalZero __IM uint32_t RESERVED16[63]; 1284*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1285*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1286*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1287*150812a8SEvalZero __IM uint32_t RESERVED17[93]; 1288*150812a8SEvalZero __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write 1289*150812a8SEvalZero one to clear. */ 1290*150812a8SEvalZero __IM uint32_t RESERVED18[31]; 1291*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1292*150812a8SEvalZero __IM uint32_t RESERVED19; 1293*150812a8SEvalZero __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1294*150812a8SEvalZero __IM uint32_t RESERVED20[3]; 1295*150812a8SEvalZero __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1296*150812a8SEvalZero selected. */ 1297*150812a8SEvalZero __IM uint32_t RESERVED21[3]; 1298*150812a8SEvalZero __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1299*150812a8SEvalZero __IM uint32_t RESERVED22; 1300*150812a8SEvalZero __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1301*150812a8SEvalZero __IM uint32_t RESERVED23[7]; 1302*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1303*150812a8SEvalZero } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1304*150812a8SEvalZero 1305*150812a8SEvalZero 1306*150812a8SEvalZero 1307*150812a8SEvalZero /* =========================================================================================================================== */ 1308*150812a8SEvalZero /* ================ GPIOTE0_S ================ */ 1309*150812a8SEvalZero /* =========================================================================================================================== */ 1310*150812a8SEvalZero 1311*150812a8SEvalZero 1312*150812a8SEvalZero /** 1313*150812a8SEvalZero * @brief GPIO Tasks and Events 0 (GPIOTE0_S) 1314*150812a8SEvalZero */ 1315*150812a8SEvalZero 1316*150812a8SEvalZero typedef struct { /*!< (@ 0x5000D000) GPIOTE0_S Structure */ 1317*150812a8SEvalZero __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 1318*150812a8SEvalZero specified in CONFIG[n].PSEL. Action on pin 1319*150812a8SEvalZero is configured in CONFIG[n].POLARITY. */ 1320*150812a8SEvalZero __IM uint32_t RESERVED[4]; 1321*150812a8SEvalZero __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 1322*150812a8SEvalZero specified in CONFIG[n].PSEL. Action on pin 1323*150812a8SEvalZero is to set it high. */ 1324*150812a8SEvalZero __IM uint32_t RESERVED1[4]; 1325*150812a8SEvalZero __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 1326*150812a8SEvalZero specified in CONFIG[n].PSEL. Action on pin 1327*150812a8SEvalZero is to set it low. */ 1328*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_OUT[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1329*150812a8SEvalZero for task OUT[n] */ 1330*150812a8SEvalZero __IM uint32_t RESERVED2[4]; 1331*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_SET[8]; /*!< (@ 0x000000B0) Description collection: Subscribe configuration 1332*150812a8SEvalZero for task SET[n] */ 1333*150812a8SEvalZero __IM uint32_t RESERVED3[4]; 1334*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_CLR[8]; /*!< (@ 0x000000E0) Description collection: Subscribe configuration 1335*150812a8SEvalZero for task CLR[n] */ 1336*150812a8SEvalZero __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 1337*150812a8SEvalZero pin specified in CONFIG[n].PSEL */ 1338*150812a8SEvalZero __IM uint32_t RESERVED4[23]; 1339*150812a8SEvalZero __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1340*150812a8SEvalZero with SENSE mechanism enabled */ 1341*150812a8SEvalZero __IOM uint32_t PUBLISH_IN[8]; /*!< (@ 0x00000180) Description collection: Publish configuration 1342*150812a8SEvalZero for event IN[n] */ 1343*150812a8SEvalZero __IM uint32_t RESERVED5[23]; 1344*150812a8SEvalZero __IOM uint32_t PUBLISH_PORT; /*!< (@ 0x000001FC) Publish configuration for event PORT */ 1345*150812a8SEvalZero __IM uint32_t RESERVED6[65]; 1346*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1347*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1348*150812a8SEvalZero __IM uint32_t RESERVED7[129]; 1349*150812a8SEvalZero __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 1350*150812a8SEvalZero SET[n] and CLR[n] tasks and IN[n] event */ 1351*150812a8SEvalZero } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1352*150812a8SEvalZero 1353*150812a8SEvalZero 1354*150812a8SEvalZero 1355*150812a8SEvalZero /* =========================================================================================================================== */ 1356*150812a8SEvalZero /* ================ SAADC_NS ================ */ 1357*150812a8SEvalZero /* =========================================================================================================================== */ 1358*150812a8SEvalZero 1359*150812a8SEvalZero 1360*150812a8SEvalZero /** 1361*150812a8SEvalZero * @brief Analog to Digital Converter 0 (SAADC_NS) 1362*150812a8SEvalZero */ 1363*150812a8SEvalZero 1364*150812a8SEvalZero typedef struct { /*!< (@ 0x4000E000) SAADC_NS Structure */ 1365*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in 1366*150812a8SEvalZero RAM */ 1367*150812a8SEvalZero __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels 1368*150812a8SEvalZero are sampled */ 1369*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ 1370*150812a8SEvalZero __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1371*150812a8SEvalZero __IM uint32_t RESERVED[28]; 1372*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1373*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000084) Subscribe configuration for task SAMPLE */ 1374*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ 1375*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_CALIBRATEOFFSET; /*!< (@ 0x0000008C) Subscribe configuration for task CALIBRATEOFFSET */ 1376*150812a8SEvalZero __IM uint32_t RESERVED1[28]; 1377*150812a8SEvalZero __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ 1378*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ 1379*150812a8SEvalZero __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1380*150812a8SEvalZero on the mode, multiple conversions might 1381*150812a8SEvalZero be needed for a result to be transferred 1382*150812a8SEvalZero to RAM. */ 1383*150812a8SEvalZero __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ 1384*150812a8SEvalZero __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1385*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ 1386*150812a8SEvalZero __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ 1387*150812a8SEvalZero __IM uint32_t RESERVED2[10]; 1388*150812a8SEvalZero __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ 1389*150812a8SEvalZero __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 1390*150812a8SEvalZero __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x00000188) Publish configuration for event DONE */ 1391*150812a8SEvalZero __IOM uint32_t PUBLISH_RESULTDONE; /*!< (@ 0x0000018C) Publish configuration for event RESULTDONE */ 1392*150812a8SEvalZero __IOM uint32_t PUBLISH_CALIBRATEDONE; /*!< (@ 0x00000190) Publish configuration for event CALIBRATEDONE */ 1393*150812a8SEvalZero __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000194) Publish configuration for event STOPPED */ 1394*150812a8SEvalZero __IOM SAADC_PUBLISH_CH_Type PUBLISH_CH[8]; /*!< (@ 0x00000198) Publish configuration for events */ 1395*150812a8SEvalZero __IM uint32_t RESERVED3[74]; 1396*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1397*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1398*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1399*150812a8SEvalZero __IM uint32_t RESERVED4[61]; 1400*150812a8SEvalZero __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1401*150812a8SEvalZero __IM uint32_t RESERVED5[63]; 1402*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ 1403*150812a8SEvalZero __IM uint32_t RESERVED6[3]; 1404*150812a8SEvalZero __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1405*150812a8SEvalZero __IM uint32_t RESERVED7[24]; 1406*150812a8SEvalZero __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1407*150812a8SEvalZero __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should 1408*150812a8SEvalZero not be combined with SCAN. The RESOLUTION 1409*150812a8SEvalZero is applied before averaging, thus for high 1410*150812a8SEvalZero OVERSAMPLE a higher RESOLUTION should be 1411*150812a8SEvalZero used. */ 1412*150812a8SEvalZero __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1413*150812a8SEvalZero __IM uint32_t RESERVED8[12]; 1414*150812a8SEvalZero __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1415*150812a8SEvalZero } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1416*150812a8SEvalZero 1417*150812a8SEvalZero 1418*150812a8SEvalZero 1419*150812a8SEvalZero /* =========================================================================================================================== */ 1420*150812a8SEvalZero /* ================ TIMER0_NS ================ */ 1421*150812a8SEvalZero /* =========================================================================================================================== */ 1422*150812a8SEvalZero 1423*150812a8SEvalZero 1424*150812a8SEvalZero /** 1425*150812a8SEvalZero * @brief Timer/Counter 0 (TIMER0_NS) 1426*150812a8SEvalZero */ 1427*150812a8SEvalZero 1428*150812a8SEvalZero typedef struct { /*!< (@ 0x4000F000) TIMER0_NS Structure */ 1429*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1430*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1431*150812a8SEvalZero __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1432*150812a8SEvalZero __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1433*150812a8SEvalZero __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1434*150812a8SEvalZero __IM uint32_t RESERVED[11]; 1435*150812a8SEvalZero __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 1436*150812a8SEvalZero CC[n] register */ 1437*150812a8SEvalZero __IM uint32_t RESERVED1[10]; 1438*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1439*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1440*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_COUNT; /*!< (@ 0x00000088) Subscribe configuration for task COUNT */ 1441*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR */ 1442*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_SHUTDOWN; /*!< (@ 0x00000090) Deprecated register - Subscribe configuration 1443*150812a8SEvalZero for task SHUTDOWN */ 1444*150812a8SEvalZero __IM uint32_t RESERVED2[11]; 1445*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_CAPTURE[6]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration 1446*150812a8SEvalZero for task CAPTURE[n] */ 1447*150812a8SEvalZero __IM uint32_t RESERVED3[26]; 1448*150812a8SEvalZero __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1449*150812a8SEvalZero match */ 1450*150812a8SEvalZero __IM uint32_t RESERVED4[26]; 1451*150812a8SEvalZero __IOM uint32_t PUBLISH_COMPARE[6]; /*!< (@ 0x000001C0) Description collection: Publish configuration 1452*150812a8SEvalZero for event COMPARE[n] */ 1453*150812a8SEvalZero __IM uint32_t RESERVED5[10]; 1454*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1455*150812a8SEvalZero __IM uint32_t RESERVED6[64]; 1456*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1457*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1458*150812a8SEvalZero __IM uint32_t RESERVED7[126]; 1459*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1460*150812a8SEvalZero __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1461*150812a8SEvalZero __IM uint32_t RESERVED8; 1462*150812a8SEvalZero __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1463*150812a8SEvalZero __IM uint32_t RESERVED9[11]; 1464*150812a8SEvalZero __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 1465*150812a8SEvalZero n */ 1466*150812a8SEvalZero } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1467*150812a8SEvalZero 1468*150812a8SEvalZero 1469*150812a8SEvalZero 1470*150812a8SEvalZero /* =========================================================================================================================== */ 1471*150812a8SEvalZero /* ================ RTC0_NS ================ */ 1472*150812a8SEvalZero /* =========================================================================================================================== */ 1473*150812a8SEvalZero 1474*150812a8SEvalZero 1475*150812a8SEvalZero /** 1476*150812a8SEvalZero * @brief Real-time counter 0 (RTC0_NS) 1477*150812a8SEvalZero */ 1478*150812a8SEvalZero 1479*150812a8SEvalZero typedef struct { /*!< (@ 0x40014000) RTC0_NS Structure */ 1480*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC counter */ 1481*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC counter */ 1482*150812a8SEvalZero __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC counter */ 1483*150812a8SEvalZero __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set counter to 0xFFFFF0 */ 1484*150812a8SEvalZero __IM uint32_t RESERVED[28]; 1485*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1486*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1487*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x00000088) Subscribe configuration for task CLEAR */ 1488*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_TRIGOVRFLW; /*!< (@ 0x0000008C) Subscribe configuration for task TRIGOVRFLW */ 1489*150812a8SEvalZero __IM uint32_t RESERVED1[28]; 1490*150812a8SEvalZero __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on counter increment */ 1491*150812a8SEvalZero __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on counter overflow */ 1492*150812a8SEvalZero __IM uint32_t RESERVED2[14]; 1493*150812a8SEvalZero __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1494*150812a8SEvalZero match */ 1495*150812a8SEvalZero __IM uint32_t RESERVED3[12]; 1496*150812a8SEvalZero __IOM uint32_t PUBLISH_TICK; /*!< (@ 0x00000180) Publish configuration for event TICK */ 1497*150812a8SEvalZero __IOM uint32_t PUBLISH_OVRFLW; /*!< (@ 0x00000184) Publish configuration for event OVRFLW */ 1498*150812a8SEvalZero __IM uint32_t RESERVED4[14]; 1499*150812a8SEvalZero __IOM uint32_t PUBLISH_COMPARE[4]; /*!< (@ 0x000001C0) Description collection: Publish configuration 1500*150812a8SEvalZero for event COMPARE[n] */ 1501*150812a8SEvalZero __IM uint32_t RESERVED5[77]; 1502*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1503*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1504*150812a8SEvalZero __IM uint32_t RESERVED6[13]; 1505*150812a8SEvalZero __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1506*150812a8SEvalZero __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1507*150812a8SEvalZero __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1508*150812a8SEvalZero __IM uint32_t RESERVED7[110]; 1509*150812a8SEvalZero __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current counter value */ 1510*150812a8SEvalZero __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). 1511*150812a8SEvalZero Must be written when RTC is stopped. */ 1512*150812a8SEvalZero __IM uint32_t RESERVED8[13]; 1513*150812a8SEvalZero __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 1514*150812a8SEvalZero } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1515*150812a8SEvalZero 1516*150812a8SEvalZero 1517*150812a8SEvalZero 1518*150812a8SEvalZero /* =========================================================================================================================== */ 1519*150812a8SEvalZero /* ================ DPPIC_NS ================ */ 1520*150812a8SEvalZero /* =========================================================================================================================== */ 1521*150812a8SEvalZero 1522*150812a8SEvalZero 1523*150812a8SEvalZero /** 1524*150812a8SEvalZero * @brief Distributed Programmable Peripheral Interconnect Controller 0 (DPPIC_NS) 1525*150812a8SEvalZero */ 1526*150812a8SEvalZero 1527*150812a8SEvalZero typedef struct { /*!< (@ 0x40017000) DPPIC_NS Structure */ 1528*150812a8SEvalZero __OM DPPIC_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 1529*150812a8SEvalZero __IM uint32_t RESERVED[20]; 1530*150812a8SEvalZero __IOM DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6];/*!< (@ 0x00000080) Subscribe configuration for tasks */ 1531*150812a8SEvalZero __IM uint32_t RESERVED1[276]; 1532*150812a8SEvalZero __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 1533*150812a8SEvalZero __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 1534*150812a8SEvalZero __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 1535*150812a8SEvalZero __IM uint32_t RESERVED2[189]; 1536*150812a8SEvalZero __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n Note: 1537*150812a8SEvalZero Writes to this register is ignored if either 1538*150812a8SEvalZero SUBSCRIBE_CHG[n].EN/DIS are enabled. */ 1539*150812a8SEvalZero } NRF_DPPIC_Type; /*!< Size = 2072 (0x818) */ 1540*150812a8SEvalZero 1541*150812a8SEvalZero 1542*150812a8SEvalZero 1543*150812a8SEvalZero /* =========================================================================================================================== */ 1544*150812a8SEvalZero /* ================ WDT_NS ================ */ 1545*150812a8SEvalZero /* =========================================================================================================================== */ 1546*150812a8SEvalZero 1547*150812a8SEvalZero 1548*150812a8SEvalZero /** 1549*150812a8SEvalZero * @brief Watchdog Timer 0 (WDT_NS) 1550*150812a8SEvalZero */ 1551*150812a8SEvalZero 1552*150812a8SEvalZero typedef struct { /*!< (@ 0x40018000) WDT_NS Structure */ 1553*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 1554*150812a8SEvalZero __IM uint32_t RESERVED[31]; 1555*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1556*150812a8SEvalZero __IM uint32_t RESERVED1[31]; 1557*150812a8SEvalZero __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 1558*150812a8SEvalZero __IM uint32_t RESERVED2[31]; 1559*150812a8SEvalZero __IOM uint32_t PUBLISH_TIMEOUT; /*!< (@ 0x00000180) Publish configuration for event TIMEOUT */ 1560*150812a8SEvalZero __IM uint32_t RESERVED3[96]; 1561*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1562*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1563*150812a8SEvalZero __IM uint32_t RESERVED4[61]; 1564*150812a8SEvalZero __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 1565*150812a8SEvalZero __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 1566*150812a8SEvalZero __IM uint32_t RESERVED5[63]; 1567*150812a8SEvalZero __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 1568*150812a8SEvalZero __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 1569*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 1570*150812a8SEvalZero __IM uint32_t RESERVED6[60]; 1571*150812a8SEvalZero __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 1572*150812a8SEvalZero } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 1573*150812a8SEvalZero 1574*150812a8SEvalZero 1575*150812a8SEvalZero 1576*150812a8SEvalZero /* =========================================================================================================================== */ 1577*150812a8SEvalZero /* ================ EGU0_NS ================ */ 1578*150812a8SEvalZero /* =========================================================================================================================== */ 1579*150812a8SEvalZero 1580*150812a8SEvalZero 1581*150812a8SEvalZero /** 1582*150812a8SEvalZero * @brief Event Generator Unit 0 (EGU0_NS) 1583*150812a8SEvalZero */ 1584*150812a8SEvalZero 1585*150812a8SEvalZero typedef struct { /*!< (@ 0x4001B000) EGU0_NS Structure */ 1586*150812a8SEvalZero __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 1587*150812a8SEvalZero the corresponding TRIGGERED[n] event */ 1588*150812a8SEvalZero __IM uint32_t RESERVED[16]; 1589*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_TRIGGER[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1590*150812a8SEvalZero for task TRIGGER[n] */ 1591*150812a8SEvalZero __IM uint32_t RESERVED1[16]; 1592*150812a8SEvalZero __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 1593*150812a8SEvalZero by triggering the corresponding TRIGGER[n] 1594*150812a8SEvalZero task */ 1595*150812a8SEvalZero __IM uint32_t RESERVED2[16]; 1596*150812a8SEvalZero __IOM uint32_t PUBLISH_TRIGGERED[16]; /*!< (@ 0x00000180) Description collection: Publish configuration 1597*150812a8SEvalZero for event TRIGGERED[n] */ 1598*150812a8SEvalZero __IM uint32_t RESERVED3[80]; 1599*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1600*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1601*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1602*150812a8SEvalZero } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1603*150812a8SEvalZero 1604*150812a8SEvalZero 1605*150812a8SEvalZero 1606*150812a8SEvalZero /* =========================================================================================================================== */ 1607*150812a8SEvalZero /* ================ PWM0_NS ================ */ 1608*150812a8SEvalZero /* =========================================================================================================================== */ 1609*150812a8SEvalZero 1610*150812a8SEvalZero 1611*150812a8SEvalZero /** 1612*150812a8SEvalZero * @brief Pulse width modulation unit 0 (PWM0_NS) 1613*150812a8SEvalZero */ 1614*150812a8SEvalZero 1615*150812a8SEvalZero typedef struct { /*!< (@ 0x40021000) PWM0_NS Structure */ 1616*150812a8SEvalZero __IM uint32_t RESERVED; 1617*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 1618*150812a8SEvalZero the end of current PWM period, and stops 1619*150812a8SEvalZero sequence playback */ 1620*150812a8SEvalZero __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value 1621*150812a8SEvalZero on all enabled channels from sequence n, 1622*150812a8SEvalZero and starts playing that sequence at the 1623*150812a8SEvalZero rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 1624*150812a8SEvalZero Causes PWM generation to start if not running. */ 1625*150812a8SEvalZero __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 1626*150812a8SEvalZero all enabled channels if DECODER.MODE=NextStep. 1627*150812a8SEvalZero Does not cause PWM generation to start if 1628*150812a8SEvalZero not running. */ 1629*150812a8SEvalZero __IM uint32_t RESERVED1[28]; 1630*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1631*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_SEQSTART[2]; /*!< (@ 0x00000088) Description collection: Subscribe configuration 1632*150812a8SEvalZero for task SEQSTART[n] */ 1633*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_NEXTSTEP; /*!< (@ 0x00000090) Subscribe configuration for task NEXTSTEP */ 1634*150812a8SEvalZero __IM uint32_t RESERVED2[28]; 1635*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 1636*150812a8SEvalZero are no longer generated */ 1637*150812a8SEvalZero __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started 1638*150812a8SEvalZero on sequence n */ 1639*150812a8SEvalZero __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every 1640*150812a8SEvalZero sequence n, when last value from RAM has 1641*150812a8SEvalZero been applied to wave counter */ 1642*150812a8SEvalZero __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 1643*150812a8SEvalZero __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 1644*150812a8SEvalZero of times defined in LOOP.CNT */ 1645*150812a8SEvalZero __IM uint32_t RESERVED3[25]; 1646*150812a8SEvalZero __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1647*150812a8SEvalZero __IOM uint32_t PUBLISH_SEQSTARTED[2]; /*!< (@ 0x00000188) Description collection: Publish configuration 1648*150812a8SEvalZero for event SEQSTARTED[n] */ 1649*150812a8SEvalZero __IOM uint32_t PUBLISH_SEQEND[2]; /*!< (@ 0x00000190) Description collection: Publish configuration 1650*150812a8SEvalZero for event SEQEND[n] */ 1651*150812a8SEvalZero __IOM uint32_t PUBLISH_PWMPERIODEND; /*!< (@ 0x00000198) Publish configuration for event PWMPERIODEND */ 1652*150812a8SEvalZero __IOM uint32_t PUBLISH_LOOPSDONE; /*!< (@ 0x0000019C) Publish configuration for event LOOPSDONE */ 1653*150812a8SEvalZero __IM uint32_t RESERVED4[24]; 1654*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1655*150812a8SEvalZero __IM uint32_t RESERVED5[63]; 1656*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1657*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1658*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1659*150812a8SEvalZero __IM uint32_t RESERVED6[125]; 1660*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 1661*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 1662*150812a8SEvalZero __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 1663*150812a8SEvalZero counts */ 1664*150812a8SEvalZero __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 1665*150812a8SEvalZero __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 1666*150812a8SEvalZero __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ 1667*150812a8SEvalZero __IM uint32_t RESERVED7[2]; 1668*150812a8SEvalZero __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 1669*150812a8SEvalZero __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 1670*150812a8SEvalZero } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 1671*150812a8SEvalZero 1672*150812a8SEvalZero 1673*150812a8SEvalZero 1674*150812a8SEvalZero /* =========================================================================================================================== */ 1675*150812a8SEvalZero /* ================ PDM_NS ================ */ 1676*150812a8SEvalZero /* =========================================================================================================================== */ 1677*150812a8SEvalZero 1678*150812a8SEvalZero 1679*150812a8SEvalZero /** 1680*150812a8SEvalZero * @brief Pulse Density Modulation (Digital Microphone) Interface 0 (PDM_NS) 1681*150812a8SEvalZero */ 1682*150812a8SEvalZero 1683*150812a8SEvalZero typedef struct { /*!< (@ 0x40026000) PDM_NS Structure */ 1684*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 1685*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 1686*150812a8SEvalZero __IM uint32_t RESERVED[30]; 1687*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1688*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1689*150812a8SEvalZero __IM uint32_t RESERVED1[30]; 1690*150812a8SEvalZero __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 1691*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 1692*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 1693*150812a8SEvalZero by SAMPLE.MAXCNT (or the last sample after 1694*150812a8SEvalZero a STOP task has been received) to Data RAM */ 1695*150812a8SEvalZero __IM uint32_t RESERVED2[29]; 1696*150812a8SEvalZero __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ 1697*150812a8SEvalZero __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1698*150812a8SEvalZero __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000188) Publish configuration for event END */ 1699*150812a8SEvalZero __IM uint32_t RESERVED3[93]; 1700*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1701*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1702*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1703*150812a8SEvalZero __IM uint32_t RESERVED4[125]; 1704*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 1705*150812a8SEvalZero __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 1706*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 1707*150812a8SEvalZero signals */ 1708*150812a8SEvalZero __IM uint32_t RESERVED5[3]; 1709*150812a8SEvalZero __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 1710*150812a8SEvalZero __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 1711*150812a8SEvalZero __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output 1712*150812a8SEvalZero sample rate. Change PDMCLKCTRL accordingly. */ 1713*150812a8SEvalZero __IM uint32_t RESERVED6[7]; 1714*150812a8SEvalZero __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 1715*150812a8SEvalZero __IM uint32_t RESERVED7[6]; 1716*150812a8SEvalZero __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 1717*150812a8SEvalZero } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 1718*150812a8SEvalZero 1719*150812a8SEvalZero 1720*150812a8SEvalZero 1721*150812a8SEvalZero /* =========================================================================================================================== */ 1722*150812a8SEvalZero /* ================ I2S_NS ================ */ 1723*150812a8SEvalZero /* =========================================================================================================================== */ 1724*150812a8SEvalZero 1725*150812a8SEvalZero 1726*150812a8SEvalZero /** 1727*150812a8SEvalZero * @brief Inter-IC Sound 0 (I2S_NS) 1728*150812a8SEvalZero */ 1729*150812a8SEvalZero 1730*150812a8SEvalZero typedef struct { /*!< (@ 0x40028000) I2S_NS Structure */ 1731*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK 1732*150812a8SEvalZero generator when this is enabled. */ 1733*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. 1734*150812a8SEvalZero Triggering this task will cause the STOPPED 1735*150812a8SEvalZero event to be generated. */ 1736*150812a8SEvalZero __IM uint32_t RESERVED[30]; 1737*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1738*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 1739*150812a8SEvalZero __IM uint32_t RESERVED1[31]; 1740*150812a8SEvalZero __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal 1741*150812a8SEvalZero double-buffers. When the I2S module is started 1742*150812a8SEvalZero and RX is enabled, this event will be generated 1743*150812a8SEvalZero for every RXTXD.MAXCNT words that are received 1744*150812a8SEvalZero on the SDIN pin. */ 1745*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ 1746*150812a8SEvalZero __IM uint32_t RESERVED2[2]; 1747*150812a8SEvalZero __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal 1748*150812a8SEvalZero double-buffers. When the I2S module is started 1749*150812a8SEvalZero and TX is enabled, this event will be generated 1750*150812a8SEvalZero for every RXTXD.MAXCNT words that are sent 1751*150812a8SEvalZero on the SDOUT pin. */ 1752*150812a8SEvalZero __IM uint32_t RESERVED3[27]; 1753*150812a8SEvalZero __IOM uint32_t PUBLISH_RXPTRUPD; /*!< (@ 0x00000184) Publish configuration for event RXPTRUPD */ 1754*150812a8SEvalZero __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000188) Publish configuration for event STOPPED */ 1755*150812a8SEvalZero __IM uint32_t RESERVED4[2]; 1756*150812a8SEvalZero __IOM uint32_t PUBLISH_TXPTRUPD; /*!< (@ 0x00000194) Publish configuration for event TXPTRUPD */ 1757*150812a8SEvalZero __IM uint32_t RESERVED5[90]; 1758*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1759*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1760*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1761*150812a8SEvalZero __IM uint32_t RESERVED6[125]; 1762*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ 1763*150812a8SEvalZero __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ 1764*150812a8SEvalZero __IM uint32_t RESERVED7[3]; 1765*150812a8SEvalZero __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ 1766*150812a8SEvalZero __IM uint32_t RESERVED8; 1767*150812a8SEvalZero __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ 1768*150812a8SEvalZero __IM uint32_t RESERVED9[3]; 1769*150812a8SEvalZero __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ 1770*150812a8SEvalZero __IM uint32_t RESERVED10[3]; 1771*150812a8SEvalZero __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 1772*150812a8SEvalZero } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ 1773*150812a8SEvalZero 1774*150812a8SEvalZero 1775*150812a8SEvalZero 1776*150812a8SEvalZero /* =========================================================================================================================== */ 1777*150812a8SEvalZero /* ================ IPC_NS ================ */ 1778*150812a8SEvalZero /* =========================================================================================================================== */ 1779*150812a8SEvalZero 1780*150812a8SEvalZero 1781*150812a8SEvalZero /** 1782*150812a8SEvalZero * @brief Inter Processor Communication 0 (IPC_NS) 1783*150812a8SEvalZero */ 1784*150812a8SEvalZero 1785*150812a8SEvalZero typedef struct { /*!< (@ 0x4002A000) IPC_NS Structure */ 1786*150812a8SEvalZero __OM uint32_t TASKS_SEND[8]; /*!< (@ 0x00000000) Description collection: Trigger events on channel 1787*150812a8SEvalZero enabled in SEND_CNF[n]. */ 1788*150812a8SEvalZero __IM uint32_t RESERVED[24]; 1789*150812a8SEvalZero __IOM uint32_t SUBSCRIBE_SEND[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1790*150812a8SEvalZero for task SEND[n] */ 1791*150812a8SEvalZero __IM uint32_t RESERVED1[24]; 1792*150812a8SEvalZero __IOM uint32_t EVENTS_RECEIVE[8]; /*!< (@ 0x00000100) Description collection: Event received on one 1793*150812a8SEvalZero or more of the enabled channels in RECEIVE_CNF[n]. */ 1794*150812a8SEvalZero __IM uint32_t RESERVED2[24]; 1795*150812a8SEvalZero __IOM uint32_t PUBLISH_RECEIVE[8]; /*!< (@ 0x00000180) Description collection: Publish configuration 1796*150812a8SEvalZero for event RECEIVE[n] */ 1797*150812a8SEvalZero __IM uint32_t RESERVED3[88]; 1798*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1799*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1800*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1801*150812a8SEvalZero __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 1802*150812a8SEvalZero __IM uint32_t RESERVED4[128]; 1803*150812a8SEvalZero __IOM uint32_t SEND_CNF[8]; /*!< (@ 0x00000510) Description collection: Send event configuration 1804*150812a8SEvalZero for TASKS_SEND[n]. */ 1805*150812a8SEvalZero __IM uint32_t RESERVED5[24]; 1806*150812a8SEvalZero __IOM uint32_t RECEIVE_CNF[8]; /*!< (@ 0x00000590) Description collection: Receive event configuration 1807*150812a8SEvalZero for EVENTS_RECEIVE[n]. */ 1808*150812a8SEvalZero __IM uint32_t RESERVED6[24]; 1809*150812a8SEvalZero __IOM uint32_t GPMEM[4]; /*!< (@ 0x00000610) Description collection: General purpose memory. */ 1810*150812a8SEvalZero } NRF_IPC_Type; /*!< Size = 1568 (0x620) */ 1811*150812a8SEvalZero 1812*150812a8SEvalZero 1813*150812a8SEvalZero 1814*150812a8SEvalZero /* =========================================================================================================================== */ 1815*150812a8SEvalZero /* ================ FPU_NS ================ */ 1816*150812a8SEvalZero /* =========================================================================================================================== */ 1817*150812a8SEvalZero 1818*150812a8SEvalZero 1819*150812a8SEvalZero /** 1820*150812a8SEvalZero * @brief FPU 0 (FPU_NS) 1821*150812a8SEvalZero */ 1822*150812a8SEvalZero 1823*150812a8SEvalZero typedef struct { /*!< (@ 0x4002C000) FPU_NS Structure */ 1824*150812a8SEvalZero __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1825*150812a8SEvalZero } NRF_FPU_Type; /*!< Size = 4 (0x4) */ 1826*150812a8SEvalZero 1827*150812a8SEvalZero 1828*150812a8SEvalZero 1829*150812a8SEvalZero /* =========================================================================================================================== */ 1830*150812a8SEvalZero /* ================ KMU_NS ================ */ 1831*150812a8SEvalZero /* =========================================================================================================================== */ 1832*150812a8SEvalZero 1833*150812a8SEvalZero 1834*150812a8SEvalZero /** 1835*150812a8SEvalZero * @brief Key management unit 0 (KMU_NS) 1836*150812a8SEvalZero */ 1837*150812a8SEvalZero 1838*150812a8SEvalZero typedef struct { /*!< (@ 0x40039000) KMU_NS Structure */ 1839*150812a8SEvalZero __OM uint32_t TASKS_PUSH_KEYSLOT; /*!< (@ 0x00000000) Push a key slot over secure APB */ 1840*150812a8SEvalZero __IM uint32_t RESERVED[63]; 1841*150812a8SEvalZero __IOM uint32_t EVENTS_KEYSLOT_PUSHED; /*!< (@ 0x00000100) Key successfully pushed over secure APB */ 1842*150812a8SEvalZero __IOM uint32_t EVENTS_KEYSLOT_REVOKED; /*!< (@ 0x00000104) Key has been revoked and cannot be tasked for 1843*150812a8SEvalZero selection */ 1844*150812a8SEvalZero __IOM uint32_t EVENTS_KEYSLOT_ERROR; /*!< (@ 0x00000108) No key slot selected, no destination address 1845*150812a8SEvalZero defined, or error during push operation */ 1846*150812a8SEvalZero __IM uint32_t RESERVED1[125]; 1847*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1848*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1849*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1850*150812a8SEvalZero __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 1851*150812a8SEvalZero __IM uint32_t RESERVED2[63]; 1852*150812a8SEvalZero __IM uint32_t STATUS; /*!< (@ 0x0000040C) Status bits for KMU operation */ 1853*150812a8SEvalZero __IM uint32_t RESERVED3[60]; 1854*150812a8SEvalZero __IOM uint32_t SELECTKEYSLOT; /*!< (@ 0x00000500) Select key slot ID to be read over AHB or pushed 1855*150812a8SEvalZero over secure APB when TASKS_PUSH_KEYSLOT 1856*150812a8SEvalZero is started */ 1857*150812a8SEvalZero } NRF_KMU_Type; /*!< Size = 1284 (0x504) */ 1858*150812a8SEvalZero 1859*150812a8SEvalZero 1860*150812a8SEvalZero 1861*150812a8SEvalZero /* =========================================================================================================================== */ 1862*150812a8SEvalZero /* ================ NVMC_NS ================ */ 1863*150812a8SEvalZero /* =========================================================================================================================== */ 1864*150812a8SEvalZero 1865*150812a8SEvalZero 1866*150812a8SEvalZero /** 1867*150812a8SEvalZero * @brief Non-volatile memory controller 0 (NVMC_NS) 1868*150812a8SEvalZero */ 1869*150812a8SEvalZero 1870*150812a8SEvalZero typedef struct { /*!< (@ 0x40039000) NVMC_NS Structure */ 1871*150812a8SEvalZero __IM uint32_t RESERVED[256]; 1872*150812a8SEvalZero __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 1873*150812a8SEvalZero __IM uint32_t RESERVED1; 1874*150812a8SEvalZero __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 1875*150812a8SEvalZero __IM uint32_t RESERVED2[62]; 1876*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1877*150812a8SEvalZero __IM uint32_t RESERVED3; 1878*150812a8SEvalZero __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 1879*150812a8SEvalZero __IM uint32_t RESERVED4[3]; 1880*150812a8SEvalZero __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 1881*150812a8SEvalZero __IM uint32_t RESERVED5[8]; 1882*150812a8SEvalZero __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register */ 1883*150812a8SEvalZero __IM uint32_t RESERVED6; 1884*150812a8SEvalZero __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */ 1885*150812a8SEvalZero __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */ 1886*150812a8SEvalZero __IM uint32_t RESERVED7[13]; 1887*150812a8SEvalZero __IOM uint32_t CONFIGNS; /*!< (@ 0x00000584) Unspecified */ 1888*150812a8SEvalZero __OM uint32_t WRITEUICRNS; /*!< (@ 0x00000588) Non-secure APPROTECT enable register */ 1889*150812a8SEvalZero __IM uint32_t RESERVED8[93]; 1890*150812a8SEvalZero __IOM uint32_t FORCEONNVM; /*!< (@ 0x00000700) Force on all NVM supplies. Also see the internal 1891*150812a8SEvalZero section in the NVMC chapter. */ 1892*150812a8SEvalZero __IM uint32_t RESERVED9[9]; 1893*150812a8SEvalZero __IOM uint32_t FORCEOFFNVM; /*!< (@ 0x00000728) Force off NVM supply. Also see the internal section 1894*150812a8SEvalZero in the NVMC chapter. */ 1895*150812a8SEvalZero } NRF_NVMC_Type; /*!< Size = 1836 (0x72c) */ 1896*150812a8SEvalZero 1897*150812a8SEvalZero 1898*150812a8SEvalZero 1899*150812a8SEvalZero /* =========================================================================================================================== */ 1900*150812a8SEvalZero /* ================ VMC_NS ================ */ 1901*150812a8SEvalZero /* =========================================================================================================================== */ 1902*150812a8SEvalZero 1903*150812a8SEvalZero 1904*150812a8SEvalZero /** 1905*150812a8SEvalZero * @brief Volatile Memory controller 0 (VMC_NS) 1906*150812a8SEvalZero */ 1907*150812a8SEvalZero 1908*150812a8SEvalZero typedef struct { /*!< (@ 0x4003A000) VMC_NS Structure */ 1909*150812a8SEvalZero __IM uint32_t RESERVED[384]; 1910*150812a8SEvalZero __IOM VMC_RAM_Type RAM[8]; /*!< (@ 0x00000600) Unspecified */ 1911*150812a8SEvalZero } NRF_VMC_Type; /*!< Size = 1664 (0x680) */ 1912*150812a8SEvalZero 1913*150812a8SEvalZero 1914*150812a8SEvalZero 1915*150812a8SEvalZero /* =========================================================================================================================== */ 1916*150812a8SEvalZero /* ================ CRYPTOCELL_S ================ */ 1917*150812a8SEvalZero /* =========================================================================================================================== */ 1918*150812a8SEvalZero 1919*150812a8SEvalZero 1920*150812a8SEvalZero /** 1921*150812a8SEvalZero * @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL_S) 1922*150812a8SEvalZero */ 1923*150812a8SEvalZero 1924*150812a8SEvalZero typedef struct { /*!< (@ 0x50840000) CRYPTOCELL_S Structure */ 1925*150812a8SEvalZero __IM uint32_t RESERVED[320]; 1926*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem */ 1927*150812a8SEvalZero } NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ 1928*150812a8SEvalZero 1929*150812a8SEvalZero 1930*150812a8SEvalZero 1931*150812a8SEvalZero /* =========================================================================================================================== */ 1932*150812a8SEvalZero /* ================ P0_NS ================ */ 1933*150812a8SEvalZero /* =========================================================================================================================== */ 1934*150812a8SEvalZero 1935*150812a8SEvalZero 1936*150812a8SEvalZero /** 1937*150812a8SEvalZero * @brief GPIO Port 0 (P0_NS) 1938*150812a8SEvalZero */ 1939*150812a8SEvalZero 1940*150812a8SEvalZero typedef struct { /*!< (@ 0x40842500) P0_NS Structure */ 1941*150812a8SEvalZero __IM uint32_t RESERVED; 1942*150812a8SEvalZero __IOM uint32_t OUT; /*!< (@ 0x00000004) Write GPIO port */ 1943*150812a8SEvalZero __IOM uint32_t OUTSET; /*!< (@ 0x00000008) Set individual bits in GPIO port */ 1944*150812a8SEvalZero __IOM uint32_t OUTCLR; /*!< (@ 0x0000000C) Clear individual bits in GPIO port */ 1945*150812a8SEvalZero __IM uint32_t IN; /*!< (@ 0x00000010) Read GPIO port */ 1946*150812a8SEvalZero __IOM uint32_t DIR; /*!< (@ 0x00000014) Direction of GPIO pins */ 1947*150812a8SEvalZero __IOM uint32_t DIRSET; /*!< (@ 0x00000018) DIR set register */ 1948*150812a8SEvalZero __IOM uint32_t DIRCLR; /*!< (@ 0x0000001C) DIR clear register */ 1949*150812a8SEvalZero __IOM uint32_t LATCH; /*!< (@ 0x00000020) Latch register indicating what GPIO pins that 1950*150812a8SEvalZero have met the criteria set in the PIN_CNF[n].SENSE 1951*150812a8SEvalZero registers */ 1952*150812a8SEvalZero __IOM uint32_t DETECTMODE; /*!< (@ 0x00000024) Select between default DETECT signal behaviour 1953*150812a8SEvalZero and LDETECT mode (For non-secure pin only) */ 1954*150812a8SEvalZero __IOM uint32_t DETECTMODE_SEC; /*!< (@ 0x00000028) Select between default DETECT signal behaviour 1955*150812a8SEvalZero and LDETECT mode (For secure pin only) */ 1956*150812a8SEvalZero __IM uint32_t RESERVED1[117]; 1957*150812a8SEvalZero __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000200) Description collection: Configuration of GPIO 1958*150812a8SEvalZero pins */ 1959*150812a8SEvalZero } NRF_GPIO_Type; /*!< Size = 640 (0x280) */ 1960*150812a8SEvalZero 1961*150812a8SEvalZero 1962*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_peripherals */ 1963*150812a8SEvalZero 1964*150812a8SEvalZero 1965*150812a8SEvalZero /* =========================================================================================================================== */ 1966*150812a8SEvalZero /* ================ Device Specific Peripheral Address Map ================ */ 1967*150812a8SEvalZero /* =========================================================================================================================== */ 1968*150812a8SEvalZero 1969*150812a8SEvalZero 1970*150812a8SEvalZero /** @addtogroup Device_Peripheral_peripheralAddr 1971*150812a8SEvalZero * @{ 1972*150812a8SEvalZero */ 1973*150812a8SEvalZero 1974*150812a8SEvalZero #define NRF_FICR_S_BASE 0x00FF0000UL 1975*150812a8SEvalZero #define NRF_UICR_S_BASE 0x00FF8000UL 1976*150812a8SEvalZero #define NRF_TAD_S_BASE 0xE0080000UL 1977*150812a8SEvalZero #define NRF_SPU_S_BASE 0x50003000UL 1978*150812a8SEvalZero #define NRF_REGULATORS_NS_BASE 0x40004000UL 1979*150812a8SEvalZero #define NRF_REGULATORS_S_BASE 0x50004000UL 1980*150812a8SEvalZero #define NRF_CLOCK_NS_BASE 0x40005000UL 1981*150812a8SEvalZero #define NRF_POWER_NS_BASE 0x40005000UL 1982*150812a8SEvalZero #define NRF_CLOCK_S_BASE 0x50005000UL 1983*150812a8SEvalZero #define NRF_POWER_S_BASE 0x50005000UL 1984*150812a8SEvalZero #define NRF_CTRL_AP_PERI_S_BASE 0x50006000UL 1985*150812a8SEvalZero #define NRF_SPIM0_NS_BASE 0x40008000UL 1986*150812a8SEvalZero #define NRF_SPIS0_NS_BASE 0x40008000UL 1987*150812a8SEvalZero #define NRF_TWIM0_NS_BASE 0x40008000UL 1988*150812a8SEvalZero #define NRF_TWIS0_NS_BASE 0x40008000UL 1989*150812a8SEvalZero #define NRF_UARTE0_NS_BASE 0x40008000UL 1990*150812a8SEvalZero #define NRF_SPIM0_S_BASE 0x50008000UL 1991*150812a8SEvalZero #define NRF_SPIS0_S_BASE 0x50008000UL 1992*150812a8SEvalZero #define NRF_TWIM0_S_BASE 0x50008000UL 1993*150812a8SEvalZero #define NRF_TWIS0_S_BASE 0x50008000UL 1994*150812a8SEvalZero #define NRF_UARTE0_S_BASE 0x50008000UL 1995*150812a8SEvalZero #define NRF_SPIM1_NS_BASE 0x40009000UL 1996*150812a8SEvalZero #define NRF_SPIS1_NS_BASE 0x40009000UL 1997*150812a8SEvalZero #define NRF_TWIM1_NS_BASE 0x40009000UL 1998*150812a8SEvalZero #define NRF_TWIS1_NS_BASE 0x40009000UL 1999*150812a8SEvalZero #define NRF_UARTE1_NS_BASE 0x40009000UL 2000*150812a8SEvalZero #define NRF_SPIM1_S_BASE 0x50009000UL 2001*150812a8SEvalZero #define NRF_SPIS1_S_BASE 0x50009000UL 2002*150812a8SEvalZero #define NRF_TWIM1_S_BASE 0x50009000UL 2003*150812a8SEvalZero #define NRF_TWIS1_S_BASE 0x50009000UL 2004*150812a8SEvalZero #define NRF_UARTE1_S_BASE 0x50009000UL 2005*150812a8SEvalZero #define NRF_SPIM2_NS_BASE 0x4000A000UL 2006*150812a8SEvalZero #define NRF_SPIS2_NS_BASE 0x4000A000UL 2007*150812a8SEvalZero #define NRF_TWIM2_NS_BASE 0x4000A000UL 2008*150812a8SEvalZero #define NRF_TWIS2_NS_BASE 0x4000A000UL 2009*150812a8SEvalZero #define NRF_UARTE2_NS_BASE 0x4000A000UL 2010*150812a8SEvalZero #define NRF_SPIM2_S_BASE 0x5000A000UL 2011*150812a8SEvalZero #define NRF_SPIS2_S_BASE 0x5000A000UL 2012*150812a8SEvalZero #define NRF_TWIM2_S_BASE 0x5000A000UL 2013*150812a8SEvalZero #define NRF_TWIS2_S_BASE 0x5000A000UL 2014*150812a8SEvalZero #define NRF_UARTE2_S_BASE 0x5000A000UL 2015*150812a8SEvalZero #define NRF_SPIM3_NS_BASE 0x4000B000UL 2016*150812a8SEvalZero #define NRF_SPIS3_NS_BASE 0x4000B000UL 2017*150812a8SEvalZero #define NRF_TWIM3_NS_BASE 0x4000B000UL 2018*150812a8SEvalZero #define NRF_TWIS3_NS_BASE 0x4000B000UL 2019*150812a8SEvalZero #define NRF_UARTE3_NS_BASE 0x4000B000UL 2020*150812a8SEvalZero #define NRF_SPIM3_S_BASE 0x5000B000UL 2021*150812a8SEvalZero #define NRF_SPIS3_S_BASE 0x5000B000UL 2022*150812a8SEvalZero #define NRF_TWIM3_S_BASE 0x5000B000UL 2023*150812a8SEvalZero #define NRF_TWIS3_S_BASE 0x5000B000UL 2024*150812a8SEvalZero #define NRF_UARTE3_S_BASE 0x5000B000UL 2025*150812a8SEvalZero #define NRF_GPIOTE0_S_BASE 0x5000D000UL 2026*150812a8SEvalZero #define NRF_SAADC_NS_BASE 0x4000E000UL 2027*150812a8SEvalZero #define NRF_SAADC_S_BASE 0x5000E000UL 2028*150812a8SEvalZero #define NRF_TIMER0_NS_BASE 0x4000F000UL 2029*150812a8SEvalZero #define NRF_TIMER0_S_BASE 0x5000F000UL 2030*150812a8SEvalZero #define NRF_TIMER1_NS_BASE 0x40010000UL 2031*150812a8SEvalZero #define NRF_TIMER1_S_BASE 0x50010000UL 2032*150812a8SEvalZero #define NRF_TIMER2_NS_BASE 0x40011000UL 2033*150812a8SEvalZero #define NRF_TIMER2_S_BASE 0x50011000UL 2034*150812a8SEvalZero #define NRF_RTC0_NS_BASE 0x40014000UL 2035*150812a8SEvalZero #define NRF_RTC0_S_BASE 0x50014000UL 2036*150812a8SEvalZero #define NRF_RTC1_NS_BASE 0x40015000UL 2037*150812a8SEvalZero #define NRF_RTC1_S_BASE 0x50015000UL 2038*150812a8SEvalZero #define NRF_DPPIC_NS_BASE 0x40017000UL 2039*150812a8SEvalZero #define NRF_DPPIC_S_BASE 0x50017000UL 2040*150812a8SEvalZero #define NRF_WDT_NS_BASE 0x40018000UL 2041*150812a8SEvalZero #define NRF_WDT_S_BASE 0x50018000UL 2042*150812a8SEvalZero #define NRF_EGU0_NS_BASE 0x4001B000UL 2043*150812a8SEvalZero #define NRF_EGU0_S_BASE 0x5001B000UL 2044*150812a8SEvalZero #define NRF_EGU1_NS_BASE 0x4001C000UL 2045*150812a8SEvalZero #define NRF_EGU1_S_BASE 0x5001C000UL 2046*150812a8SEvalZero #define NRF_EGU2_NS_BASE 0x4001D000UL 2047*150812a8SEvalZero #define NRF_EGU2_S_BASE 0x5001D000UL 2048*150812a8SEvalZero #define NRF_EGU3_NS_BASE 0x4001E000UL 2049*150812a8SEvalZero #define NRF_EGU3_S_BASE 0x5001E000UL 2050*150812a8SEvalZero #define NRF_EGU4_NS_BASE 0x4001F000UL 2051*150812a8SEvalZero #define NRF_EGU4_S_BASE 0x5001F000UL 2052*150812a8SEvalZero #define NRF_EGU5_NS_BASE 0x40020000UL 2053*150812a8SEvalZero #define NRF_EGU5_S_BASE 0x50020000UL 2054*150812a8SEvalZero #define NRF_PWM0_NS_BASE 0x40021000UL 2055*150812a8SEvalZero #define NRF_PWM0_S_BASE 0x50021000UL 2056*150812a8SEvalZero #define NRF_PWM1_NS_BASE 0x40022000UL 2057*150812a8SEvalZero #define NRF_PWM1_S_BASE 0x50022000UL 2058*150812a8SEvalZero #define NRF_PWM2_NS_BASE 0x40023000UL 2059*150812a8SEvalZero #define NRF_PWM2_S_BASE 0x50023000UL 2060*150812a8SEvalZero #define NRF_PWM3_NS_BASE 0x40024000UL 2061*150812a8SEvalZero #define NRF_PWM3_S_BASE 0x50024000UL 2062*150812a8SEvalZero #define NRF_PDM_NS_BASE 0x40026000UL 2063*150812a8SEvalZero #define NRF_PDM_S_BASE 0x50026000UL 2064*150812a8SEvalZero #define NRF_I2S_NS_BASE 0x40028000UL 2065*150812a8SEvalZero #define NRF_I2S_S_BASE 0x50028000UL 2066*150812a8SEvalZero #define NRF_IPC_NS_BASE 0x4002A000UL 2067*150812a8SEvalZero #define NRF_IPC_S_BASE 0x5002A000UL 2068*150812a8SEvalZero #define NRF_FPU_NS_BASE 0x4002C000UL 2069*150812a8SEvalZero #define NRF_FPU_S_BASE 0x5002C000UL 2070*150812a8SEvalZero #define NRF_GPIOTE1_NS_BASE 0x40031000UL 2071*150812a8SEvalZero #define NRF_KMU_NS_BASE 0x40039000UL 2072*150812a8SEvalZero #define NRF_NVMC_NS_BASE 0x40039000UL 2073*150812a8SEvalZero #define NRF_KMU_S_BASE 0x50039000UL 2074*150812a8SEvalZero #define NRF_NVMC_S_BASE 0x50039000UL 2075*150812a8SEvalZero #define NRF_VMC_NS_BASE 0x4003A000UL 2076*150812a8SEvalZero #define NRF_VMC_S_BASE 0x5003A000UL 2077*150812a8SEvalZero #define NRF_CRYPTOCELL_S_BASE 0x50840000UL 2078*150812a8SEvalZero #define NRF_P0_NS_BASE 0x40842500UL 2079*150812a8SEvalZero #define NRF_P0_S_BASE 0x50842500UL 2080*150812a8SEvalZero 2081*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 2082*150812a8SEvalZero 2083*150812a8SEvalZero 2084*150812a8SEvalZero /* =========================================================================================================================== */ 2085*150812a8SEvalZero /* ================ Peripheral declaration ================ */ 2086*150812a8SEvalZero /* =========================================================================================================================== */ 2087*150812a8SEvalZero 2088*150812a8SEvalZero 2089*150812a8SEvalZero /** @addtogroup Device_Peripheral_declaration 2090*150812a8SEvalZero * @{ 2091*150812a8SEvalZero */ 2092*150812a8SEvalZero 2093*150812a8SEvalZero #define NRF_FICR_S ((NRF_FICR_Type*) NRF_FICR_S_BASE) 2094*150812a8SEvalZero #define NRF_UICR_S ((NRF_UICR_Type*) NRF_UICR_S_BASE) 2095*150812a8SEvalZero #define NRF_TAD_S ((NRF_TAD_Type*) NRF_TAD_S_BASE) 2096*150812a8SEvalZero #define NRF_SPU_S ((NRF_SPU_Type*) NRF_SPU_S_BASE) 2097*150812a8SEvalZero #define NRF_REGULATORS_NS ((NRF_REGULATORS_Type*) NRF_REGULATORS_NS_BASE) 2098*150812a8SEvalZero #define NRF_REGULATORS_S ((NRF_REGULATORS_Type*) NRF_REGULATORS_S_BASE) 2099*150812a8SEvalZero #define NRF_CLOCK_NS ((NRF_CLOCK_Type*) NRF_CLOCK_NS_BASE) 2100*150812a8SEvalZero #define NRF_POWER_NS ((NRF_POWER_Type*) NRF_POWER_NS_BASE) 2101*150812a8SEvalZero #define NRF_CLOCK_S ((NRF_CLOCK_Type*) NRF_CLOCK_S_BASE) 2102*150812a8SEvalZero #define NRF_POWER_S ((NRF_POWER_Type*) NRF_POWER_S_BASE) 2103*150812a8SEvalZero #define NRF_CTRL_AP_PERI_S ((NRF_CTRLAPPERI_Type*) NRF_CTRL_AP_PERI_S_BASE) 2104*150812a8SEvalZero #define NRF_SPIM0_NS ((NRF_SPIM_Type*) NRF_SPIM0_NS_BASE) 2105*150812a8SEvalZero #define NRF_SPIS0_NS ((NRF_SPIS_Type*) NRF_SPIS0_NS_BASE) 2106*150812a8SEvalZero #define NRF_TWIM0_NS ((NRF_TWIM_Type*) NRF_TWIM0_NS_BASE) 2107*150812a8SEvalZero #define NRF_TWIS0_NS ((NRF_TWIS_Type*) NRF_TWIS0_NS_BASE) 2108*150812a8SEvalZero #define NRF_UARTE0_NS ((NRF_UARTE_Type*) NRF_UARTE0_NS_BASE) 2109*150812a8SEvalZero #define NRF_SPIM0_S ((NRF_SPIM_Type*) NRF_SPIM0_S_BASE) 2110*150812a8SEvalZero #define NRF_SPIS0_S ((NRF_SPIS_Type*) NRF_SPIS0_S_BASE) 2111*150812a8SEvalZero #define NRF_TWIM0_S ((NRF_TWIM_Type*) NRF_TWIM0_S_BASE) 2112*150812a8SEvalZero #define NRF_TWIS0_S ((NRF_TWIS_Type*) NRF_TWIS0_S_BASE) 2113*150812a8SEvalZero #define NRF_UARTE0_S ((NRF_UARTE_Type*) NRF_UARTE0_S_BASE) 2114*150812a8SEvalZero #define NRF_SPIM1_NS ((NRF_SPIM_Type*) NRF_SPIM1_NS_BASE) 2115*150812a8SEvalZero #define NRF_SPIS1_NS ((NRF_SPIS_Type*) NRF_SPIS1_NS_BASE) 2116*150812a8SEvalZero #define NRF_TWIM1_NS ((NRF_TWIM_Type*) NRF_TWIM1_NS_BASE) 2117*150812a8SEvalZero #define NRF_TWIS1_NS ((NRF_TWIS_Type*) NRF_TWIS1_NS_BASE) 2118*150812a8SEvalZero #define NRF_UARTE1_NS ((NRF_UARTE_Type*) NRF_UARTE1_NS_BASE) 2119*150812a8SEvalZero #define NRF_SPIM1_S ((NRF_SPIM_Type*) NRF_SPIM1_S_BASE) 2120*150812a8SEvalZero #define NRF_SPIS1_S ((NRF_SPIS_Type*) NRF_SPIS1_S_BASE) 2121*150812a8SEvalZero #define NRF_TWIM1_S ((NRF_TWIM_Type*) NRF_TWIM1_S_BASE) 2122*150812a8SEvalZero #define NRF_TWIS1_S ((NRF_TWIS_Type*) NRF_TWIS1_S_BASE) 2123*150812a8SEvalZero #define NRF_UARTE1_S ((NRF_UARTE_Type*) NRF_UARTE1_S_BASE) 2124*150812a8SEvalZero #define NRF_SPIM2_NS ((NRF_SPIM_Type*) NRF_SPIM2_NS_BASE) 2125*150812a8SEvalZero #define NRF_SPIS2_NS ((NRF_SPIS_Type*) NRF_SPIS2_NS_BASE) 2126*150812a8SEvalZero #define NRF_TWIM2_NS ((NRF_TWIM_Type*) NRF_TWIM2_NS_BASE) 2127*150812a8SEvalZero #define NRF_TWIS2_NS ((NRF_TWIS_Type*) NRF_TWIS2_NS_BASE) 2128*150812a8SEvalZero #define NRF_UARTE2_NS ((NRF_UARTE_Type*) NRF_UARTE2_NS_BASE) 2129*150812a8SEvalZero #define NRF_SPIM2_S ((NRF_SPIM_Type*) NRF_SPIM2_S_BASE) 2130*150812a8SEvalZero #define NRF_SPIS2_S ((NRF_SPIS_Type*) NRF_SPIS2_S_BASE) 2131*150812a8SEvalZero #define NRF_TWIM2_S ((NRF_TWIM_Type*) NRF_TWIM2_S_BASE) 2132*150812a8SEvalZero #define NRF_TWIS2_S ((NRF_TWIS_Type*) NRF_TWIS2_S_BASE) 2133*150812a8SEvalZero #define NRF_UARTE2_S ((NRF_UARTE_Type*) NRF_UARTE2_S_BASE) 2134*150812a8SEvalZero #define NRF_SPIM3_NS ((NRF_SPIM_Type*) NRF_SPIM3_NS_BASE) 2135*150812a8SEvalZero #define NRF_SPIS3_NS ((NRF_SPIS_Type*) NRF_SPIS3_NS_BASE) 2136*150812a8SEvalZero #define NRF_TWIM3_NS ((NRF_TWIM_Type*) NRF_TWIM3_NS_BASE) 2137*150812a8SEvalZero #define NRF_TWIS3_NS ((NRF_TWIS_Type*) NRF_TWIS3_NS_BASE) 2138*150812a8SEvalZero #define NRF_UARTE3_NS ((NRF_UARTE_Type*) NRF_UARTE3_NS_BASE) 2139*150812a8SEvalZero #define NRF_SPIM3_S ((NRF_SPIM_Type*) NRF_SPIM3_S_BASE) 2140*150812a8SEvalZero #define NRF_SPIS3_S ((NRF_SPIS_Type*) NRF_SPIS3_S_BASE) 2141*150812a8SEvalZero #define NRF_TWIM3_S ((NRF_TWIM_Type*) NRF_TWIM3_S_BASE) 2142*150812a8SEvalZero #define NRF_TWIS3_S ((NRF_TWIS_Type*) NRF_TWIS3_S_BASE) 2143*150812a8SEvalZero #define NRF_UARTE3_S ((NRF_UARTE_Type*) NRF_UARTE3_S_BASE) 2144*150812a8SEvalZero #define NRF_GPIOTE0_S ((NRF_GPIOTE_Type*) NRF_GPIOTE0_S_BASE) 2145*150812a8SEvalZero #define NRF_SAADC_NS ((NRF_SAADC_Type*) NRF_SAADC_NS_BASE) 2146*150812a8SEvalZero #define NRF_SAADC_S ((NRF_SAADC_Type*) NRF_SAADC_S_BASE) 2147*150812a8SEvalZero #define NRF_TIMER0_NS ((NRF_TIMER_Type*) NRF_TIMER0_NS_BASE) 2148*150812a8SEvalZero #define NRF_TIMER0_S ((NRF_TIMER_Type*) NRF_TIMER0_S_BASE) 2149*150812a8SEvalZero #define NRF_TIMER1_NS ((NRF_TIMER_Type*) NRF_TIMER1_NS_BASE) 2150*150812a8SEvalZero #define NRF_TIMER1_S ((NRF_TIMER_Type*) NRF_TIMER1_S_BASE) 2151*150812a8SEvalZero #define NRF_TIMER2_NS ((NRF_TIMER_Type*) NRF_TIMER2_NS_BASE) 2152*150812a8SEvalZero #define NRF_TIMER2_S ((NRF_TIMER_Type*) NRF_TIMER2_S_BASE) 2153*150812a8SEvalZero #define NRF_RTC0_NS ((NRF_RTC_Type*) NRF_RTC0_NS_BASE) 2154*150812a8SEvalZero #define NRF_RTC0_S ((NRF_RTC_Type*) NRF_RTC0_S_BASE) 2155*150812a8SEvalZero #define NRF_RTC1_NS ((NRF_RTC_Type*) NRF_RTC1_NS_BASE) 2156*150812a8SEvalZero #define NRF_RTC1_S ((NRF_RTC_Type*) NRF_RTC1_S_BASE) 2157*150812a8SEvalZero #define NRF_DPPIC_NS ((NRF_DPPIC_Type*) NRF_DPPIC_NS_BASE) 2158*150812a8SEvalZero #define NRF_DPPIC_S ((NRF_DPPIC_Type*) NRF_DPPIC_S_BASE) 2159*150812a8SEvalZero #define NRF_WDT_NS ((NRF_WDT_Type*) NRF_WDT_NS_BASE) 2160*150812a8SEvalZero #define NRF_WDT_S ((NRF_WDT_Type*) NRF_WDT_S_BASE) 2161*150812a8SEvalZero #define NRF_EGU0_NS ((NRF_EGU_Type*) NRF_EGU0_NS_BASE) 2162*150812a8SEvalZero #define NRF_EGU0_S ((NRF_EGU_Type*) NRF_EGU0_S_BASE) 2163*150812a8SEvalZero #define NRF_EGU1_NS ((NRF_EGU_Type*) NRF_EGU1_NS_BASE) 2164*150812a8SEvalZero #define NRF_EGU1_S ((NRF_EGU_Type*) NRF_EGU1_S_BASE) 2165*150812a8SEvalZero #define NRF_EGU2_NS ((NRF_EGU_Type*) NRF_EGU2_NS_BASE) 2166*150812a8SEvalZero #define NRF_EGU2_S ((NRF_EGU_Type*) NRF_EGU2_S_BASE) 2167*150812a8SEvalZero #define NRF_EGU3_NS ((NRF_EGU_Type*) NRF_EGU3_NS_BASE) 2168*150812a8SEvalZero #define NRF_EGU3_S ((NRF_EGU_Type*) NRF_EGU3_S_BASE) 2169*150812a8SEvalZero #define NRF_EGU4_NS ((NRF_EGU_Type*) NRF_EGU4_NS_BASE) 2170*150812a8SEvalZero #define NRF_EGU4_S ((NRF_EGU_Type*) NRF_EGU4_S_BASE) 2171*150812a8SEvalZero #define NRF_EGU5_NS ((NRF_EGU_Type*) NRF_EGU5_NS_BASE) 2172*150812a8SEvalZero #define NRF_EGU5_S ((NRF_EGU_Type*) NRF_EGU5_S_BASE) 2173*150812a8SEvalZero #define NRF_PWM0_NS ((NRF_PWM_Type*) NRF_PWM0_NS_BASE) 2174*150812a8SEvalZero #define NRF_PWM0_S ((NRF_PWM_Type*) NRF_PWM0_S_BASE) 2175*150812a8SEvalZero #define NRF_PWM1_NS ((NRF_PWM_Type*) NRF_PWM1_NS_BASE) 2176*150812a8SEvalZero #define NRF_PWM1_S ((NRF_PWM_Type*) NRF_PWM1_S_BASE) 2177*150812a8SEvalZero #define NRF_PWM2_NS ((NRF_PWM_Type*) NRF_PWM2_NS_BASE) 2178*150812a8SEvalZero #define NRF_PWM2_S ((NRF_PWM_Type*) NRF_PWM2_S_BASE) 2179*150812a8SEvalZero #define NRF_PWM3_NS ((NRF_PWM_Type*) NRF_PWM3_NS_BASE) 2180*150812a8SEvalZero #define NRF_PWM3_S ((NRF_PWM_Type*) NRF_PWM3_S_BASE) 2181*150812a8SEvalZero #define NRF_PDM_NS ((NRF_PDM_Type*) NRF_PDM_NS_BASE) 2182*150812a8SEvalZero #define NRF_PDM_S ((NRF_PDM_Type*) NRF_PDM_S_BASE) 2183*150812a8SEvalZero #define NRF_I2S_NS ((NRF_I2S_Type*) NRF_I2S_NS_BASE) 2184*150812a8SEvalZero #define NRF_I2S_S ((NRF_I2S_Type*) NRF_I2S_S_BASE) 2185*150812a8SEvalZero #define NRF_IPC_NS ((NRF_IPC_Type*) NRF_IPC_NS_BASE) 2186*150812a8SEvalZero #define NRF_IPC_S ((NRF_IPC_Type*) NRF_IPC_S_BASE) 2187*150812a8SEvalZero #define NRF_FPU_NS ((NRF_FPU_Type*) NRF_FPU_NS_BASE) 2188*150812a8SEvalZero #define NRF_FPU_S ((NRF_FPU_Type*) NRF_FPU_S_BASE) 2189*150812a8SEvalZero #define NRF_GPIOTE1_NS ((NRF_GPIOTE_Type*) NRF_GPIOTE1_NS_BASE) 2190*150812a8SEvalZero #define NRF_KMU_NS ((NRF_KMU_Type*) NRF_KMU_NS_BASE) 2191*150812a8SEvalZero #define NRF_NVMC_NS ((NRF_NVMC_Type*) NRF_NVMC_NS_BASE) 2192*150812a8SEvalZero #define NRF_KMU_S ((NRF_KMU_Type*) NRF_KMU_S_BASE) 2193*150812a8SEvalZero #define NRF_NVMC_S ((NRF_NVMC_Type*) NRF_NVMC_S_BASE) 2194*150812a8SEvalZero #define NRF_VMC_NS ((NRF_VMC_Type*) NRF_VMC_NS_BASE) 2195*150812a8SEvalZero #define NRF_VMC_S ((NRF_VMC_Type*) NRF_VMC_S_BASE) 2196*150812a8SEvalZero #define NRF_CRYPTOCELL_S ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_S_BASE) 2197*150812a8SEvalZero #define NRF_P0_NS ((NRF_GPIO_Type*) NRF_P0_NS_BASE) 2198*150812a8SEvalZero #define NRF_P0_S ((NRF_GPIO_Type*) NRF_P0_S_BASE) 2199*150812a8SEvalZero 2200*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_declaration */ 2201*150812a8SEvalZero 2202*150812a8SEvalZero 2203*150812a8SEvalZero #ifdef __cplusplus 2204*150812a8SEvalZero } 2205*150812a8SEvalZero #endif 2206*150812a8SEvalZero 2207*150812a8SEvalZero #endif /* NRF9160_H */ 2208*150812a8SEvalZero 2209*150812a8SEvalZero 2210*150812a8SEvalZero /** @} */ /* End of group nrf9160 */ 2211*150812a8SEvalZero 2212*150812a8SEvalZero /** @} */ /* End of group Nordic Semiconductor */ 2213