1*150812a8SEvalZero /* 2*150812a8SEvalZero * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. 3*150812a8SEvalZero * 4*150812a8SEvalZero * Redistribution and use in source and binary forms, with or without 5*150812a8SEvalZero * modification, are permitted provided that the following conditions are met: 6*150812a8SEvalZero * 7*150812a8SEvalZero * 1. Redistributions of source code must retain the above copyright notice, this 8*150812a8SEvalZero * list of conditions and the following disclaimer. 9*150812a8SEvalZero * 10*150812a8SEvalZero * 2. Redistributions in binary form must reproduce the above copyright 11*150812a8SEvalZero * notice, this list of conditions and the following disclaimer in the 12*150812a8SEvalZero * documentation and/or other materials provided with the distribution. 13*150812a8SEvalZero * 14*150812a8SEvalZero * 3. Neither the name of Nordic Semiconductor ASA nor the names of its 15*150812a8SEvalZero * contributors may be used to endorse or promote products derived from this 16*150812a8SEvalZero * software without specific prior written permission. 17*150812a8SEvalZero * 18*150812a8SEvalZero * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*150812a8SEvalZero * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*150812a8SEvalZero * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 21*150812a8SEvalZero * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 22*150812a8SEvalZero * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*150812a8SEvalZero * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*150812a8SEvalZero * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*150812a8SEvalZero * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*150812a8SEvalZero * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*150812a8SEvalZero * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*150812a8SEvalZero * POSSIBILITY OF SUCH DAMAGE. 29*150812a8SEvalZero * 30*150812a8SEvalZero * @file nrf52840.h 31*150812a8SEvalZero * @brief CMSIS HeaderFile 32*150812a8SEvalZero * @version 1 33*150812a8SEvalZero * @date 03. December 2018 34*150812a8SEvalZero * @note Generated by SVDConv V3.3.18 on Monday, 03.12.2018 11:18:25 35*150812a8SEvalZero * from File 'nrf52840.svd', 36*150812a8SEvalZero * last modified on Monday, 03.12.2018 10:18:21 37*150812a8SEvalZero */ 38*150812a8SEvalZero 39*150812a8SEvalZero 40*150812a8SEvalZero 41*150812a8SEvalZero /** @addtogroup Nordic Semiconductor 42*150812a8SEvalZero * @{ 43*150812a8SEvalZero */ 44*150812a8SEvalZero 45*150812a8SEvalZero 46*150812a8SEvalZero /** @addtogroup nrf52840 47*150812a8SEvalZero * @{ 48*150812a8SEvalZero */ 49*150812a8SEvalZero 50*150812a8SEvalZero 51*150812a8SEvalZero #ifndef NRF52840_H 52*150812a8SEvalZero #define NRF52840_H 53*150812a8SEvalZero 54*150812a8SEvalZero #ifdef __cplusplus 55*150812a8SEvalZero extern "C" { 56*150812a8SEvalZero #endif 57*150812a8SEvalZero 58*150812a8SEvalZero 59*150812a8SEvalZero /** @addtogroup Configuration_of_CMSIS 60*150812a8SEvalZero * @{ 61*150812a8SEvalZero */ 62*150812a8SEvalZero 63*150812a8SEvalZero 64*150812a8SEvalZero 65*150812a8SEvalZero /* =========================================================================================================================== */ 66*150812a8SEvalZero /* ================ Interrupt Number Definition ================ */ 67*150812a8SEvalZero /* =========================================================================================================================== */ 68*150812a8SEvalZero 69*150812a8SEvalZero typedef enum { 70*150812a8SEvalZero /* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ 71*150812a8SEvalZero Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 72*150812a8SEvalZero NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 73*150812a8SEvalZero HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 74*150812a8SEvalZero MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 75*150812a8SEvalZero and No Match */ 76*150812a8SEvalZero BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 77*150812a8SEvalZero related Fault */ 78*150812a8SEvalZero UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 79*150812a8SEvalZero SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 80*150812a8SEvalZero DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 81*150812a8SEvalZero PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 82*150812a8SEvalZero SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 83*150812a8SEvalZero /* ========================================== nrf52840 Specific Interrupt Numbers ========================================== */ 84*150812a8SEvalZero POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 85*150812a8SEvalZero RADIO_IRQn = 1, /*!< 1 RADIO */ 86*150812a8SEvalZero UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ 87*150812a8SEvalZero SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ 88*150812a8SEvalZero SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ 89*150812a8SEvalZero NFCT_IRQn = 5, /*!< 5 NFCT */ 90*150812a8SEvalZero GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 91*150812a8SEvalZero SAADC_IRQn = 7, /*!< 7 SAADC */ 92*150812a8SEvalZero TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 93*150812a8SEvalZero TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 94*150812a8SEvalZero TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 95*150812a8SEvalZero RTC0_IRQn = 11, /*!< 11 RTC0 */ 96*150812a8SEvalZero TEMP_IRQn = 12, /*!< 12 TEMP */ 97*150812a8SEvalZero RNG_IRQn = 13, /*!< 13 RNG */ 98*150812a8SEvalZero ECB_IRQn = 14, /*!< 14 ECB */ 99*150812a8SEvalZero CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 100*150812a8SEvalZero WDT_IRQn = 16, /*!< 16 WDT */ 101*150812a8SEvalZero RTC1_IRQn = 17, /*!< 17 RTC1 */ 102*150812a8SEvalZero QDEC_IRQn = 18, /*!< 18 QDEC */ 103*150812a8SEvalZero COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ 104*150812a8SEvalZero SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ 105*150812a8SEvalZero SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ 106*150812a8SEvalZero SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ 107*150812a8SEvalZero SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ 108*150812a8SEvalZero SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ 109*150812a8SEvalZero SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ 110*150812a8SEvalZero TIMER3_IRQn = 26, /*!< 26 TIMER3 */ 111*150812a8SEvalZero TIMER4_IRQn = 27, /*!< 27 TIMER4 */ 112*150812a8SEvalZero PWM0_IRQn = 28, /*!< 28 PWM0 */ 113*150812a8SEvalZero PDM_IRQn = 29, /*!< 29 PDM */ 114*150812a8SEvalZero MWU_IRQn = 32, /*!< 32 MWU */ 115*150812a8SEvalZero PWM1_IRQn = 33, /*!< 33 PWM1 */ 116*150812a8SEvalZero PWM2_IRQn = 34, /*!< 34 PWM2 */ 117*150812a8SEvalZero SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ 118*150812a8SEvalZero RTC2_IRQn = 36, /*!< 36 RTC2 */ 119*150812a8SEvalZero I2S_IRQn = 37, /*!< 37 I2S */ 120*150812a8SEvalZero FPU_IRQn = 38, /*!< 38 FPU */ 121*150812a8SEvalZero USBD_IRQn = 39, /*!< 39 USBD */ 122*150812a8SEvalZero UARTE1_IRQn = 40, /*!< 40 UARTE1 */ 123*150812a8SEvalZero QSPI_IRQn = 41, /*!< 41 QSPI */ 124*150812a8SEvalZero CRYPTOCELL_IRQn = 42, /*!< 42 CRYPTOCELL */ 125*150812a8SEvalZero PWM3_IRQn = 45, /*!< 45 PWM3 */ 126*150812a8SEvalZero SPIM3_IRQn = 47 /*!< 47 SPIM3 */ 127*150812a8SEvalZero } IRQn_Type; 128*150812a8SEvalZero 129*150812a8SEvalZero 130*150812a8SEvalZero 131*150812a8SEvalZero /* =========================================================================================================================== */ 132*150812a8SEvalZero /* ================ Processor and Core Peripheral Section ================ */ 133*150812a8SEvalZero /* =========================================================================================================================== */ 134*150812a8SEvalZero 135*150812a8SEvalZero /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ 136*150812a8SEvalZero #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 137*150812a8SEvalZero #define __DSP_PRESENT 0 /*!< DSP present or not */ 138*150812a8SEvalZero #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 139*150812a8SEvalZero #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 140*150812a8SEvalZero #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 141*150812a8SEvalZero #define __MPU_PRESENT 1 /*!< MPU present or not */ 142*150812a8SEvalZero #define __FPU_PRESENT 1 /*!< FPU present or not */ 143*150812a8SEvalZero 144*150812a8SEvalZero 145*150812a8SEvalZero /** @} */ /* End of group Configuration_of_CMSIS */ 146*150812a8SEvalZero 147*150812a8SEvalZero #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 148*150812a8SEvalZero #include "system_nrf52840.h" /*!< nrf52840 System */ 149*150812a8SEvalZero 150*150812a8SEvalZero #ifndef __IM /*!< Fallback for older CMSIS versions */ 151*150812a8SEvalZero #define __IM __I 152*150812a8SEvalZero #endif 153*150812a8SEvalZero #ifndef __OM /*!< Fallback for older CMSIS versions */ 154*150812a8SEvalZero #define __OM __O 155*150812a8SEvalZero #endif 156*150812a8SEvalZero #ifndef __IOM /*!< Fallback for older CMSIS versions */ 157*150812a8SEvalZero #define __IOM __IO 158*150812a8SEvalZero #endif 159*150812a8SEvalZero 160*150812a8SEvalZero 161*150812a8SEvalZero /* ======================================== Start of section using anonymous unions ======================================== */ 162*150812a8SEvalZero #if defined (__CC_ARM) 163*150812a8SEvalZero #pragma push 164*150812a8SEvalZero #pragma anon_unions 165*150812a8SEvalZero #elif defined (__ICCARM__) 166*150812a8SEvalZero #pragma language=extended 167*150812a8SEvalZero #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 168*150812a8SEvalZero #pragma clang diagnostic push 169*150812a8SEvalZero #pragma clang diagnostic ignored "-Wc11-extensions" 170*150812a8SEvalZero #pragma clang diagnostic ignored "-Wreserved-id-macro" 171*150812a8SEvalZero #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 172*150812a8SEvalZero #pragma clang diagnostic ignored "-Wnested-anon-types" 173*150812a8SEvalZero #elif defined (__GNUC__) 174*150812a8SEvalZero /* anonymous unions are enabled by default */ 175*150812a8SEvalZero #elif defined (__TMS470__) 176*150812a8SEvalZero /* anonymous unions are enabled by default */ 177*150812a8SEvalZero #elif defined (__TASKING__) 178*150812a8SEvalZero #pragma warning 586 179*150812a8SEvalZero #elif defined (__CSMC__) 180*150812a8SEvalZero /* anonymous unions are enabled by default */ 181*150812a8SEvalZero #else 182*150812a8SEvalZero #warning Not supported compiler type 183*150812a8SEvalZero #endif 184*150812a8SEvalZero 185*150812a8SEvalZero 186*150812a8SEvalZero /* =========================================================================================================================== */ 187*150812a8SEvalZero /* ================ Device Specific Cluster Section ================ */ 188*150812a8SEvalZero /* =========================================================================================================================== */ 189*150812a8SEvalZero 190*150812a8SEvalZero 191*150812a8SEvalZero /** @addtogroup Device_Peripheral_clusters 192*150812a8SEvalZero * @{ 193*150812a8SEvalZero */ 194*150812a8SEvalZero 195*150812a8SEvalZero 196*150812a8SEvalZero /** 197*150812a8SEvalZero * @brief FICR_INFO [INFO] (Device info) 198*150812a8SEvalZero */ 199*150812a8SEvalZero typedef struct { 200*150812a8SEvalZero __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ 201*150812a8SEvalZero __IM uint32_t VARIANT; /*!< (@ 0x00000004) Build code (hardware version and production configuration) */ 202*150812a8SEvalZero __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ 203*150812a8SEvalZero __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ 204*150812a8SEvalZero __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ 205*150812a8SEvalZero __IOM uint32_t UNUSED8[3]; /*!< (@ 0x00000014) Unspecified */ 206*150812a8SEvalZero } FICR_INFO_Type; /*!< Size = 32 (0x20) */ 207*150812a8SEvalZero 208*150812a8SEvalZero 209*150812a8SEvalZero /** 210*150812a8SEvalZero * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) 211*150812a8SEvalZero */ 212*150812a8SEvalZero typedef struct { 213*150812a8SEvalZero __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ 214*150812a8SEvalZero __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ 215*150812a8SEvalZero __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ 216*150812a8SEvalZero __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ 217*150812a8SEvalZero __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ 218*150812a8SEvalZero __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ 219*150812a8SEvalZero __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ 220*150812a8SEvalZero __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ 221*150812a8SEvalZero __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ 222*150812a8SEvalZero __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ 223*150812a8SEvalZero __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ 224*150812a8SEvalZero __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ 225*150812a8SEvalZero __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ 226*150812a8SEvalZero __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ 227*150812a8SEvalZero __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ 228*150812a8SEvalZero __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ 229*150812a8SEvalZero __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ 230*150812a8SEvalZero } FICR_TEMP_Type; /*!< Size = 68 (0x44) */ 231*150812a8SEvalZero 232*150812a8SEvalZero 233*150812a8SEvalZero /** 234*150812a8SEvalZero * @brief FICR_NFC [NFC] (Unspecified) 235*150812a8SEvalZero */ 236*150812a8SEvalZero typedef struct { 237*150812a8SEvalZero __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC tag. Software can read 238*150812a8SEvalZero these values to populate NFCID1_3RD_LAST, 239*150812a8SEvalZero NFCID1_2ND_LAST and NFCID1_LAST. */ 240*150812a8SEvalZero __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC tag. Software can read 241*150812a8SEvalZero these values to populate NFCID1_3RD_LAST, 242*150812a8SEvalZero NFCID1_2ND_LAST and NFCID1_LAST. */ 243*150812a8SEvalZero __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC tag. Software can read 244*150812a8SEvalZero these values to populate NFCID1_3RD_LAST, 245*150812a8SEvalZero NFCID1_2ND_LAST and NFCID1_LAST. */ 246*150812a8SEvalZero __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC tag. Software can read 247*150812a8SEvalZero these values to populate NFCID1_3RD_LAST, 248*150812a8SEvalZero NFCID1_2ND_LAST and NFCID1_LAST. */ 249*150812a8SEvalZero } FICR_NFC_Type; /*!< Size = 16 (0x10) */ 250*150812a8SEvalZero 251*150812a8SEvalZero 252*150812a8SEvalZero /** 253*150812a8SEvalZero * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) 254*150812a8SEvalZero */ 255*150812a8SEvalZero typedef struct { 256*150812a8SEvalZero __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ 257*150812a8SEvalZero __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ 258*150812a8SEvalZero __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ 259*150812a8SEvalZero __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ 260*150812a8SEvalZero __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ 261*150812a8SEvalZero __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ 262*150812a8SEvalZero __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ 263*150812a8SEvalZero __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ 264*150812a8SEvalZero } FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ 265*150812a8SEvalZero 266*150812a8SEvalZero 267*150812a8SEvalZero /** 268*150812a8SEvalZero * @brief POWER_RAM [RAM] (Unspecified) 269*150812a8SEvalZero */ 270*150812a8SEvalZero typedef struct { 271*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[n]: RAMn power control register */ 272*150812a8SEvalZero __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[n]: RAMn power control set 273*150812a8SEvalZero register */ 274*150812a8SEvalZero __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[n]: RAMn power control clear 275*150812a8SEvalZero register */ 276*150812a8SEvalZero __IM uint32_t RESERVED; 277*150812a8SEvalZero } POWER_RAM_Type; /*!< Size = 16 (0x10) */ 278*150812a8SEvalZero 279*150812a8SEvalZero 280*150812a8SEvalZero /** 281*150812a8SEvalZero * @brief UART_PSEL [PSEL] (Unspecified) 282*150812a8SEvalZero */ 283*150812a8SEvalZero typedef struct { 284*150812a8SEvalZero __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ 285*150812a8SEvalZero __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ 286*150812a8SEvalZero __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ 287*150812a8SEvalZero __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ 288*150812a8SEvalZero } UART_PSEL_Type; /*!< Size = 16 (0x10) */ 289*150812a8SEvalZero 290*150812a8SEvalZero 291*150812a8SEvalZero /** 292*150812a8SEvalZero * @brief UARTE_PSEL [PSEL] (Unspecified) 293*150812a8SEvalZero */ 294*150812a8SEvalZero typedef struct { 295*150812a8SEvalZero __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 296*150812a8SEvalZero __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 297*150812a8SEvalZero __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 298*150812a8SEvalZero __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 299*150812a8SEvalZero } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 300*150812a8SEvalZero 301*150812a8SEvalZero 302*150812a8SEvalZero /** 303*150812a8SEvalZero * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 304*150812a8SEvalZero */ 305*150812a8SEvalZero typedef struct { 306*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 307*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 308*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 309*150812a8SEvalZero } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 310*150812a8SEvalZero 311*150812a8SEvalZero 312*150812a8SEvalZero /** 313*150812a8SEvalZero * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 314*150812a8SEvalZero */ 315*150812a8SEvalZero typedef struct { 316*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 317*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 318*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 319*150812a8SEvalZero } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 320*150812a8SEvalZero 321*150812a8SEvalZero 322*150812a8SEvalZero /** 323*150812a8SEvalZero * @brief SPI_PSEL [PSEL] (Unspecified) 324*150812a8SEvalZero */ 325*150812a8SEvalZero typedef struct { 326*150812a8SEvalZero __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 327*150812a8SEvalZero __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 328*150812a8SEvalZero __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 329*150812a8SEvalZero } SPI_PSEL_Type; /*!< Size = 12 (0xc) */ 330*150812a8SEvalZero 331*150812a8SEvalZero 332*150812a8SEvalZero /** 333*150812a8SEvalZero * @brief SPIM_PSEL [PSEL] (Unspecified) 334*150812a8SEvalZero */ 335*150812a8SEvalZero typedef struct { 336*150812a8SEvalZero __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 337*150812a8SEvalZero __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 338*150812a8SEvalZero __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 339*150812a8SEvalZero __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN */ 340*150812a8SEvalZero } SPIM_PSEL_Type; /*!< Size = 16 (0x10) */ 341*150812a8SEvalZero 342*150812a8SEvalZero 343*150812a8SEvalZero /** 344*150812a8SEvalZero * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 345*150812a8SEvalZero */ 346*150812a8SEvalZero typedef struct { 347*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 348*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 349*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 350*150812a8SEvalZero __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 351*150812a8SEvalZero } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 352*150812a8SEvalZero 353*150812a8SEvalZero 354*150812a8SEvalZero /** 355*150812a8SEvalZero * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 356*150812a8SEvalZero */ 357*150812a8SEvalZero typedef struct { 358*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 359*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of bytes in transmit buffer */ 360*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 361*150812a8SEvalZero __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 362*150812a8SEvalZero } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 363*150812a8SEvalZero 364*150812a8SEvalZero 365*150812a8SEvalZero /** 366*150812a8SEvalZero * @brief SPIM_IFTIMING [IFTIMING] (Unspecified) 367*150812a8SEvalZero */ 368*150812a8SEvalZero typedef struct { 369*150812a8SEvalZero __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on MISO */ 370*150812a8SEvalZero __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge 371*150812a8SEvalZero of SCK and minimum duration CSN must stay 372*150812a8SEvalZero high between transactions */ 373*150812a8SEvalZero } SPIM_IFTIMING_Type; /*!< Size = 8 (0x8) */ 374*150812a8SEvalZero 375*150812a8SEvalZero 376*150812a8SEvalZero /** 377*150812a8SEvalZero * @brief SPIS_PSEL [PSEL] (Unspecified) 378*150812a8SEvalZero */ 379*150812a8SEvalZero typedef struct { 380*150812a8SEvalZero __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 381*150812a8SEvalZero __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 382*150812a8SEvalZero __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 383*150812a8SEvalZero __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 384*150812a8SEvalZero } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 385*150812a8SEvalZero 386*150812a8SEvalZero 387*150812a8SEvalZero /** 388*150812a8SEvalZero * @brief SPIS_RXD [RXD] (Unspecified) 389*150812a8SEvalZero */ 390*150812a8SEvalZero typedef struct { 391*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 392*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 393*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 394*150812a8SEvalZero } SPIS_RXD_Type; /*!< Size = 12 (0xc) */ 395*150812a8SEvalZero 396*150812a8SEvalZero 397*150812a8SEvalZero /** 398*150812a8SEvalZero * @brief SPIS_TXD [TXD] (Unspecified) 399*150812a8SEvalZero */ 400*150812a8SEvalZero typedef struct { 401*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 402*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 403*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 404*150812a8SEvalZero } SPIS_TXD_Type; /*!< Size = 12 (0xc) */ 405*150812a8SEvalZero 406*150812a8SEvalZero 407*150812a8SEvalZero /** 408*150812a8SEvalZero * @brief TWI_PSEL [PSEL] (Unspecified) 409*150812a8SEvalZero */ 410*150812a8SEvalZero typedef struct { 411*150812a8SEvalZero __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */ 412*150812a8SEvalZero __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */ 413*150812a8SEvalZero } TWI_PSEL_Type; /*!< Size = 8 (0x8) */ 414*150812a8SEvalZero 415*150812a8SEvalZero 416*150812a8SEvalZero /** 417*150812a8SEvalZero * @brief TWIM_PSEL [PSEL] (Unspecified) 418*150812a8SEvalZero */ 419*150812a8SEvalZero typedef struct { 420*150812a8SEvalZero __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 421*150812a8SEvalZero __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 422*150812a8SEvalZero } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 423*150812a8SEvalZero 424*150812a8SEvalZero 425*150812a8SEvalZero /** 426*150812a8SEvalZero * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 427*150812a8SEvalZero */ 428*150812a8SEvalZero typedef struct { 429*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 430*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 431*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 432*150812a8SEvalZero __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 433*150812a8SEvalZero } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 434*150812a8SEvalZero 435*150812a8SEvalZero 436*150812a8SEvalZero /** 437*150812a8SEvalZero * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 438*150812a8SEvalZero */ 439*150812a8SEvalZero typedef struct { 440*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 441*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 442*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 443*150812a8SEvalZero __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 444*150812a8SEvalZero } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 445*150812a8SEvalZero 446*150812a8SEvalZero 447*150812a8SEvalZero /** 448*150812a8SEvalZero * @brief TWIS_PSEL [PSEL] (Unspecified) 449*150812a8SEvalZero */ 450*150812a8SEvalZero typedef struct { 451*150812a8SEvalZero __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 452*150812a8SEvalZero __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 453*150812a8SEvalZero } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 454*150812a8SEvalZero 455*150812a8SEvalZero 456*150812a8SEvalZero /** 457*150812a8SEvalZero * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 458*150812a8SEvalZero */ 459*150812a8SEvalZero typedef struct { 460*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 461*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 462*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 463*150812a8SEvalZero } TWIS_RXD_Type; /*!< Size = 12 (0xc) */ 464*150812a8SEvalZero 465*150812a8SEvalZero 466*150812a8SEvalZero /** 467*150812a8SEvalZero * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 468*150812a8SEvalZero */ 469*150812a8SEvalZero typedef struct { 470*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 471*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 472*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 473*150812a8SEvalZero } TWIS_TXD_Type; /*!< Size = 12 (0xc) */ 474*150812a8SEvalZero 475*150812a8SEvalZero 476*150812a8SEvalZero /** 477*150812a8SEvalZero * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) 478*150812a8SEvalZero */ 479*150812a8SEvalZero typedef struct { 480*150812a8SEvalZero __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frame */ 481*150812a8SEvalZero } NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ 482*150812a8SEvalZero 483*150812a8SEvalZero 484*150812a8SEvalZero /** 485*150812a8SEvalZero * @brief NFCT_TXD [TXD] (Unspecified) 486*150812a8SEvalZero */ 487*150812a8SEvalZero typedef struct { 488*150812a8SEvalZero __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ 489*150812a8SEvalZero __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ 490*150812a8SEvalZero } NFCT_TXD_Type; /*!< Size = 8 (0x8) */ 491*150812a8SEvalZero 492*150812a8SEvalZero 493*150812a8SEvalZero /** 494*150812a8SEvalZero * @brief NFCT_RXD [RXD] (Unspecified) 495*150812a8SEvalZero */ 496*150812a8SEvalZero typedef struct { 497*150812a8SEvalZero __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ 498*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ 499*150812a8SEvalZero } NFCT_RXD_Type; /*!< Size = 8 (0x8) */ 500*150812a8SEvalZero 501*150812a8SEvalZero 502*150812a8SEvalZero /** 503*150812a8SEvalZero * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified) 504*150812a8SEvalZero */ 505*150812a8SEvalZero typedef struct { 506*150812a8SEvalZero __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[n]: Last result is equal 507*150812a8SEvalZero or above CH[n].LIMIT.HIGH */ 508*150812a8SEvalZero __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[n]: Last result is equal 509*150812a8SEvalZero or below CH[n].LIMIT.LOW */ 510*150812a8SEvalZero } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 511*150812a8SEvalZero 512*150812a8SEvalZero 513*150812a8SEvalZero /** 514*150812a8SEvalZero * @brief SAADC_CH [CH] (Unspecified) 515*150812a8SEvalZero */ 516*150812a8SEvalZero typedef struct { 517*150812a8SEvalZero __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[n]: Input positive pin selection 518*150812a8SEvalZero for CH[n] */ 519*150812a8SEvalZero __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[n]: Input negative pin selection 520*150812a8SEvalZero for CH[n] */ 521*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[n]: Input configuration for 522*150812a8SEvalZero CH[n] */ 523*150812a8SEvalZero __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[n]: High/low limits for event 524*150812a8SEvalZero monitoring of a channel */ 525*150812a8SEvalZero } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 526*150812a8SEvalZero 527*150812a8SEvalZero 528*150812a8SEvalZero /** 529*150812a8SEvalZero * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 530*150812a8SEvalZero */ 531*150812a8SEvalZero typedef struct { 532*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 533*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of 16-bit samples to be written 534*150812a8SEvalZero to output RAM buffer */ 535*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of 16-bit samples written to output RAM 536*150812a8SEvalZero buffer since the previous START task */ 537*150812a8SEvalZero } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 538*150812a8SEvalZero 539*150812a8SEvalZero 540*150812a8SEvalZero /** 541*150812a8SEvalZero * @brief QDEC_PSEL [PSEL] (Unspecified) 542*150812a8SEvalZero */ 543*150812a8SEvalZero typedef struct { 544*150812a8SEvalZero __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ 545*150812a8SEvalZero __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ 546*150812a8SEvalZero __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ 547*150812a8SEvalZero } QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ 548*150812a8SEvalZero 549*150812a8SEvalZero 550*150812a8SEvalZero /** 551*150812a8SEvalZero * @brief PWM_SEQ [SEQ] (Unspecified) 552*150812a8SEvalZero */ 553*150812a8SEvalZero typedef struct { 554*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Beginning address in 555*150812a8SEvalZero RAM of this sequence */ 556*150812a8SEvalZero __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[n]: Number of values (duty 557*150812a8SEvalZero cycles) in this sequence */ 558*150812a8SEvalZero __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[n]: Number of additional 559*150812a8SEvalZero PWM periods between samples loaded into 560*150812a8SEvalZero compare register */ 561*150812a8SEvalZero __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[n]: Time added after the 562*150812a8SEvalZero sequence */ 563*150812a8SEvalZero __IM uint32_t RESERVED[4]; 564*150812a8SEvalZero } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 565*150812a8SEvalZero 566*150812a8SEvalZero 567*150812a8SEvalZero /** 568*150812a8SEvalZero * @brief PWM_PSEL [PSEL] (Unspecified) 569*150812a8SEvalZero */ 570*150812a8SEvalZero typedef struct { 571*150812a8SEvalZero __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[n]: Output pin select 572*150812a8SEvalZero for PWM channel n */ 573*150812a8SEvalZero } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 574*150812a8SEvalZero 575*150812a8SEvalZero 576*150812a8SEvalZero /** 577*150812a8SEvalZero * @brief PDM_PSEL [PSEL] (Unspecified) 578*150812a8SEvalZero */ 579*150812a8SEvalZero typedef struct { 580*150812a8SEvalZero __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 581*150812a8SEvalZero __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 582*150812a8SEvalZero } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 583*150812a8SEvalZero 584*150812a8SEvalZero 585*150812a8SEvalZero /** 586*150812a8SEvalZero * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 587*150812a8SEvalZero */ 588*150812a8SEvalZero typedef struct { 589*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 590*150812a8SEvalZero EasyDMA */ 591*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 592*150812a8SEvalZero mode */ 593*150812a8SEvalZero } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 594*150812a8SEvalZero 595*150812a8SEvalZero 596*150812a8SEvalZero /** 597*150812a8SEvalZero * @brief ACL_ACL [ACL] (Unspecified) 598*150812a8SEvalZero */ 599*150812a8SEvalZero typedef struct { 600*150812a8SEvalZero __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster[n]: Configure the word-aligned 601*150812a8SEvalZero start address of region n to protect */ 602*150812a8SEvalZero __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster[n]: Size of region to protect 603*150812a8SEvalZero counting from address ACL[n].ADDR. Write 604*150812a8SEvalZero '0' as no effect. */ 605*150812a8SEvalZero __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster[n]: Access permissions for 606*150812a8SEvalZero region n as defined by start address ACL[n].ADDR 607*150812a8SEvalZero and size ACL[n].SIZE */ 608*150812a8SEvalZero __IOM uint32_t UNUSED0; /*!< (@ 0x0000000C) Unspecified */ 609*150812a8SEvalZero } ACL_ACL_Type; /*!< Size = 16 (0x10) */ 610*150812a8SEvalZero 611*150812a8SEvalZero 612*150812a8SEvalZero /** 613*150812a8SEvalZero * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) 614*150812a8SEvalZero */ 615*150812a8SEvalZero typedef struct { 616*150812a8SEvalZero __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[n]: Enable channel group 617*150812a8SEvalZero n */ 618*150812a8SEvalZero __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[n]: Disable channel group 619*150812a8SEvalZero n */ 620*150812a8SEvalZero } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 621*150812a8SEvalZero 622*150812a8SEvalZero 623*150812a8SEvalZero /** 624*150812a8SEvalZero * @brief PPI_CH [CH] (PPI Channel) 625*150812a8SEvalZero */ 626*150812a8SEvalZero typedef struct { 627*150812a8SEvalZero __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n event end-point */ 628*150812a8SEvalZero __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[n]: Channel n task end-point */ 629*150812a8SEvalZero } PPI_CH_Type; /*!< Size = 8 (0x8) */ 630*150812a8SEvalZero 631*150812a8SEvalZero 632*150812a8SEvalZero /** 633*150812a8SEvalZero * @brief PPI_FORK [FORK] (Fork) 634*150812a8SEvalZero */ 635*150812a8SEvalZero typedef struct { 636*150812a8SEvalZero __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n task end-point */ 637*150812a8SEvalZero } PPI_FORK_Type; /*!< Size = 4 (0x4) */ 638*150812a8SEvalZero 639*150812a8SEvalZero 640*150812a8SEvalZero /** 641*150812a8SEvalZero * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Unspecified) 642*150812a8SEvalZero */ 643*150812a8SEvalZero typedef struct { 644*150812a8SEvalZero __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[n]: Write access to region 645*150812a8SEvalZero n detected */ 646*150812a8SEvalZero __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[n]: Read access to region 647*150812a8SEvalZero n detected */ 648*150812a8SEvalZero } MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ 649*150812a8SEvalZero 650*150812a8SEvalZero 651*150812a8SEvalZero /** 652*150812a8SEvalZero * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Unspecified) 653*150812a8SEvalZero */ 654*150812a8SEvalZero typedef struct { 655*150812a8SEvalZero __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[n]: Write access to peripheral 656*150812a8SEvalZero region n detected */ 657*150812a8SEvalZero __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[n]: Read access to peripheral 658*150812a8SEvalZero region n detected */ 659*150812a8SEvalZero } MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ 660*150812a8SEvalZero 661*150812a8SEvalZero 662*150812a8SEvalZero /** 663*150812a8SEvalZero * @brief MWU_PERREGION [PERREGION] (Unspecified) 664*150812a8SEvalZero */ 665*150812a8SEvalZero typedef struct { 666*150812a8SEvalZero __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster[n]: Source of event/interrupt 667*150812a8SEvalZero in region n, write access detected while 668*150812a8SEvalZero corresponding subregion was enabled for 669*150812a8SEvalZero watching */ 670*150812a8SEvalZero __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster[n]: Source of event/interrupt 671*150812a8SEvalZero in region n, read access detected while 672*150812a8SEvalZero corresponding subregion was enabled for 673*150812a8SEvalZero watching */ 674*150812a8SEvalZero } MWU_PERREGION_Type; /*!< Size = 8 (0x8) */ 675*150812a8SEvalZero 676*150812a8SEvalZero 677*150812a8SEvalZero /** 678*150812a8SEvalZero * @brief MWU_REGION [REGION] (Unspecified) 679*150812a8SEvalZero */ 680*150812a8SEvalZero typedef struct { 681*150812a8SEvalZero __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster[n]: Start address for region 682*150812a8SEvalZero n */ 683*150812a8SEvalZero __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster[n]: End address of region 684*150812a8SEvalZero n */ 685*150812a8SEvalZero __IM uint32_t RESERVED[2]; 686*150812a8SEvalZero } MWU_REGION_Type; /*!< Size = 16 (0x10) */ 687*150812a8SEvalZero 688*150812a8SEvalZero 689*150812a8SEvalZero /** 690*150812a8SEvalZero * @brief MWU_PREGION [PREGION] (Unspecified) 691*150812a8SEvalZero */ 692*150812a8SEvalZero typedef struct { 693*150812a8SEvalZero __IM uint32_t START; /*!< (@ 0x00000000) Description cluster[n]: Reserved for future use */ 694*150812a8SEvalZero __IM uint32_t END; /*!< (@ 0x00000004) Description cluster[n]: Reserved for future use */ 695*150812a8SEvalZero __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster[n]: Subregions of region 696*150812a8SEvalZero n */ 697*150812a8SEvalZero __IM uint32_t RESERVED; 698*150812a8SEvalZero } MWU_PREGION_Type; /*!< Size = 16 (0x10) */ 699*150812a8SEvalZero 700*150812a8SEvalZero 701*150812a8SEvalZero /** 702*150812a8SEvalZero * @brief I2S_CONFIG [CONFIG] (Unspecified) 703*150812a8SEvalZero */ 704*150812a8SEvalZero typedef struct { 705*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ 706*150812a8SEvalZero __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ 707*150812a8SEvalZero __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ 708*150812a8SEvalZero __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ 709*150812a8SEvalZero __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ 710*150812a8SEvalZero __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ 711*150812a8SEvalZero __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ 712*150812a8SEvalZero __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ 713*150812a8SEvalZero __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ 714*150812a8SEvalZero __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ 715*150812a8SEvalZero } I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ 716*150812a8SEvalZero 717*150812a8SEvalZero 718*150812a8SEvalZero /** 719*150812a8SEvalZero * @brief I2S_RXD [RXD] (Unspecified) 720*150812a8SEvalZero */ 721*150812a8SEvalZero typedef struct { 722*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ 723*150812a8SEvalZero } I2S_RXD_Type; /*!< Size = 4 (0x4) */ 724*150812a8SEvalZero 725*150812a8SEvalZero 726*150812a8SEvalZero /** 727*150812a8SEvalZero * @brief I2S_TXD [TXD] (Unspecified) 728*150812a8SEvalZero */ 729*150812a8SEvalZero typedef struct { 730*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ 731*150812a8SEvalZero } I2S_TXD_Type; /*!< Size = 4 (0x4) */ 732*150812a8SEvalZero 733*150812a8SEvalZero 734*150812a8SEvalZero /** 735*150812a8SEvalZero * @brief I2S_RXTXD [RXTXD] (Unspecified) 736*150812a8SEvalZero */ 737*150812a8SEvalZero typedef struct { 738*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ 739*150812a8SEvalZero } I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ 740*150812a8SEvalZero 741*150812a8SEvalZero 742*150812a8SEvalZero /** 743*150812a8SEvalZero * @brief I2S_PSEL [PSEL] (Unspecified) 744*150812a8SEvalZero */ 745*150812a8SEvalZero typedef struct { 746*150812a8SEvalZero __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ 747*150812a8SEvalZero __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ 748*150812a8SEvalZero __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ 749*150812a8SEvalZero __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ 750*150812a8SEvalZero __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ 751*150812a8SEvalZero } I2S_PSEL_Type; /*!< Size = 20 (0x14) */ 752*150812a8SEvalZero 753*150812a8SEvalZero 754*150812a8SEvalZero /** 755*150812a8SEvalZero * @brief USBD_HALTED [HALTED] (Unspecified) 756*150812a8SEvalZero */ 757*150812a8SEvalZero typedef struct { 758*150812a8SEvalZero __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection[n]: IN endpoint halted 759*150812a8SEvalZero status. Can be used as is as response to 760*150812a8SEvalZero a GetStatus() request to endpoint. */ 761*150812a8SEvalZero __IM uint32_t RESERVED; 762*150812a8SEvalZero __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection[n]: OUT endpoint halted 763*150812a8SEvalZero status. Can be used as is as response to 764*150812a8SEvalZero a GetStatus() request to endpoint. */ 765*150812a8SEvalZero } USBD_HALTED_Type; /*!< Size = 68 (0x44) */ 766*150812a8SEvalZero 767*150812a8SEvalZero 768*150812a8SEvalZero /** 769*150812a8SEvalZero * @brief USBD_SIZE [SIZE] (Unspecified) 770*150812a8SEvalZero */ 771*150812a8SEvalZero typedef struct { 772*150812a8SEvalZero __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection[n]: Number of bytes received 773*150812a8SEvalZero last in the data stage of this OUT endpoint */ 774*150812a8SEvalZero __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT 775*150812a8SEvalZero data endpoint */ 776*150812a8SEvalZero } USBD_SIZE_Type; /*!< Size = 36 (0x24) */ 777*150812a8SEvalZero 778*150812a8SEvalZero 779*150812a8SEvalZero /** 780*150812a8SEvalZero * @brief USBD_EPIN [EPIN] (Unspecified) 781*150812a8SEvalZero */ 782*150812a8SEvalZero typedef struct { 783*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Data pointer */ 784*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster[n]: Maximum number of bytes 785*150812a8SEvalZero to transfer */ 786*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster[n]: Number of bytes transferred 787*150812a8SEvalZero in the last transaction */ 788*150812a8SEvalZero __IM uint32_t RESERVED[2]; 789*150812a8SEvalZero } USBD_EPIN_Type; /*!< Size = 20 (0x14) */ 790*150812a8SEvalZero 791*150812a8SEvalZero 792*150812a8SEvalZero /** 793*150812a8SEvalZero * @brief USBD_ISOIN [ISOIN] (Unspecified) 794*150812a8SEvalZero */ 795*150812a8SEvalZero typedef struct { 796*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 797*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ 798*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 799*150812a8SEvalZero } USBD_ISOIN_Type; /*!< Size = 12 (0xc) */ 800*150812a8SEvalZero 801*150812a8SEvalZero 802*150812a8SEvalZero /** 803*150812a8SEvalZero * @brief USBD_EPOUT [EPOUT] (Unspecified) 804*150812a8SEvalZero */ 805*150812a8SEvalZero typedef struct { 806*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Data pointer */ 807*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster[n]: Maximum number of bytes 808*150812a8SEvalZero to transfer */ 809*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster[n]: Number of bytes transferred 810*150812a8SEvalZero in the last transaction */ 811*150812a8SEvalZero __IM uint32_t RESERVED[2]; 812*150812a8SEvalZero } USBD_EPOUT_Type; /*!< Size = 20 (0x14) */ 813*150812a8SEvalZero 814*150812a8SEvalZero 815*150812a8SEvalZero /** 816*150812a8SEvalZero * @brief USBD_ISOOUT [ISOOUT] (Unspecified) 817*150812a8SEvalZero */ 818*150812a8SEvalZero typedef struct { 819*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 820*150812a8SEvalZero __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ 821*150812a8SEvalZero __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 822*150812a8SEvalZero } USBD_ISOOUT_Type; /*!< Size = 12 (0xc) */ 823*150812a8SEvalZero 824*150812a8SEvalZero 825*150812a8SEvalZero /** 826*150812a8SEvalZero * @brief QSPI_READ [READ] (Unspecified) 827*150812a8SEvalZero */ 828*150812a8SEvalZero typedef struct { 829*150812a8SEvalZero __IOM uint32_t SRC; /*!< (@ 0x00000000) Flash memory source address */ 830*150812a8SEvalZero __IOM uint32_t DST; /*!< (@ 0x00000004) RAM destination address */ 831*150812a8SEvalZero __IOM uint32_t CNT; /*!< (@ 0x00000008) Read transfer length */ 832*150812a8SEvalZero } QSPI_READ_Type; /*!< Size = 12 (0xc) */ 833*150812a8SEvalZero 834*150812a8SEvalZero 835*150812a8SEvalZero /** 836*150812a8SEvalZero * @brief QSPI_WRITE [WRITE] (Unspecified) 837*150812a8SEvalZero */ 838*150812a8SEvalZero typedef struct { 839*150812a8SEvalZero __IOM uint32_t DST; /*!< (@ 0x00000000) Flash destination address */ 840*150812a8SEvalZero __IOM uint32_t SRC; /*!< (@ 0x00000004) RAM source address */ 841*150812a8SEvalZero __IOM uint32_t CNT; /*!< (@ 0x00000008) Write transfer length */ 842*150812a8SEvalZero } QSPI_WRITE_Type; /*!< Size = 12 (0xc) */ 843*150812a8SEvalZero 844*150812a8SEvalZero 845*150812a8SEvalZero /** 846*150812a8SEvalZero * @brief QSPI_ERASE [ERASE] (Unspecified) 847*150812a8SEvalZero */ 848*150812a8SEvalZero typedef struct { 849*150812a8SEvalZero __IOM uint32_t PTR; /*!< (@ 0x00000000) Start address of flash block to be erased */ 850*150812a8SEvalZero __IOM uint32_t LEN; /*!< (@ 0x00000004) Size of block to be erased. */ 851*150812a8SEvalZero } QSPI_ERASE_Type; /*!< Size = 8 (0x8) */ 852*150812a8SEvalZero 853*150812a8SEvalZero 854*150812a8SEvalZero /** 855*150812a8SEvalZero * @brief QSPI_PSEL [PSEL] (Unspecified) 856*150812a8SEvalZero */ 857*150812a8SEvalZero typedef struct { 858*150812a8SEvalZero __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for serial clock SCK */ 859*150812a8SEvalZero __IOM uint32_t CSN; /*!< (@ 0x00000004) Pin select for chip select signal CSN. */ 860*150812a8SEvalZero __IM uint32_t RESERVED; 861*150812a8SEvalZero __IOM uint32_t IO0; /*!< (@ 0x0000000C) Pin select for serial data MOSI/IO0. */ 862*150812a8SEvalZero __IOM uint32_t IO1; /*!< (@ 0x00000010) Pin select for serial data MISO/IO1. */ 863*150812a8SEvalZero __IOM uint32_t IO2; /*!< (@ 0x00000014) Pin select for serial data IO2. */ 864*150812a8SEvalZero __IOM uint32_t IO3; /*!< (@ 0x00000018) Pin select for serial data IO3. */ 865*150812a8SEvalZero } QSPI_PSEL_Type; /*!< Size = 28 (0x1c) */ 866*150812a8SEvalZero 867*150812a8SEvalZero 868*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_clusters */ 869*150812a8SEvalZero 870*150812a8SEvalZero 871*150812a8SEvalZero /* =========================================================================================================================== */ 872*150812a8SEvalZero /* ================ Device Specific Peripheral Section ================ */ 873*150812a8SEvalZero /* =========================================================================================================================== */ 874*150812a8SEvalZero 875*150812a8SEvalZero 876*150812a8SEvalZero /** @addtogroup Device_Peripheral_peripherals 877*150812a8SEvalZero * @{ 878*150812a8SEvalZero */ 879*150812a8SEvalZero 880*150812a8SEvalZero 881*150812a8SEvalZero 882*150812a8SEvalZero /* =========================================================================================================================== */ 883*150812a8SEvalZero /* ================ FICR ================ */ 884*150812a8SEvalZero /* =========================================================================================================================== */ 885*150812a8SEvalZero 886*150812a8SEvalZero 887*150812a8SEvalZero /** 888*150812a8SEvalZero * @brief Factory information configuration registers (FICR) 889*150812a8SEvalZero */ 890*150812a8SEvalZero 891*150812a8SEvalZero typedef struct { /*!< (@ 0x10000000) FICR Structure */ 892*150812a8SEvalZero __IM uint32_t RESERVED[4]; 893*150812a8SEvalZero __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ 894*150812a8SEvalZero __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ 895*150812a8SEvalZero __IM uint32_t RESERVED1[18]; 896*150812a8SEvalZero __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[n]: Device identifier */ 897*150812a8SEvalZero __IM uint32_t RESERVED2[6]; 898*150812a8SEvalZero __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[n]: Encryption root, word 899*150812a8SEvalZero n */ 900*150812a8SEvalZero __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[n]: Identity Root, word 901*150812a8SEvalZero n */ 902*150812a8SEvalZero __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ 903*150812a8SEvalZero __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[n]: Device address n */ 904*150812a8SEvalZero __IM uint32_t RESERVED3[21]; 905*150812a8SEvalZero __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ 906*150812a8SEvalZero __IM uint32_t RESERVED4[140]; 907*150812a8SEvalZero __IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection[n]: Production test signature 908*150812a8SEvalZero n */ 909*150812a8SEvalZero __IM uint32_t RESERVED5[42]; 910*150812a8SEvalZero __IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization 911*150812a8SEvalZero coefficients */ 912*150812a8SEvalZero __IM uint32_t RESERVED6[2]; 913*150812a8SEvalZero __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ 914*150812a8SEvalZero __IM uint32_t RESERVED7[488]; 915*150812a8SEvalZero __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ 916*150812a8SEvalZero } NRF_FICR_Type; /*!< Size = 3104 (0xc20) */ 917*150812a8SEvalZero 918*150812a8SEvalZero 919*150812a8SEvalZero 920*150812a8SEvalZero /* =========================================================================================================================== */ 921*150812a8SEvalZero /* ================ UICR ================ */ 922*150812a8SEvalZero /* =========================================================================================================================== */ 923*150812a8SEvalZero 924*150812a8SEvalZero 925*150812a8SEvalZero /** 926*150812a8SEvalZero * @brief User information configuration registers (UICR) 927*150812a8SEvalZero */ 928*150812a8SEvalZero 929*150812a8SEvalZero typedef struct { /*!< (@ 0x10001000) UICR Structure */ 930*150812a8SEvalZero __IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */ 931*150812a8SEvalZero __IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */ 932*150812a8SEvalZero __IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */ 933*150812a8SEvalZero __IM uint32_t RESERVED; 934*150812a8SEvalZero __IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */ 935*150812a8SEvalZero __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[n]: Reserved for Nordic 936*150812a8SEvalZero firmware design */ 937*150812a8SEvalZero __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[n]: Reserved for Nordic 938*150812a8SEvalZero hardware design */ 939*150812a8SEvalZero __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[n]: Reserved for customer */ 940*150812a8SEvalZero __IM uint32_t RESERVED1[64]; 941*150812a8SEvalZero __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[n]: Mapping of the nRESET 942*150812a8SEvalZero function */ 943*150812a8SEvalZero __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ 944*150812a8SEvalZero __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: 945*150812a8SEvalZero NFC antenna or GPIO */ 946*150812a8SEvalZero __IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */ 947*150812a8SEvalZero __IM uint32_t RESERVED2[60]; 948*150812a8SEvalZero __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) GPIO reference voltage / external output supply 949*150812a8SEvalZero voltage in high voltage mode */ 950*150812a8SEvalZero } NRF_UICR_Type; /*!< Size = 776 (0x308) */ 951*150812a8SEvalZero 952*150812a8SEvalZero 953*150812a8SEvalZero 954*150812a8SEvalZero /* =========================================================================================================================== */ 955*150812a8SEvalZero /* ================ CLOCK ================ */ 956*150812a8SEvalZero /* =========================================================================================================================== */ 957*150812a8SEvalZero 958*150812a8SEvalZero 959*150812a8SEvalZero /** 960*150812a8SEvalZero * @brief Clock control (CLOCK) 961*150812a8SEvalZero */ 962*150812a8SEvalZero 963*150812a8SEvalZero typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 964*150812a8SEvalZero __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFXO crystal oscillator */ 965*150812a8SEvalZero __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFXO crystal oscillator */ 966*150812a8SEvalZero __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK */ 967*150812a8SEvalZero __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK */ 968*150812a8SEvalZero __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC */ 969*150812a8SEvalZero __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ 970*150812a8SEvalZero __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ 971*150812a8SEvalZero __IM uint32_t RESERVED[57]; 972*150812a8SEvalZero __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFXO crystal oscillator started */ 973*150812a8SEvalZero __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 974*150812a8SEvalZero __IM uint32_t RESERVED1; 975*150812a8SEvalZero __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFRC completed */ 976*150812a8SEvalZero __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ 977*150812a8SEvalZero __IM uint32_t RESERVED2[5]; 978*150812a8SEvalZero __IOM uint32_t EVENTS_CTSTARTED; /*!< (@ 0x00000128) Calibration timer has been started and is ready 979*150812a8SEvalZero to process new tasks */ 980*150812a8SEvalZero __IOM uint32_t EVENTS_CTSTOPPED; /*!< (@ 0x0000012C) Calibration timer has been stopped and is ready 981*150812a8SEvalZero to process new tasks */ 982*150812a8SEvalZero __IM uint32_t RESERVED3[117]; 983*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 984*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 985*150812a8SEvalZero __IM uint32_t RESERVED4[63]; 986*150812a8SEvalZero __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 987*150812a8SEvalZero triggered */ 988*150812a8SEvalZero __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ 989*150812a8SEvalZero __IM uint32_t RESERVED5; 990*150812a8SEvalZero __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 991*150812a8SEvalZero triggered */ 992*150812a8SEvalZero __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ 993*150812a8SEvalZero __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 994*150812a8SEvalZero task was triggered */ 995*150812a8SEvalZero __IM uint32_t RESERVED6[62]; 996*150812a8SEvalZero __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ 997*150812a8SEvalZero __IM uint32_t RESERVED7[3]; 998*150812a8SEvalZero __IOM uint32_t HFXODEBOUNCE; /*!< (@ 0x00000528) HFXO debounce time. The HFXO is started by triggering 999*150812a8SEvalZero the TASKS_HFCLKSTART task. */ 1000*150812a8SEvalZero __IM uint32_t RESERVED8[3]; 1001*150812a8SEvalZero __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ 1002*150812a8SEvalZero __IM uint32_t RESERVED9[8]; 1003*150812a8SEvalZero __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the trace port debug interface */ 1004*150812a8SEvalZero __IM uint32_t RESERVED10[21]; 1005*150812a8SEvalZero __IOM uint32_t LFRCMODE; /*!< (@ 0x000005B4) LFRC mode configuration */ 1006*150812a8SEvalZero } NRF_CLOCK_Type; /*!< Size = 1464 (0x5b8) */ 1007*150812a8SEvalZero 1008*150812a8SEvalZero 1009*150812a8SEvalZero 1010*150812a8SEvalZero /* =========================================================================================================================== */ 1011*150812a8SEvalZero /* ================ POWER ================ */ 1012*150812a8SEvalZero /* =========================================================================================================================== */ 1013*150812a8SEvalZero 1014*150812a8SEvalZero 1015*150812a8SEvalZero /** 1016*150812a8SEvalZero * @brief Power control (POWER) 1017*150812a8SEvalZero */ 1018*150812a8SEvalZero 1019*150812a8SEvalZero typedef struct { /*!< (@ 0x40000000) POWER Structure */ 1020*150812a8SEvalZero __IM uint32_t RESERVED[30]; 1021*150812a8SEvalZero __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ 1022*150812a8SEvalZero __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ 1023*150812a8SEvalZero __IM uint32_t RESERVED1[34]; 1024*150812a8SEvalZero __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 1025*150812a8SEvalZero __IM uint32_t RESERVED2[2]; 1026*150812a8SEvalZero __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 1027*150812a8SEvalZero __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 1028*150812a8SEvalZero __IOM uint32_t EVENTS_USBDETECTED; /*!< (@ 0x0000011C) Voltage supply detected on VBUS */ 1029*150812a8SEvalZero __IOM uint32_t EVENTS_USBREMOVED; /*!< (@ 0x00000120) Voltage supply removed from VBUS */ 1030*150812a8SEvalZero __IOM uint32_t EVENTS_USBPWRRDY; /*!< (@ 0x00000124) USB 3.3 V supply ready */ 1031*150812a8SEvalZero __IM uint32_t RESERVED3[119]; 1032*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1033*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1034*150812a8SEvalZero __IM uint32_t RESERVED4[61]; 1035*150812a8SEvalZero __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 1036*150812a8SEvalZero __IM uint32_t RESERVED5[9]; 1037*150812a8SEvalZero __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ 1038*150812a8SEvalZero __IM uint32_t RESERVED6[3]; 1039*150812a8SEvalZero __IM uint32_t USBREGSTATUS; /*!< (@ 0x00000438) USB supply status */ 1040*150812a8SEvalZero __IM uint32_t RESERVED7[49]; 1041*150812a8SEvalZero __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 1042*150812a8SEvalZero __IM uint32_t RESERVED8[3]; 1043*150812a8SEvalZero __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power-fail comparator configuration */ 1044*150812a8SEvalZero __IM uint32_t RESERVED9[2]; 1045*150812a8SEvalZero __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ 1046*150812a8SEvalZero __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ 1047*150812a8SEvalZero __IM uint32_t RESERVED10[21]; 1048*150812a8SEvalZero __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage. */ 1049*150812a8SEvalZero __IM uint32_t RESERVED11; 1050*150812a8SEvalZero __IOM uint32_t DCDCEN0; /*!< (@ 0x00000580) Enable DC/DC converter for REG0 stage. */ 1051*150812a8SEvalZero __IM uint32_t RESERVED12[47]; 1052*150812a8SEvalZero __IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000640) Main supply status */ 1053*150812a8SEvalZero __IM uint32_t RESERVED13[175]; 1054*150812a8SEvalZero __IOM POWER_RAM_Type RAM[9]; /*!< (@ 0x00000900) Unspecified */ 1055*150812a8SEvalZero } NRF_POWER_Type; /*!< Size = 2448 (0x990) */ 1056*150812a8SEvalZero 1057*150812a8SEvalZero 1058*150812a8SEvalZero 1059*150812a8SEvalZero /* =========================================================================================================================== */ 1060*150812a8SEvalZero /* ================ RADIO ================ */ 1061*150812a8SEvalZero /* =========================================================================================================================== */ 1062*150812a8SEvalZero 1063*150812a8SEvalZero 1064*150812a8SEvalZero /** 1065*150812a8SEvalZero * @brief 2.4 GHz radio (RADIO) 1066*150812a8SEvalZero */ 1067*150812a8SEvalZero 1068*150812a8SEvalZero typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 1069*150812a8SEvalZero __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 1070*150812a8SEvalZero __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 1071*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 1072*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 1073*150812a8SEvalZero __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 1074*150812a8SEvalZero __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 1075*150812a8SEvalZero the receive signal strength */ 1076*150812a8SEvalZero __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 1077*150812a8SEvalZero __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 1078*150812a8SEvalZero __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 1079*150812a8SEvalZero __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE 1080*150812a8SEvalZero 802.15.4 mode */ 1081*150812a8SEvalZero __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */ 1082*150812a8SEvalZero __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE 1083*150812a8SEvalZero 802.15.4 mode */ 1084*150812a8SEvalZero __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */ 1085*150812a8SEvalZero __IM uint32_t RESERVED[51]; 1086*150812a8SEvalZero __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 1087*150812a8SEvalZero __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 1088*150812a8SEvalZero __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 1089*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 1090*150812a8SEvalZero __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 1091*150812a8SEvalZero __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 1092*150812a8SEvalZero packet */ 1093*150812a8SEvalZero __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 1094*150812a8SEvalZero received packet */ 1095*150812a8SEvalZero __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ 1096*150812a8SEvalZero __IM uint32_t RESERVED1[2]; 1097*150812a8SEvalZero __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ 1098*150812a8SEvalZero __IM uint32_t RESERVED2; 1099*150812a8SEvalZero __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 1100*150812a8SEvalZero __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 1101*150812a8SEvalZero __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ 1102*150812a8SEvalZero __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new 1103*150812a8SEvalZero ED sample is ready for readout from the 1104*150812a8SEvalZero RADIO.EDSAMPLE register. */ 1105*150812a8SEvalZero __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ 1106*150812a8SEvalZero __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ 1107*150812a8SEvalZero __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ 1108*150812a8SEvalZero __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */ 1109*150812a8SEvalZero __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed 1110*150812a8SEvalZero from Ble_LR125Kbit to Ble_LR500Kbit. */ 1111*150812a8SEvalZero __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started 1112*150812a8SEvalZero TX path */ 1113*150812a8SEvalZero __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started 1114*150812a8SEvalZero RX path */ 1115*150812a8SEvalZero __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ 1116*150812a8SEvalZero __IM uint32_t RESERVED3[3]; 1117*150812a8SEvalZero __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated in Ble_LR125Kbit, Ble_LR500Kbit and 1118*150812a8SEvalZero BleIeee802154_250Kbit modes when last bit 1119*150812a8SEvalZero is sent on air. */ 1120*150812a8SEvalZero __IM uint32_t RESERVED4[36]; 1121*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1122*150812a8SEvalZero __IM uint32_t RESERVED5[64]; 1123*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1124*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1125*150812a8SEvalZero __IM uint32_t RESERVED6[61]; 1126*150812a8SEvalZero __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 1127*150812a8SEvalZero __IM uint32_t RESERVED7; 1128*150812a8SEvalZero __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 1129*150812a8SEvalZero __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 1130*150812a8SEvalZero __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 1131*150812a8SEvalZero __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ 1132*150812a8SEvalZero __IM uint32_t RESERVED8[59]; 1133*150812a8SEvalZero __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 1134*150812a8SEvalZero __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 1135*150812a8SEvalZero __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 1136*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 1137*150812a8SEvalZero __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 1138*150812a8SEvalZero __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 1139*150812a8SEvalZero __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 1140*150812a8SEvalZero __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 1141*150812a8SEvalZero __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 1142*150812a8SEvalZero __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 1143*150812a8SEvalZero __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 1144*150812a8SEvalZero __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 1145*150812a8SEvalZero __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 1146*150812a8SEvalZero __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 1147*150812a8SEvalZero __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 1148*150812a8SEvalZero __IM uint32_t RESERVED9; 1149*150812a8SEvalZero __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ 1150*150812a8SEvalZero __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 1151*150812a8SEvalZero __IM uint32_t RESERVED10; 1152*150812a8SEvalZero __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 1153*150812a8SEvalZero __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 1154*150812a8SEvalZero __IM uint32_t RESERVED11[2]; 1155*150812a8SEvalZero __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 1156*150812a8SEvalZero __IM uint32_t RESERVED12[39]; 1157*150812a8SEvalZero __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[n]: Device address base 1158*150812a8SEvalZero segment n */ 1159*150812a8SEvalZero __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[n]: Device address prefix 1160*150812a8SEvalZero n */ 1161*150812a8SEvalZero __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 1162*150812a8SEvalZero __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ 1163*150812a8SEvalZero __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ 1164*150812a8SEvalZero __IM uint32_t RESERVED13; 1165*150812a8SEvalZero __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 1166*150812a8SEvalZero __IM uint32_t RESERVED14[3]; 1167*150812a8SEvalZero __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ 1168*150812a8SEvalZero __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ 1169*150812a8SEvalZero __IOM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ 1170*150812a8SEvalZero __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ 1171*150812a8SEvalZero __IM uint32_t RESERVED15[611]; 1172*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 1173*150812a8SEvalZero } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 1174*150812a8SEvalZero 1175*150812a8SEvalZero 1176*150812a8SEvalZero 1177*150812a8SEvalZero /* =========================================================================================================================== */ 1178*150812a8SEvalZero /* ================ UART0 ================ */ 1179*150812a8SEvalZero /* =========================================================================================================================== */ 1180*150812a8SEvalZero 1181*150812a8SEvalZero 1182*150812a8SEvalZero /** 1183*150812a8SEvalZero * @brief Universal Asynchronous Receiver/Transmitter (UART0) 1184*150812a8SEvalZero */ 1185*150812a8SEvalZero 1186*150812a8SEvalZero typedef struct { /*!< (@ 0x40002000) UART0 Structure */ 1187*150812a8SEvalZero __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1188*150812a8SEvalZero __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1189*150812a8SEvalZero __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1190*150812a8SEvalZero __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1191*150812a8SEvalZero __IM uint32_t RESERVED[3]; 1192*150812a8SEvalZero __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ 1193*150812a8SEvalZero __IM uint32_t RESERVED1[56]; 1194*150812a8SEvalZero __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1195*150812a8SEvalZero __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1196*150812a8SEvalZero __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ 1197*150812a8SEvalZero __IM uint32_t RESERVED2[4]; 1198*150812a8SEvalZero __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1199*150812a8SEvalZero __IM uint32_t RESERVED3; 1200*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1201*150812a8SEvalZero __IM uint32_t RESERVED4[7]; 1202*150812a8SEvalZero __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1203*150812a8SEvalZero __IM uint32_t RESERVED5[46]; 1204*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1205*150812a8SEvalZero __IM uint32_t RESERVED6[64]; 1206*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1207*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1208*150812a8SEvalZero __IM uint32_t RESERVED7[93]; 1209*150812a8SEvalZero __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 1210*150812a8SEvalZero __IM uint32_t RESERVED8[31]; 1211*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1212*150812a8SEvalZero __IM uint32_t RESERVED9; 1213*150812a8SEvalZero __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1214*150812a8SEvalZero __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1215*150812a8SEvalZero __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1216*150812a8SEvalZero __IM uint32_t RESERVED10; 1217*150812a8SEvalZero __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1218*150812a8SEvalZero selected. */ 1219*150812a8SEvalZero __IM uint32_t RESERVED11[17]; 1220*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1221*150812a8SEvalZero } NRF_UART_Type; /*!< Size = 1392 (0x570) */ 1222*150812a8SEvalZero 1223*150812a8SEvalZero 1224*150812a8SEvalZero 1225*150812a8SEvalZero /* =========================================================================================================================== */ 1226*150812a8SEvalZero /* ================ UARTE0 ================ */ 1227*150812a8SEvalZero /* =========================================================================================================================== */ 1228*150812a8SEvalZero 1229*150812a8SEvalZero 1230*150812a8SEvalZero /** 1231*150812a8SEvalZero * @brief UART with EasyDMA 0 (UARTE0) 1232*150812a8SEvalZero */ 1233*150812a8SEvalZero 1234*150812a8SEvalZero typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ 1235*150812a8SEvalZero __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1236*150812a8SEvalZero __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1237*150812a8SEvalZero __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1238*150812a8SEvalZero __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1239*150812a8SEvalZero __IM uint32_t RESERVED[7]; 1240*150812a8SEvalZero __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 1241*150812a8SEvalZero __IM uint32_t RESERVED1[52]; 1242*150812a8SEvalZero __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1243*150812a8SEvalZero __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1244*150812a8SEvalZero __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 1245*150812a8SEvalZero transferred to Data RAM) */ 1246*150812a8SEvalZero __IM uint32_t RESERVED2; 1247*150812a8SEvalZero __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 1248*150812a8SEvalZero __IM uint32_t RESERVED3[2]; 1249*150812a8SEvalZero __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1250*150812a8SEvalZero __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 1251*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1252*150812a8SEvalZero __IM uint32_t RESERVED4[7]; 1253*150812a8SEvalZero __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1254*150812a8SEvalZero __IM uint32_t RESERVED5; 1255*150812a8SEvalZero __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 1256*150812a8SEvalZero __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 1257*150812a8SEvalZero __IM uint32_t RESERVED6; 1258*150812a8SEvalZero __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 1259*150812a8SEvalZero __IM uint32_t RESERVED7[41]; 1260*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1261*150812a8SEvalZero __IM uint32_t RESERVED8[63]; 1262*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1263*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1264*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1265*150812a8SEvalZero __IM uint32_t RESERVED9[93]; 1266*150812a8SEvalZero __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write 1267*150812a8SEvalZero one to clear. */ 1268*150812a8SEvalZero __IM uint32_t RESERVED10[31]; 1269*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1270*150812a8SEvalZero __IM uint32_t RESERVED11; 1271*150812a8SEvalZero __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1272*150812a8SEvalZero __IM uint32_t RESERVED12[3]; 1273*150812a8SEvalZero __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1274*150812a8SEvalZero selected. */ 1275*150812a8SEvalZero __IM uint32_t RESERVED13[3]; 1276*150812a8SEvalZero __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1277*150812a8SEvalZero __IM uint32_t RESERVED14; 1278*150812a8SEvalZero __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1279*150812a8SEvalZero __IM uint32_t RESERVED15[7]; 1280*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1281*150812a8SEvalZero } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1282*150812a8SEvalZero 1283*150812a8SEvalZero 1284*150812a8SEvalZero 1285*150812a8SEvalZero /* =========================================================================================================================== */ 1286*150812a8SEvalZero /* ================ SPI0 ================ */ 1287*150812a8SEvalZero /* =========================================================================================================================== */ 1288*150812a8SEvalZero 1289*150812a8SEvalZero 1290*150812a8SEvalZero /** 1291*150812a8SEvalZero * @brief Serial Peripheral Interface 0 (SPI0) 1292*150812a8SEvalZero */ 1293*150812a8SEvalZero 1294*150812a8SEvalZero typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ 1295*150812a8SEvalZero __IM uint32_t RESERVED[66]; 1296*150812a8SEvalZero __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ 1297*150812a8SEvalZero __IM uint32_t RESERVED1[126]; 1298*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1299*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1300*150812a8SEvalZero __IM uint32_t RESERVED2[125]; 1301*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ 1302*150812a8SEvalZero __IM uint32_t RESERVED3; 1303*150812a8SEvalZero __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1304*150812a8SEvalZero __IM uint32_t RESERVED4; 1305*150812a8SEvalZero __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1306*150812a8SEvalZero __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1307*150812a8SEvalZero __IM uint32_t RESERVED5; 1308*150812a8SEvalZero __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1309*150812a8SEvalZero source selected. */ 1310*150812a8SEvalZero __IM uint32_t RESERVED6[11]; 1311*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1312*150812a8SEvalZero } NRF_SPI_Type; /*!< Size = 1368 (0x558) */ 1313*150812a8SEvalZero 1314*150812a8SEvalZero 1315*150812a8SEvalZero 1316*150812a8SEvalZero /* =========================================================================================================================== */ 1317*150812a8SEvalZero /* ================ SPIM0 ================ */ 1318*150812a8SEvalZero /* =========================================================================================================================== */ 1319*150812a8SEvalZero 1320*150812a8SEvalZero 1321*150812a8SEvalZero /** 1322*150812a8SEvalZero * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) 1323*150812a8SEvalZero */ 1324*150812a8SEvalZero 1325*150812a8SEvalZero typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ 1326*150812a8SEvalZero __IM uint32_t RESERVED[4]; 1327*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1328*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1329*150812a8SEvalZero __IM uint32_t RESERVED1; 1330*150812a8SEvalZero __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1331*150812a8SEvalZero __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1332*150812a8SEvalZero __IM uint32_t RESERVED2[56]; 1333*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1334*150812a8SEvalZero __IM uint32_t RESERVED3[2]; 1335*150812a8SEvalZero __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1336*150812a8SEvalZero __IM uint32_t RESERVED4; 1337*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1338*150812a8SEvalZero __IM uint32_t RESERVED5; 1339*150812a8SEvalZero __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1340*150812a8SEvalZero __IM uint32_t RESERVED6[10]; 1341*150812a8SEvalZero __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1342*150812a8SEvalZero __IM uint32_t RESERVED7[44]; 1343*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1344*150812a8SEvalZero __IM uint32_t RESERVED8[64]; 1345*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1346*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1347*150812a8SEvalZero __IM uint32_t RESERVED9[61]; 1348*150812a8SEvalZero __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields 1349*150812a8SEvalZero in this register is set to STALL by hardware 1350*150812a8SEvalZero whenever a stall occurres and can be cleared 1351*150812a8SEvalZero (set to NOSTALL) by the CPU. */ 1352*150812a8SEvalZero __IM uint32_t RESERVED10[63]; 1353*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1354*150812a8SEvalZero __IM uint32_t RESERVED11; 1355*150812a8SEvalZero __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1356*150812a8SEvalZero __IM uint32_t RESERVED12[3]; 1357*150812a8SEvalZero __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1358*150812a8SEvalZero source selected. */ 1359*150812a8SEvalZero __IM uint32_t RESERVED13[3]; 1360*150812a8SEvalZero __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1361*150812a8SEvalZero __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1362*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1363*150812a8SEvalZero __IM uint32_t RESERVED14[2]; 1364*150812a8SEvalZero __IOM SPIM_IFTIMING_Type IFTIMING; /*!< (@ 0x00000560) Unspecified */ 1365*150812a8SEvalZero __IOM uint32_t CSNPOL; /*!< (@ 0x00000568) Polarity of CSN output */ 1366*150812a8SEvalZero __IOM uint32_t PSELDCX; /*!< (@ 0x0000056C) Pin select for DCX signal */ 1367*150812a8SEvalZero __IOM uint32_t DCXCNT; /*!< (@ 0x00000570) DCX configuration */ 1368*150812a8SEvalZero __IM uint32_t RESERVED15[19]; 1369*150812a8SEvalZero __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have 1370*150812a8SEvalZero been transmitted in the case when RXD.MAXCNT 1371*150812a8SEvalZero is greater than TXD.MAXCNT */ 1372*150812a8SEvalZero } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1373*150812a8SEvalZero 1374*150812a8SEvalZero 1375*150812a8SEvalZero 1376*150812a8SEvalZero /* =========================================================================================================================== */ 1377*150812a8SEvalZero /* ================ SPIS0 ================ */ 1378*150812a8SEvalZero /* =========================================================================================================================== */ 1379*150812a8SEvalZero 1380*150812a8SEvalZero 1381*150812a8SEvalZero /** 1382*150812a8SEvalZero * @brief SPI Slave 0 (SPIS0) 1383*150812a8SEvalZero */ 1384*150812a8SEvalZero 1385*150812a8SEvalZero typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ 1386*150812a8SEvalZero __IM uint32_t RESERVED[9]; 1387*150812a8SEvalZero __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1388*150812a8SEvalZero __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1389*150812a8SEvalZero to acquire it */ 1390*150812a8SEvalZero __IM uint32_t RESERVED1[54]; 1391*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1392*150812a8SEvalZero __IM uint32_t RESERVED2[2]; 1393*150812a8SEvalZero __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1394*150812a8SEvalZero __IM uint32_t RESERVED3[5]; 1395*150812a8SEvalZero __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1396*150812a8SEvalZero __IM uint32_t RESERVED4[53]; 1397*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1398*150812a8SEvalZero __IM uint32_t RESERVED5[64]; 1399*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1400*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1401*150812a8SEvalZero __IM uint32_t RESERVED6[61]; 1402*150812a8SEvalZero __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1403*150812a8SEvalZero __IM uint32_t RESERVED7[15]; 1404*150812a8SEvalZero __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1405*150812a8SEvalZero __IM uint32_t RESERVED8[47]; 1406*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1407*150812a8SEvalZero __IM uint32_t RESERVED9; 1408*150812a8SEvalZero __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1409*150812a8SEvalZero __IM uint32_t RESERVED10[7]; 1410*150812a8SEvalZero __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1411*150812a8SEvalZero __IM uint32_t RESERVED11; 1412*150812a8SEvalZero __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1413*150812a8SEvalZero __IM uint32_t RESERVED12; 1414*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1415*150812a8SEvalZero __IM uint32_t RESERVED13; 1416*150812a8SEvalZero __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1417*150812a8SEvalZero of an ignored transaction. */ 1418*150812a8SEvalZero __IM uint32_t RESERVED14[24]; 1419*150812a8SEvalZero __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1420*150812a8SEvalZero } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1421*150812a8SEvalZero 1422*150812a8SEvalZero 1423*150812a8SEvalZero 1424*150812a8SEvalZero /* =========================================================================================================================== */ 1425*150812a8SEvalZero /* ================ TWI0 ================ */ 1426*150812a8SEvalZero /* =========================================================================================================================== */ 1427*150812a8SEvalZero 1428*150812a8SEvalZero 1429*150812a8SEvalZero /** 1430*150812a8SEvalZero * @brief I2C compatible Two-Wire Interface 0 (TWI0) 1431*150812a8SEvalZero */ 1432*150812a8SEvalZero 1433*150812a8SEvalZero typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ 1434*150812a8SEvalZero __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1435*150812a8SEvalZero __IM uint32_t RESERVED; 1436*150812a8SEvalZero __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1437*150812a8SEvalZero __IM uint32_t RESERVED1[2]; 1438*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1439*150812a8SEvalZero __IM uint32_t RESERVED2; 1440*150812a8SEvalZero __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1441*150812a8SEvalZero __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1442*150812a8SEvalZero __IM uint32_t RESERVED3[56]; 1443*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1444*150812a8SEvalZero __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ 1445*150812a8SEvalZero __IM uint32_t RESERVED4[4]; 1446*150812a8SEvalZero __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ 1447*150812a8SEvalZero __IM uint32_t RESERVED5; 1448*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1449*150812a8SEvalZero __IM uint32_t RESERVED6[4]; 1450*150812a8SEvalZero __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte 1451*150812a8SEvalZero that is sent or received */ 1452*150812a8SEvalZero __IM uint32_t RESERVED7[3]; 1453*150812a8SEvalZero __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ 1454*150812a8SEvalZero __IM uint32_t RESERVED8[45]; 1455*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1456*150812a8SEvalZero __IM uint32_t RESERVED9[64]; 1457*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1458*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1459*150812a8SEvalZero __IM uint32_t RESERVED10[110]; 1460*150812a8SEvalZero __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1461*150812a8SEvalZero __IM uint32_t RESERVED11[14]; 1462*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ 1463*150812a8SEvalZero __IM uint32_t RESERVED12; 1464*150812a8SEvalZero __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1465*150812a8SEvalZero __IM uint32_t RESERVED13[2]; 1466*150812a8SEvalZero __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1467*150812a8SEvalZero __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1468*150812a8SEvalZero __IM uint32_t RESERVED14; 1469*150812a8SEvalZero __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1470*150812a8SEvalZero source selected. */ 1471*150812a8SEvalZero __IM uint32_t RESERVED15[24]; 1472*150812a8SEvalZero __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1473*150812a8SEvalZero } NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ 1474*150812a8SEvalZero 1475*150812a8SEvalZero 1476*150812a8SEvalZero 1477*150812a8SEvalZero /* =========================================================================================================================== */ 1478*150812a8SEvalZero /* ================ TWIM0 ================ */ 1479*150812a8SEvalZero /* =========================================================================================================================== */ 1480*150812a8SEvalZero 1481*150812a8SEvalZero 1482*150812a8SEvalZero /** 1483*150812a8SEvalZero * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) 1484*150812a8SEvalZero */ 1485*150812a8SEvalZero 1486*150812a8SEvalZero typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ 1487*150812a8SEvalZero __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1488*150812a8SEvalZero __IM uint32_t RESERVED; 1489*150812a8SEvalZero __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1490*150812a8SEvalZero __IM uint32_t RESERVED1[2]; 1491*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1492*150812a8SEvalZero TWI master is not suspended. */ 1493*150812a8SEvalZero __IM uint32_t RESERVED2; 1494*150812a8SEvalZero __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1495*150812a8SEvalZero __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1496*150812a8SEvalZero __IM uint32_t RESERVED3[56]; 1497*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1498*150812a8SEvalZero __IM uint32_t RESERVED4[7]; 1499*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1500*150812a8SEvalZero __IM uint32_t RESERVED5[8]; 1501*150812a8SEvalZero __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND 1502*150812a8SEvalZero task has been issued, TWI traffic is now 1503*150812a8SEvalZero suspended. */ 1504*150812a8SEvalZero __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1505*150812a8SEvalZero __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1506*150812a8SEvalZero __IM uint32_t RESERVED6[2]; 1507*150812a8SEvalZero __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1508*150812a8SEvalZero __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1509*150812a8SEvalZero byte */ 1510*150812a8SEvalZero __IM uint32_t RESERVED7[39]; 1511*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1512*150812a8SEvalZero __IM uint32_t RESERVED8[63]; 1513*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1514*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1515*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1516*150812a8SEvalZero __IM uint32_t RESERVED9[110]; 1517*150812a8SEvalZero __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1518*150812a8SEvalZero __IM uint32_t RESERVED10[14]; 1519*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1520*150812a8SEvalZero __IM uint32_t RESERVED11; 1521*150812a8SEvalZero __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1522*150812a8SEvalZero __IM uint32_t RESERVED12[5]; 1523*150812a8SEvalZero __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1524*150812a8SEvalZero source selected. */ 1525*150812a8SEvalZero __IM uint32_t RESERVED13[3]; 1526*150812a8SEvalZero __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1527*150812a8SEvalZero __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1528*150812a8SEvalZero __IM uint32_t RESERVED14[13]; 1529*150812a8SEvalZero __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1530*150812a8SEvalZero } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1531*150812a8SEvalZero 1532*150812a8SEvalZero 1533*150812a8SEvalZero 1534*150812a8SEvalZero /* =========================================================================================================================== */ 1535*150812a8SEvalZero /* ================ TWIS0 ================ */ 1536*150812a8SEvalZero /* =========================================================================================================================== */ 1537*150812a8SEvalZero 1538*150812a8SEvalZero 1539*150812a8SEvalZero /** 1540*150812a8SEvalZero * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) 1541*150812a8SEvalZero */ 1542*150812a8SEvalZero 1543*150812a8SEvalZero typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ 1544*150812a8SEvalZero __IM uint32_t RESERVED[5]; 1545*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1546*150812a8SEvalZero __IM uint32_t RESERVED1; 1547*150812a8SEvalZero __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1548*150812a8SEvalZero __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1549*150812a8SEvalZero __IM uint32_t RESERVED2[3]; 1550*150812a8SEvalZero __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1551*150812a8SEvalZero __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1552*150812a8SEvalZero __IM uint32_t RESERVED3[51]; 1553*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1554*150812a8SEvalZero __IM uint32_t RESERVED4[7]; 1555*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1556*150812a8SEvalZero __IM uint32_t RESERVED5[9]; 1557*150812a8SEvalZero __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1558*150812a8SEvalZero __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1559*150812a8SEvalZero __IM uint32_t RESERVED6[4]; 1560*150812a8SEvalZero __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1561*150812a8SEvalZero __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1562*150812a8SEvalZero __IM uint32_t RESERVED7[37]; 1563*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1564*150812a8SEvalZero __IM uint32_t RESERVED8[63]; 1565*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1566*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1567*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1568*150812a8SEvalZero __IM uint32_t RESERVED9[113]; 1569*150812a8SEvalZero __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1570*150812a8SEvalZero __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1571*150812a8SEvalZero a match */ 1572*150812a8SEvalZero __IM uint32_t RESERVED10[10]; 1573*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1574*150812a8SEvalZero __IM uint32_t RESERVED11; 1575*150812a8SEvalZero __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1576*150812a8SEvalZero __IM uint32_t RESERVED12[9]; 1577*150812a8SEvalZero __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1578*150812a8SEvalZero __IM uint32_t RESERVED13; 1579*150812a8SEvalZero __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1580*150812a8SEvalZero __IM uint32_t RESERVED14[14]; 1581*150812a8SEvalZero __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[n]: TWI slave address 1582*150812a8SEvalZero n */ 1583*150812a8SEvalZero __IM uint32_t RESERVED15; 1584*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1585*150812a8SEvalZero mechanism */ 1586*150812a8SEvalZero __IM uint32_t RESERVED16[10]; 1587*150812a8SEvalZero __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1588*150812a8SEvalZero of an over-read of the transmit buffer. */ 1589*150812a8SEvalZero } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1590*150812a8SEvalZero 1591*150812a8SEvalZero 1592*150812a8SEvalZero 1593*150812a8SEvalZero /* =========================================================================================================================== */ 1594*150812a8SEvalZero /* ================ NFCT ================ */ 1595*150812a8SEvalZero /* =========================================================================================================================== */ 1596*150812a8SEvalZero 1597*150812a8SEvalZero 1598*150812a8SEvalZero /** 1599*150812a8SEvalZero * @brief NFC-A compatible radio (NFCT) 1600*150812a8SEvalZero */ 1601*150812a8SEvalZero 1602*150812a8SEvalZero typedef struct { /*!< (@ 0x40005000) NFCT Structure */ 1603*150812a8SEvalZero __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFCT peripheral for incoming and outgoing 1604*150812a8SEvalZero frames, change state to activated */ 1605*150812a8SEvalZero __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFCT peripheral */ 1606*150812a8SEvalZero __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to 1607*150812a8SEvalZero sense mode */ 1608*150812a8SEvalZero __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of an outgoing frame, change 1609*150812a8SEvalZero state to transmit */ 1610*150812a8SEvalZero __IM uint32_t RESERVED[3]; 1611*150812a8SEvalZero __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ 1612*150812a8SEvalZero __IM uint32_t RESERVED1; 1613*150812a8SEvalZero __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ 1614*150812a8SEvalZero __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ 1615*150812a8SEvalZero __IM uint32_t RESERVED2[53]; 1616*150812a8SEvalZero __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFCT peripheral is ready to receive and send 1617*150812a8SEvalZero frames */ 1618*150812a8SEvalZero __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ 1619*150812a8SEvalZero __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ 1620*150812a8SEvalZero __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted 1621*150812a8SEvalZero frame */ 1622*150812a8SEvalZero __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air 1623*150812a8SEvalZero symbol of a frame */ 1624*150812a8SEvalZero __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received 1625*150812a8SEvalZero frame */ 1626*150812a8SEvalZero __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data has been checked (CRC, parity) 1627*150812a8SEvalZero and transferred to RAM, and EasyDMA has 1628*150812a8SEvalZero ended accessing the RX buffer */ 1629*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register 1630*150812a8SEvalZero contains details on the source of the error. */ 1631*150812a8SEvalZero __IM uint32_t RESERVED3[2]; 1632*150812a8SEvalZero __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX 1633*150812a8SEvalZero register contains details on the source 1634*150812a8SEvalZero of the error. */ 1635*150812a8SEvalZero __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) 1636*150812a8SEvalZero in Data RAM full. */ 1637*150812a8SEvalZero __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA 1638*150812a8SEvalZero has ended accessing the TX buffer */ 1639*150812a8SEvalZero __IM uint32_t RESERVED4; 1640*150812a8SEvalZero __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ 1641*150812a8SEvalZero __IM uint32_t RESERVED5[3]; 1642*150812a8SEvalZero __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC auto collision resolution error reported. */ 1643*150812a8SEvalZero __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed */ 1644*150812a8SEvalZero __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ 1645*150812a8SEvalZero __IM uint32_t RESERVED6[43]; 1646*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1647*150812a8SEvalZero __IM uint32_t RESERVED7[63]; 1648*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1649*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1650*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1651*150812a8SEvalZero __IM uint32_t RESERVED8[62]; 1652*150812a8SEvalZero __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ 1653*150812a8SEvalZero __IM uint32_t RESERVED9; 1654*150812a8SEvalZero __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ 1655*150812a8SEvalZero __IM uint32_t NFCTAGSTATE; /*!< (@ 0x00000410) NfcTag state register */ 1656*150812a8SEvalZero __IM uint32_t RESERVED10[3]; 1657*150812a8SEvalZero __IM uint32_t SLEEPSTATE; /*!< (@ 0x00000420) Sleep state during automatic collision resolution */ 1658*150812a8SEvalZero __IM uint32_t RESERVED11[6]; 1659*150812a8SEvalZero __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ 1660*150812a8SEvalZero __IM uint32_t RESERVED12[49]; 1661*150812a8SEvalZero __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ 1662*150812a8SEvalZero __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ 1663*150812a8SEvalZero __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ 1664*150812a8SEvalZero __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in 1665*150812a8SEvalZero Data RAM */ 1666*150812a8SEvalZero __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of the RAM buffer allocated to TXD and RXD 1667*150812a8SEvalZero data storage each */ 1668*150812a8SEvalZero __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ 1669*150812a8SEvalZero __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ 1670*150812a8SEvalZero __IM uint32_t RESERVED13[26]; 1671*150812a8SEvalZero __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ 1672*150812a8SEvalZero __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ 1673*150812a8SEvalZero __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ 1674*150812a8SEvalZero __IOM uint32_t AUTOCOLRESCONFIG; /*!< (@ 0x0000059C) Controls the auto collision resolution function. 1675*150812a8SEvalZero This setting must be done before the NFCT 1676*150812a8SEvalZero peripheral is enabled. */ 1677*150812a8SEvalZero __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ 1678*150812a8SEvalZero __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ 1679*150812a8SEvalZero } NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ 1680*150812a8SEvalZero 1681*150812a8SEvalZero 1682*150812a8SEvalZero 1683*150812a8SEvalZero /* =========================================================================================================================== */ 1684*150812a8SEvalZero /* ================ GPIOTE ================ */ 1685*150812a8SEvalZero /* =========================================================================================================================== */ 1686*150812a8SEvalZero 1687*150812a8SEvalZero 1688*150812a8SEvalZero /** 1689*150812a8SEvalZero * @brief GPIO Tasks and Events (GPIOTE) 1690*150812a8SEvalZero */ 1691*150812a8SEvalZero 1692*150812a8SEvalZero typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 1693*150812a8SEvalZero __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[n]: Task for writing to 1694*150812a8SEvalZero pin specified in CONFIG[n].PSEL. Action 1695*150812a8SEvalZero on pin is configured in CONFIG[n].POLARITY. */ 1696*150812a8SEvalZero __IM uint32_t RESERVED[4]; 1697*150812a8SEvalZero __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[n]: Task for writing to 1698*150812a8SEvalZero pin specified in CONFIG[n].PSEL. Action 1699*150812a8SEvalZero on pin is to set it high. */ 1700*150812a8SEvalZero __IM uint32_t RESERVED1[4]; 1701*150812a8SEvalZero __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[n]: Task for writing to 1702*150812a8SEvalZero pin specified in CONFIG[n].PSEL. Action 1703*150812a8SEvalZero on pin is to set it low. */ 1704*150812a8SEvalZero __IM uint32_t RESERVED2[32]; 1705*150812a8SEvalZero __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[n]: Event generated from 1706*150812a8SEvalZero pin specified in CONFIG[n].PSEL */ 1707*150812a8SEvalZero __IM uint32_t RESERVED3[23]; 1708*150812a8SEvalZero __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1709*150812a8SEvalZero with SENSE mechanism enabled */ 1710*150812a8SEvalZero __IM uint32_t RESERVED4[97]; 1711*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1712*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1713*150812a8SEvalZero __IM uint32_t RESERVED5[129]; 1714*150812a8SEvalZero __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[n]: Configuration for 1715*150812a8SEvalZero OUT[n], SET[n] and CLR[n] tasks and IN[n] 1716*150812a8SEvalZero event */ 1717*150812a8SEvalZero } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1718*150812a8SEvalZero 1719*150812a8SEvalZero 1720*150812a8SEvalZero 1721*150812a8SEvalZero /* =========================================================================================================================== */ 1722*150812a8SEvalZero /* ================ SAADC ================ */ 1723*150812a8SEvalZero /* =========================================================================================================================== */ 1724*150812a8SEvalZero 1725*150812a8SEvalZero 1726*150812a8SEvalZero /** 1727*150812a8SEvalZero * @brief Successive approximation register (SAR) analog-to-digital converter (SAADC) 1728*150812a8SEvalZero */ 1729*150812a8SEvalZero 1730*150812a8SEvalZero typedef struct { /*!< (@ 0x40007000) SAADC Structure */ 1731*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts the SAADC and prepares the result buffer 1732*150812a8SEvalZero in RAM */ 1733*150812a8SEvalZero __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Takes one SAADC sample */ 1734*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stops the SAADC and terminates all on-going conversions */ 1735*150812a8SEvalZero __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1736*150812a8SEvalZero __IM uint32_t RESERVED[60]; 1737*150812a8SEvalZero __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The SAADC has started */ 1738*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The SAADC has filled up the result buffer */ 1739*150812a8SEvalZero __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1740*150812a8SEvalZero on the configuration, multiple conversions 1741*150812a8SEvalZero might be needed for a result to be transferred 1742*150812a8SEvalZero to RAM. */ 1743*150812a8SEvalZero __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) Result ready for transfer to RAM */ 1744*150812a8SEvalZero __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1745*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The SAADC has stopped */ 1746*150812a8SEvalZero __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */ 1747*150812a8SEvalZero __IM uint32_t RESERVED1[106]; 1748*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1749*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1750*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1751*150812a8SEvalZero __IM uint32_t RESERVED2[61]; 1752*150812a8SEvalZero __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1753*150812a8SEvalZero __IM uint32_t RESERVED3[63]; 1754*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable SAADC */ 1755*150812a8SEvalZero __IM uint32_t RESERVED4[3]; 1756*150812a8SEvalZero __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1757*150812a8SEvalZero __IM uint32_t RESERVED5[24]; 1758*150812a8SEvalZero __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1759*150812a8SEvalZero __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. The RESOLUTION is 1760*150812a8SEvalZero applied before averaging, thus for high 1761*150812a8SEvalZero OVERSAMPLE a higher RESOLUTION should be 1762*150812a8SEvalZero used. */ 1763*150812a8SEvalZero __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1764*150812a8SEvalZero __IM uint32_t RESERVED6[12]; 1765*150812a8SEvalZero __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1766*150812a8SEvalZero } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1767*150812a8SEvalZero 1768*150812a8SEvalZero 1769*150812a8SEvalZero 1770*150812a8SEvalZero /* =========================================================================================================================== */ 1771*150812a8SEvalZero /* ================ TIMER0 ================ */ 1772*150812a8SEvalZero /* =========================================================================================================================== */ 1773*150812a8SEvalZero 1774*150812a8SEvalZero 1775*150812a8SEvalZero /** 1776*150812a8SEvalZero * @brief Timer/Counter 0 (TIMER0) 1777*150812a8SEvalZero */ 1778*150812a8SEvalZero 1779*150812a8SEvalZero typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 1780*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1781*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1782*150812a8SEvalZero __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1783*150812a8SEvalZero __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1784*150812a8SEvalZero __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1785*150812a8SEvalZero __IM uint32_t RESERVED[11]; 1786*150812a8SEvalZero __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[n]: Capture Timer value 1787*150812a8SEvalZero to CC[n] register */ 1788*150812a8SEvalZero __IM uint32_t RESERVED1[58]; 1789*150812a8SEvalZero __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] 1790*150812a8SEvalZero match */ 1791*150812a8SEvalZero __IM uint32_t RESERVED2[42]; 1792*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1793*150812a8SEvalZero __IM uint32_t RESERVED3[64]; 1794*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1795*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1796*150812a8SEvalZero __IM uint32_t RESERVED4[126]; 1797*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1798*150812a8SEvalZero __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1799*150812a8SEvalZero __IM uint32_t RESERVED5; 1800*150812a8SEvalZero __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1801*150812a8SEvalZero __IM uint32_t RESERVED6[11]; 1802*150812a8SEvalZero __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[n]: Capture/Compare register 1803*150812a8SEvalZero n */ 1804*150812a8SEvalZero } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1805*150812a8SEvalZero 1806*150812a8SEvalZero 1807*150812a8SEvalZero 1808*150812a8SEvalZero /* =========================================================================================================================== */ 1809*150812a8SEvalZero /* ================ RTC0 ================ */ 1810*150812a8SEvalZero /* =========================================================================================================================== */ 1811*150812a8SEvalZero 1812*150812a8SEvalZero 1813*150812a8SEvalZero /** 1814*150812a8SEvalZero * @brief Real time counter 0 (RTC0) 1815*150812a8SEvalZero */ 1816*150812a8SEvalZero 1817*150812a8SEvalZero typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 1818*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ 1819*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ 1820*150812a8SEvalZero __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ 1821*150812a8SEvalZero __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ 1822*150812a8SEvalZero __IM uint32_t RESERVED[60]; 1823*150812a8SEvalZero __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ 1824*150812a8SEvalZero __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ 1825*150812a8SEvalZero __IM uint32_t RESERVED1[14]; 1826*150812a8SEvalZero __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] 1827*150812a8SEvalZero match */ 1828*150812a8SEvalZero __IM uint32_t RESERVED2[109]; 1829*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1830*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1831*150812a8SEvalZero __IM uint32_t RESERVED3[13]; 1832*150812a8SEvalZero __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1833*150812a8SEvalZero __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1834*150812a8SEvalZero __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1835*150812a8SEvalZero __IM uint32_t RESERVED4[110]; 1836*150812a8SEvalZero __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ 1837*150812a8SEvalZero __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu 1838*150812a8SEvalZero t be written when RTC is stopped */ 1839*150812a8SEvalZero __IM uint32_t RESERVED5[13]; 1840*150812a8SEvalZero __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[n]: Compare register n */ 1841*150812a8SEvalZero } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1842*150812a8SEvalZero 1843*150812a8SEvalZero 1844*150812a8SEvalZero 1845*150812a8SEvalZero /* =========================================================================================================================== */ 1846*150812a8SEvalZero /* ================ TEMP ================ */ 1847*150812a8SEvalZero /* =========================================================================================================================== */ 1848*150812a8SEvalZero 1849*150812a8SEvalZero 1850*150812a8SEvalZero /** 1851*150812a8SEvalZero * @brief Temperature Sensor (TEMP) 1852*150812a8SEvalZero */ 1853*150812a8SEvalZero 1854*150812a8SEvalZero typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 1855*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 1856*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 1857*150812a8SEvalZero __IM uint32_t RESERVED[62]; 1858*150812a8SEvalZero __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 1859*150812a8SEvalZero __IM uint32_t RESERVED1[128]; 1860*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1861*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1862*150812a8SEvalZero __IM uint32_t RESERVED2[127]; 1863*150812a8SEvalZero __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 1864*150812a8SEvalZero __IM uint32_t RESERVED3[5]; 1865*150812a8SEvalZero __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ 1866*150812a8SEvalZero __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ 1867*150812a8SEvalZero __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ 1868*150812a8SEvalZero __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ 1869*150812a8SEvalZero __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ 1870*150812a8SEvalZero __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ 1871*150812a8SEvalZero __IM uint32_t RESERVED4[2]; 1872*150812a8SEvalZero __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ 1873*150812a8SEvalZero __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ 1874*150812a8SEvalZero __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ 1875*150812a8SEvalZero __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ 1876*150812a8SEvalZero __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ 1877*150812a8SEvalZero __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ 1878*150812a8SEvalZero __IM uint32_t RESERVED5[2]; 1879*150812a8SEvalZero __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ 1880*150812a8SEvalZero __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ 1881*150812a8SEvalZero __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ 1882*150812a8SEvalZero __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ 1883*150812a8SEvalZero __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ 1884*150812a8SEvalZero } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 1885*150812a8SEvalZero 1886*150812a8SEvalZero 1887*150812a8SEvalZero 1888*150812a8SEvalZero /* =========================================================================================================================== */ 1889*150812a8SEvalZero /* ================ RNG ================ */ 1890*150812a8SEvalZero /* =========================================================================================================================== */ 1891*150812a8SEvalZero 1892*150812a8SEvalZero 1893*150812a8SEvalZero /** 1894*150812a8SEvalZero * @brief Random Number Generator (RNG) 1895*150812a8SEvalZero */ 1896*150812a8SEvalZero 1897*150812a8SEvalZero typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 1898*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 1899*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 1900*150812a8SEvalZero __IM uint32_t RESERVED[62]; 1901*150812a8SEvalZero __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 1902*150812a8SEvalZero written to the VALUE register */ 1903*150812a8SEvalZero __IM uint32_t RESERVED1[63]; 1904*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1905*150812a8SEvalZero __IM uint32_t RESERVED2[64]; 1906*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1907*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1908*150812a8SEvalZero __IM uint32_t RESERVED3[126]; 1909*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1910*150812a8SEvalZero __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 1911*150812a8SEvalZero } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 1912*150812a8SEvalZero 1913*150812a8SEvalZero 1914*150812a8SEvalZero 1915*150812a8SEvalZero /* =========================================================================================================================== */ 1916*150812a8SEvalZero /* ================ ECB ================ */ 1917*150812a8SEvalZero /* =========================================================================================================================== */ 1918*150812a8SEvalZero 1919*150812a8SEvalZero 1920*150812a8SEvalZero /** 1921*150812a8SEvalZero * @brief AES ECB Mode Encryption (ECB) 1922*150812a8SEvalZero */ 1923*150812a8SEvalZero 1924*150812a8SEvalZero typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 1925*150812a8SEvalZero __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1926*150812a8SEvalZero __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1927*150812a8SEvalZero __IM uint32_t RESERVED[62]; 1928*150812a8SEvalZero __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1929*150812a8SEvalZero __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1930*150812a8SEvalZero task or due to an error */ 1931*150812a8SEvalZero __IM uint32_t RESERVED1[127]; 1932*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1933*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1934*150812a8SEvalZero __IM uint32_t RESERVED2[126]; 1935*150812a8SEvalZero __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1936*150812a8SEvalZero } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1937*150812a8SEvalZero 1938*150812a8SEvalZero 1939*150812a8SEvalZero 1940*150812a8SEvalZero /* =========================================================================================================================== */ 1941*150812a8SEvalZero /* ================ AAR ================ */ 1942*150812a8SEvalZero /* =========================================================================================================================== */ 1943*150812a8SEvalZero 1944*150812a8SEvalZero 1945*150812a8SEvalZero /** 1946*150812a8SEvalZero * @brief Accelerated Address Resolver (AAR) 1947*150812a8SEvalZero */ 1948*150812a8SEvalZero 1949*150812a8SEvalZero typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 1950*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 1951*150812a8SEvalZero in the IRK data structure */ 1952*150812a8SEvalZero __IM uint32_t RESERVED; 1953*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 1954*150812a8SEvalZero __IM uint32_t RESERVED1[61]; 1955*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 1956*150812a8SEvalZero __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 1957*150812a8SEvalZero __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 1958*150812a8SEvalZero __IM uint32_t RESERVED2[126]; 1959*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1960*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1961*150812a8SEvalZero __IM uint32_t RESERVED3[61]; 1962*150812a8SEvalZero __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 1963*150812a8SEvalZero __IM uint32_t RESERVED4[63]; 1964*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 1965*150812a8SEvalZero __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 1966*150812a8SEvalZero __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 1967*150812a8SEvalZero __IM uint32_t RESERVED5; 1968*150812a8SEvalZero __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 1969*150812a8SEvalZero __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1970*150812a8SEvalZero } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 1971*150812a8SEvalZero 1972*150812a8SEvalZero 1973*150812a8SEvalZero 1974*150812a8SEvalZero /* =========================================================================================================================== */ 1975*150812a8SEvalZero /* ================ CCM ================ */ 1976*150812a8SEvalZero /* =========================================================================================================================== */ 1977*150812a8SEvalZero 1978*150812a8SEvalZero 1979*150812a8SEvalZero /** 1980*150812a8SEvalZero * @brief AES CCM Mode Encryption (CCM) 1981*150812a8SEvalZero */ 1982*150812a8SEvalZero 1983*150812a8SEvalZero typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 1984*150812a8SEvalZero __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation 1985*150812a8SEvalZero will stop by itself when completed. */ 1986*150812a8SEvalZero __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 1987*150812a8SEvalZero stop by itself when completed. */ 1988*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 1989*150812a8SEvalZero __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with 1990*150812a8SEvalZero the contents of the RATEOVERRIDE register 1991*150812a8SEvalZero for any ongoing encryption/decryption */ 1992*150812a8SEvalZero __IM uint32_t RESERVED[60]; 1993*150812a8SEvalZero __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ 1994*150812a8SEvalZero __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 1995*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ 1996*150812a8SEvalZero __IM uint32_t RESERVED1[61]; 1997*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1998*150812a8SEvalZero __IM uint32_t RESERVED2[64]; 1999*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2000*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2001*150812a8SEvalZero __IM uint32_t RESERVED3[61]; 2002*150812a8SEvalZero __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 2003*150812a8SEvalZero __IM uint32_t RESERVED4[63]; 2004*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 2005*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 2006*150812a8SEvalZero __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and 2007*150812a8SEvalZero NONCE vector */ 2008*150812a8SEvalZero __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 2009*150812a8SEvalZero __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 2010*150812a8SEvalZero __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 2011*150812a8SEvalZero __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH 2012*150812a8SEvalZero = Extended. */ 2013*150812a8SEvalZero __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ 2014*150812a8SEvalZero } NRF_CCM_Type; /*!< Size = 1312 (0x520) */ 2015*150812a8SEvalZero 2016*150812a8SEvalZero 2017*150812a8SEvalZero 2018*150812a8SEvalZero /* =========================================================================================================================== */ 2019*150812a8SEvalZero /* ================ WDT ================ */ 2020*150812a8SEvalZero /* =========================================================================================================================== */ 2021*150812a8SEvalZero 2022*150812a8SEvalZero 2023*150812a8SEvalZero /** 2024*150812a8SEvalZero * @brief Watchdog Timer (WDT) 2025*150812a8SEvalZero */ 2026*150812a8SEvalZero 2027*150812a8SEvalZero typedef struct { /*!< (@ 0x40010000) WDT Structure */ 2028*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 2029*150812a8SEvalZero __IM uint32_t RESERVED[63]; 2030*150812a8SEvalZero __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 2031*150812a8SEvalZero __IM uint32_t RESERVED1[128]; 2032*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2033*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2034*150812a8SEvalZero __IM uint32_t RESERVED2[61]; 2035*150812a8SEvalZero __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 2036*150812a8SEvalZero __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 2037*150812a8SEvalZero __IM uint32_t RESERVED3[63]; 2038*150812a8SEvalZero __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 2039*150812a8SEvalZero __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 2040*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 2041*150812a8SEvalZero __IM uint32_t RESERVED4[60]; 2042*150812a8SEvalZero __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[n]: Reload request n */ 2043*150812a8SEvalZero } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 2044*150812a8SEvalZero 2045*150812a8SEvalZero 2046*150812a8SEvalZero 2047*150812a8SEvalZero /* =========================================================================================================================== */ 2048*150812a8SEvalZero /* ================ QDEC ================ */ 2049*150812a8SEvalZero /* =========================================================================================================================== */ 2050*150812a8SEvalZero 2051*150812a8SEvalZero 2052*150812a8SEvalZero /** 2053*150812a8SEvalZero * @brief Quadrature Decoder (QDEC) 2054*150812a8SEvalZero */ 2055*150812a8SEvalZero 2056*150812a8SEvalZero typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 2057*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ 2058*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ 2059*150812a8SEvalZero __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ 2060*150812a8SEvalZero __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ 2061*150812a8SEvalZero __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ 2062*150812a8SEvalZero __IM uint32_t RESERVED[59]; 2063*150812a8SEvalZero __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value 2064*150812a8SEvalZero written to the SAMPLE register */ 2065*150812a8SEvalZero __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ 2066*150812a8SEvalZero __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ 2067*150812a8SEvalZero __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ 2068*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ 2069*150812a8SEvalZero __IM uint32_t RESERVED1[59]; 2070*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 2071*150812a8SEvalZero __IM uint32_t RESERVED2[64]; 2072*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2073*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2074*150812a8SEvalZero __IM uint32_t RESERVED3[125]; 2075*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ 2076*150812a8SEvalZero __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ 2077*150812a8SEvalZero __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ 2078*150812a8SEvalZero __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ 2079*150812a8SEvalZero __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY 2080*150812a8SEvalZero and DBLRDY events can be generated */ 2081*150812a8SEvalZero __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ 2082*150812a8SEvalZero __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the 2083*150812a8SEvalZero READCLRACC or RDCLRACC task */ 2084*150812a8SEvalZero __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ 2085*150812a8SEvalZero __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ 2086*150812a8SEvalZero __IM uint32_t RESERVED4[5]; 2087*150812a8SEvalZero __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ 2088*150812a8SEvalZero __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected 2089*150812a8SEvalZero double transitions */ 2090*150812a8SEvalZero __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC 2091*150812a8SEvalZero or RDCLRDBL task */ 2092*150812a8SEvalZero } NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ 2093*150812a8SEvalZero 2094*150812a8SEvalZero 2095*150812a8SEvalZero 2096*150812a8SEvalZero /* =========================================================================================================================== */ 2097*150812a8SEvalZero /* ================ COMP ================ */ 2098*150812a8SEvalZero /* =========================================================================================================================== */ 2099*150812a8SEvalZero 2100*150812a8SEvalZero 2101*150812a8SEvalZero /** 2102*150812a8SEvalZero * @brief Comparator (COMP) 2103*150812a8SEvalZero */ 2104*150812a8SEvalZero 2105*150812a8SEvalZero typedef struct { /*!< (@ 0x40013000) COMP Structure */ 2106*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 2107*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 2108*150812a8SEvalZero __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 2109*150812a8SEvalZero __IM uint32_t RESERVED[61]; 2110*150812a8SEvalZero __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ 2111*150812a8SEvalZero __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 2112*150812a8SEvalZero __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 2113*150812a8SEvalZero __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 2114*150812a8SEvalZero __IM uint32_t RESERVED1[60]; 2115*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 2116*150812a8SEvalZero __IM uint32_t RESERVED2[63]; 2117*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2118*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2119*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2120*150812a8SEvalZero __IM uint32_t RESERVED3[61]; 2121*150812a8SEvalZero __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 2122*150812a8SEvalZero __IM uint32_t RESERVED4[63]; 2123*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ 2124*150812a8SEvalZero __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ 2125*150812a8SEvalZero __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ 2126*150812a8SEvalZero __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 2127*150812a8SEvalZero __IM uint32_t RESERVED5[8]; 2128*150812a8SEvalZero __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ 2129*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ 2130*150812a8SEvalZero __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 2131*150812a8SEvalZero } NRF_COMP_Type; /*!< Size = 1340 (0x53c) */ 2132*150812a8SEvalZero 2133*150812a8SEvalZero 2134*150812a8SEvalZero 2135*150812a8SEvalZero /* =========================================================================================================================== */ 2136*150812a8SEvalZero /* ================ LPCOMP ================ */ 2137*150812a8SEvalZero /* =========================================================================================================================== */ 2138*150812a8SEvalZero 2139*150812a8SEvalZero 2140*150812a8SEvalZero /** 2141*150812a8SEvalZero * @brief Low Power Comparator (LPCOMP) 2142*150812a8SEvalZero */ 2143*150812a8SEvalZero 2144*150812a8SEvalZero typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ 2145*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 2146*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 2147*150812a8SEvalZero __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 2148*150812a8SEvalZero __IM uint32_t RESERVED[61]; 2149*150812a8SEvalZero __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ 2150*150812a8SEvalZero __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 2151*150812a8SEvalZero __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 2152*150812a8SEvalZero __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 2153*150812a8SEvalZero __IM uint32_t RESERVED1[60]; 2154*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 2155*150812a8SEvalZero __IM uint32_t RESERVED2[64]; 2156*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2157*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2158*150812a8SEvalZero __IM uint32_t RESERVED3[61]; 2159*150812a8SEvalZero __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 2160*150812a8SEvalZero __IM uint32_t RESERVED4[63]; 2161*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ 2162*150812a8SEvalZero __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ 2163*150812a8SEvalZero __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ 2164*150812a8SEvalZero __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 2165*150812a8SEvalZero __IM uint32_t RESERVED5[4]; 2166*150812a8SEvalZero __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ 2167*150812a8SEvalZero __IM uint32_t RESERVED6[5]; 2168*150812a8SEvalZero __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 2169*150812a8SEvalZero } NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ 2170*150812a8SEvalZero 2171*150812a8SEvalZero 2172*150812a8SEvalZero 2173*150812a8SEvalZero /* =========================================================================================================================== */ 2174*150812a8SEvalZero /* ================ EGU0 ================ */ 2175*150812a8SEvalZero /* =========================================================================================================================== */ 2176*150812a8SEvalZero 2177*150812a8SEvalZero 2178*150812a8SEvalZero /** 2179*150812a8SEvalZero * @brief Event Generator Unit 0 (EGU0) 2180*150812a8SEvalZero */ 2181*150812a8SEvalZero 2182*150812a8SEvalZero typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ 2183*150812a8SEvalZero __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[n]: Trigger n for triggering 2184*150812a8SEvalZero the corresponding TRIGGERED[n] event */ 2185*150812a8SEvalZero __IM uint32_t RESERVED[48]; 2186*150812a8SEvalZero __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[n]: Event number n generated 2187*150812a8SEvalZero by triggering the corresponding TRIGGER[n] 2188*150812a8SEvalZero task */ 2189*150812a8SEvalZero __IM uint32_t RESERVED1[112]; 2190*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2191*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2192*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2193*150812a8SEvalZero } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 2194*150812a8SEvalZero 2195*150812a8SEvalZero 2196*150812a8SEvalZero 2197*150812a8SEvalZero /* =========================================================================================================================== */ 2198*150812a8SEvalZero /* ================ SWI0 ================ */ 2199*150812a8SEvalZero /* =========================================================================================================================== */ 2200*150812a8SEvalZero 2201*150812a8SEvalZero 2202*150812a8SEvalZero /** 2203*150812a8SEvalZero * @brief Software interrupt 0 (SWI0) 2204*150812a8SEvalZero */ 2205*150812a8SEvalZero 2206*150812a8SEvalZero typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ 2207*150812a8SEvalZero __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 2208*150812a8SEvalZero } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 2209*150812a8SEvalZero 2210*150812a8SEvalZero 2211*150812a8SEvalZero 2212*150812a8SEvalZero /* =========================================================================================================================== */ 2213*150812a8SEvalZero /* ================ PWM0 ================ */ 2214*150812a8SEvalZero /* =========================================================================================================================== */ 2215*150812a8SEvalZero 2216*150812a8SEvalZero 2217*150812a8SEvalZero /** 2218*150812a8SEvalZero * @brief Pulse width modulation unit 0 (PWM0) 2219*150812a8SEvalZero */ 2220*150812a8SEvalZero 2221*150812a8SEvalZero typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ 2222*150812a8SEvalZero __IM uint32_t RESERVED; 2223*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 2224*150812a8SEvalZero the end of current PWM period, and stops 2225*150812a8SEvalZero sequence playback */ 2226*150812a8SEvalZero __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[n]: Loads the first PWM 2227*150812a8SEvalZero value on all enabled channels from sequence 2228*150812a8SEvalZero n, and starts playing that sequence at the 2229*150812a8SEvalZero rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 2230*150812a8SEvalZero Causes PWM generation to start if not running. */ 2231*150812a8SEvalZero __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 2232*150812a8SEvalZero all enabled channels if DECODER.MODE=NextStep. 2233*150812a8SEvalZero Does not cause PWM generation to start if 2234*150812a8SEvalZero not running. */ 2235*150812a8SEvalZero __IM uint32_t RESERVED1[60]; 2236*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 2237*150812a8SEvalZero are no longer generated */ 2238*150812a8SEvalZero __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[n]: First PWM period started 2239*150812a8SEvalZero on sequence n */ 2240*150812a8SEvalZero __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[n]: Emitted at end of 2241*150812a8SEvalZero every sequence n, when last value from RAM 2242*150812a8SEvalZero has been applied to wave counter */ 2243*150812a8SEvalZero __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 2244*150812a8SEvalZero __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 2245*150812a8SEvalZero of times defined in LOOP.CNT */ 2246*150812a8SEvalZero __IM uint32_t RESERVED2[56]; 2247*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 2248*150812a8SEvalZero __IM uint32_t RESERVED3[63]; 2249*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2250*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2251*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2252*150812a8SEvalZero __IM uint32_t RESERVED4[125]; 2253*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 2254*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 2255*150812a8SEvalZero __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 2256*150812a8SEvalZero counts */ 2257*150812a8SEvalZero __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 2258*150812a8SEvalZero __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 2259*150812a8SEvalZero __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ 2260*150812a8SEvalZero __IM uint32_t RESERVED5[2]; 2261*150812a8SEvalZero __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 2262*150812a8SEvalZero __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2263*150812a8SEvalZero } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 2264*150812a8SEvalZero 2265*150812a8SEvalZero 2266*150812a8SEvalZero 2267*150812a8SEvalZero /* =========================================================================================================================== */ 2268*150812a8SEvalZero /* ================ PDM ================ */ 2269*150812a8SEvalZero /* =========================================================================================================================== */ 2270*150812a8SEvalZero 2271*150812a8SEvalZero 2272*150812a8SEvalZero /** 2273*150812a8SEvalZero * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) 2274*150812a8SEvalZero */ 2275*150812a8SEvalZero 2276*150812a8SEvalZero typedef struct { /*!< (@ 0x4001D000) PDM Structure */ 2277*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 2278*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 2279*150812a8SEvalZero __IM uint32_t RESERVED[62]; 2280*150812a8SEvalZero __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 2281*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 2282*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 2283*150812a8SEvalZero by SAMPLE.MAXCNT (or the last sample after 2284*150812a8SEvalZero a STOP task has been received) to Data RAM */ 2285*150812a8SEvalZero __IM uint32_t RESERVED1[125]; 2286*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2287*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2288*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2289*150812a8SEvalZero __IM uint32_t RESERVED2[125]; 2290*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 2291*150812a8SEvalZero __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 2292*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 2293*150812a8SEvalZero signals */ 2294*150812a8SEvalZero __IM uint32_t RESERVED3[3]; 2295*150812a8SEvalZero __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 2296*150812a8SEvalZero __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 2297*150812a8SEvalZero __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output 2298*150812a8SEvalZero sample rate. Change PDMCLKCTRL accordingly. */ 2299*150812a8SEvalZero __IM uint32_t RESERVED4[7]; 2300*150812a8SEvalZero __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 2301*150812a8SEvalZero __IM uint32_t RESERVED5[6]; 2302*150812a8SEvalZero __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 2303*150812a8SEvalZero } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 2304*150812a8SEvalZero 2305*150812a8SEvalZero 2306*150812a8SEvalZero 2307*150812a8SEvalZero /* =========================================================================================================================== */ 2308*150812a8SEvalZero /* ================ ACL ================ */ 2309*150812a8SEvalZero /* =========================================================================================================================== */ 2310*150812a8SEvalZero 2311*150812a8SEvalZero 2312*150812a8SEvalZero /** 2313*150812a8SEvalZero * @brief Access control lists (ACL) 2314*150812a8SEvalZero */ 2315*150812a8SEvalZero 2316*150812a8SEvalZero typedef struct { /*!< (@ 0x4001E000) ACL Structure */ 2317*150812a8SEvalZero __IM uint32_t RESERVED[512]; 2318*150812a8SEvalZero __IOM ACL_ACL_Type ACL[8]; /*!< (@ 0x00000800) Unspecified */ 2319*150812a8SEvalZero } NRF_ACL_Type; /*!< Size = 2176 (0x880) */ 2320*150812a8SEvalZero 2321*150812a8SEvalZero 2322*150812a8SEvalZero 2323*150812a8SEvalZero /* =========================================================================================================================== */ 2324*150812a8SEvalZero /* ================ NVMC ================ */ 2325*150812a8SEvalZero /* =========================================================================================================================== */ 2326*150812a8SEvalZero 2327*150812a8SEvalZero 2328*150812a8SEvalZero /** 2329*150812a8SEvalZero * @brief Non Volatile Memory Controller (NVMC) 2330*150812a8SEvalZero */ 2331*150812a8SEvalZero 2332*150812a8SEvalZero typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 2333*150812a8SEvalZero __IM uint32_t RESERVED[256]; 2334*150812a8SEvalZero __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 2335*150812a8SEvalZero __IM uint32_t RESERVED1; 2336*150812a8SEvalZero __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 2337*150812a8SEvalZero __IM uint32_t RESERVED2[62]; 2338*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 2339*150812a8SEvalZero 2340*150812a8SEvalZero union { 2341*150812a8SEvalZero __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ 2342*150812a8SEvalZero __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a 2343*150812a8SEvalZero page in code area. Equivalent to ERASEPAGE. */ 2344*150812a8SEvalZero }; 2345*150812a8SEvalZero __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 2346*150812a8SEvalZero __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a 2347*150812a8SEvalZero page in code area. Equivalent to ERASEPAGE. */ 2348*150812a8SEvalZero __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration 2349*150812a8SEvalZero registers */ 2350*150812a8SEvalZero __IOM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code 2351*150812a8SEvalZero area */ 2352*150812a8SEvalZero __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 2353*150812a8SEvalZero __IM uint32_t RESERVED3[8]; 2354*150812a8SEvalZero __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register. */ 2355*150812a8SEvalZero __IM uint32_t RESERVED4; 2356*150812a8SEvalZero __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter. */ 2357*150812a8SEvalZero __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter. */ 2358*150812a8SEvalZero } NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ 2359*150812a8SEvalZero 2360*150812a8SEvalZero 2361*150812a8SEvalZero 2362*150812a8SEvalZero /* =========================================================================================================================== */ 2363*150812a8SEvalZero /* ================ PPI ================ */ 2364*150812a8SEvalZero /* =========================================================================================================================== */ 2365*150812a8SEvalZero 2366*150812a8SEvalZero 2367*150812a8SEvalZero /** 2368*150812a8SEvalZero * @brief Programmable Peripheral Interconnect (PPI) 2369*150812a8SEvalZero */ 2370*150812a8SEvalZero 2371*150812a8SEvalZero typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 2372*150812a8SEvalZero __IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 2373*150812a8SEvalZero __IM uint32_t RESERVED[308]; 2374*150812a8SEvalZero __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 2375*150812a8SEvalZero __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 2376*150812a8SEvalZero __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 2377*150812a8SEvalZero __IM uint32_t RESERVED1; 2378*150812a8SEvalZero __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ 2379*150812a8SEvalZero __IM uint32_t RESERVED2[148]; 2380*150812a8SEvalZero __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[n]: Channel group n */ 2381*150812a8SEvalZero __IM uint32_t RESERVED3[62]; 2382*150812a8SEvalZero __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ 2383*150812a8SEvalZero } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ 2384*150812a8SEvalZero 2385*150812a8SEvalZero 2386*150812a8SEvalZero 2387*150812a8SEvalZero /* =========================================================================================================================== */ 2388*150812a8SEvalZero /* ================ MWU ================ */ 2389*150812a8SEvalZero /* =========================================================================================================================== */ 2390*150812a8SEvalZero 2391*150812a8SEvalZero 2392*150812a8SEvalZero /** 2393*150812a8SEvalZero * @brief Memory Watch Unit (MWU) 2394*150812a8SEvalZero */ 2395*150812a8SEvalZero 2396*150812a8SEvalZero typedef struct { /*!< (@ 0x40020000) MWU Structure */ 2397*150812a8SEvalZero __IM uint32_t RESERVED[64]; 2398*150812a8SEvalZero __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Unspecified */ 2399*150812a8SEvalZero __IM uint32_t RESERVED1[16]; 2400*150812a8SEvalZero __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Unspecified */ 2401*150812a8SEvalZero __IM uint32_t RESERVED2[100]; 2402*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2403*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2404*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2405*150812a8SEvalZero __IM uint32_t RESERVED3[5]; 2406*150812a8SEvalZero __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable non-maskable interrupt */ 2407*150812a8SEvalZero __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable non-maskable interrupt */ 2408*150812a8SEvalZero __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable non-maskable interrupt */ 2409*150812a8SEvalZero __IM uint32_t RESERVED4[53]; 2410*150812a8SEvalZero __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ 2411*150812a8SEvalZero __IM uint32_t RESERVED5[64]; 2412*150812a8SEvalZero __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */ 2413*150812a8SEvalZero __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */ 2414*150812a8SEvalZero __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */ 2415*150812a8SEvalZero __IM uint32_t RESERVED6[57]; 2416*150812a8SEvalZero __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */ 2417*150812a8SEvalZero __IM uint32_t RESERVED7[32]; 2418*150812a8SEvalZero __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */ 2419*150812a8SEvalZero } NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */ 2420*150812a8SEvalZero 2421*150812a8SEvalZero 2422*150812a8SEvalZero 2423*150812a8SEvalZero /* =========================================================================================================================== */ 2424*150812a8SEvalZero /* ================ I2S ================ */ 2425*150812a8SEvalZero /* =========================================================================================================================== */ 2426*150812a8SEvalZero 2427*150812a8SEvalZero 2428*150812a8SEvalZero /** 2429*150812a8SEvalZero * @brief Inter-IC Sound (I2S) 2430*150812a8SEvalZero */ 2431*150812a8SEvalZero 2432*150812a8SEvalZero typedef struct { /*!< (@ 0x40025000) I2S Structure */ 2433*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK 2434*150812a8SEvalZero generator when this is enabled. */ 2435*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. 2436*150812a8SEvalZero Triggering this task will cause the {event:STOPPED} 2437*150812a8SEvalZero event to be generated. */ 2438*150812a8SEvalZero __IM uint32_t RESERVED[63]; 2439*150812a8SEvalZero __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal 2440*150812a8SEvalZero double-buffers. When the I2S module is started 2441*150812a8SEvalZero and RX is enabled, this event will be generated 2442*150812a8SEvalZero for every RXTXD.MAXCNT words that are received 2443*150812a8SEvalZero on the SDIN pin. */ 2444*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ 2445*150812a8SEvalZero __IM uint32_t RESERVED1[2]; 2446*150812a8SEvalZero __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal 2447*150812a8SEvalZero double-buffers. When the I2S module is started 2448*150812a8SEvalZero and TX is enabled, this event will be generated 2449*150812a8SEvalZero for every RXTXD.MAXCNT words that are sent 2450*150812a8SEvalZero on the SDOUT pin. */ 2451*150812a8SEvalZero __IM uint32_t RESERVED2[122]; 2452*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2453*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2454*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2455*150812a8SEvalZero __IM uint32_t RESERVED3[125]; 2456*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ 2457*150812a8SEvalZero __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ 2458*150812a8SEvalZero __IM uint32_t RESERVED4[3]; 2459*150812a8SEvalZero __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ 2460*150812a8SEvalZero __IM uint32_t RESERVED5; 2461*150812a8SEvalZero __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ 2462*150812a8SEvalZero __IM uint32_t RESERVED6[3]; 2463*150812a8SEvalZero __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ 2464*150812a8SEvalZero __IM uint32_t RESERVED7[3]; 2465*150812a8SEvalZero __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2466*150812a8SEvalZero } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ 2467*150812a8SEvalZero 2468*150812a8SEvalZero 2469*150812a8SEvalZero 2470*150812a8SEvalZero /* =========================================================================================================================== */ 2471*150812a8SEvalZero /* ================ FPU ================ */ 2472*150812a8SEvalZero /* =========================================================================================================================== */ 2473*150812a8SEvalZero 2474*150812a8SEvalZero 2475*150812a8SEvalZero /** 2476*150812a8SEvalZero * @brief FPU (FPU) 2477*150812a8SEvalZero */ 2478*150812a8SEvalZero 2479*150812a8SEvalZero typedef struct { /*!< (@ 0x40026000) FPU Structure */ 2480*150812a8SEvalZero __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 2481*150812a8SEvalZero } NRF_FPU_Type; /*!< Size = 4 (0x4) */ 2482*150812a8SEvalZero 2483*150812a8SEvalZero 2484*150812a8SEvalZero 2485*150812a8SEvalZero /* =========================================================================================================================== */ 2486*150812a8SEvalZero /* ================ USBD ================ */ 2487*150812a8SEvalZero /* =========================================================================================================================== */ 2488*150812a8SEvalZero 2489*150812a8SEvalZero 2490*150812a8SEvalZero /** 2491*150812a8SEvalZero * @brief Universal serial bus device (USBD) 2492*150812a8SEvalZero */ 2493*150812a8SEvalZero 2494*150812a8SEvalZero typedef struct { /*!< (@ 0x40027000) USBD Structure */ 2495*150812a8SEvalZero __IM uint32_t RESERVED; 2496*150812a8SEvalZero __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection[n]: Captures the EPIN[n].PTR 2497*150812a8SEvalZero and EPIN[n].MAXCNT registers values, and 2498*150812a8SEvalZero enables endpoint IN n to respond to traffic 2499*150812a8SEvalZero from host */ 2500*150812a8SEvalZero __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers 2501*150812a8SEvalZero values, and enables sending data on ISO 2502*150812a8SEvalZero endpoint */ 2503*150812a8SEvalZero __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection[n]: Captures the EPOUT[n].PTR 2504*150812a8SEvalZero and EPOUT[n].MAXCNT registers values, and 2505*150812a8SEvalZero enables endpoint n to respond to traffic 2506*150812a8SEvalZero from host */ 2507*150812a8SEvalZero __OM uint32_t TASKS_STARTISOOUT; /*!< (@ 0x00000048) Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers 2508*150812a8SEvalZero values, and enables receiving of data on 2509*150812a8SEvalZero ISO endpoint */ 2510*150812a8SEvalZero __OM uint32_t TASKS_EP0RCVOUT; /*!< (@ 0x0000004C) Allows OUT data stage on control endpoint 0 */ 2511*150812a8SEvalZero __OM uint32_t TASKS_EP0STATUS; /*!< (@ 0x00000050) Allows status stage on control endpoint 0 */ 2512*150812a8SEvalZero __OM uint32_t TASKS_EP0STALL; /*!< (@ 0x00000054) Stalls data and status stage on control endpoint 2513*150812a8SEvalZero 0 */ 2514*150812a8SEvalZero __OM uint32_t TASKS_DPDMDRIVE; /*!< (@ 0x00000058) Forces D+ and D- lines into the state defined 2515*150812a8SEvalZero in the DPDMVALUE register */ 2516*150812a8SEvalZero __OM uint32_t TASKS_DPDMNODRIVE; /*!< (@ 0x0000005C) Stops forcing D+ and D- lines into any state 2517*150812a8SEvalZero (USB engine takes control) */ 2518*150812a8SEvalZero __IM uint32_t RESERVED1[40]; 2519*150812a8SEvalZero __IOM uint32_t EVENTS_USBRESET; /*!< (@ 0x00000100) Signals that a USB reset condition has been detected 2520*150812a8SEvalZero on USB lines */ 2521*150812a8SEvalZero __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000104) Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, 2522*150812a8SEvalZero or EPOUT[n].PTR and EPOUT[n].MAXCNT registers 2523*150812a8SEvalZero have been captured on all endpoints reported 2524*150812a8SEvalZero in the EPSTATUS register */ 2525*150812a8SEvalZero __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection[n]: The whole EPIN[n] 2526*150812a8SEvalZero buffer has been consumed. The RAM buffer 2527*150812a8SEvalZero can be accessed safely by software. */ 2528*150812a8SEvalZero __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place 2529*150812a8SEvalZero on the control endpoint */ 2530*150812a8SEvalZero __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The 2531*150812a8SEvalZero RAM buffer can be accessed safely by software. */ 2532*150812a8SEvalZero __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection[n]: The whole EPOUT[n] 2533*150812a8SEvalZero buffer has been consumed. The RAM buffer 2534*150812a8SEvalZero can be accessed safely by software. */ 2535*150812a8SEvalZero __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The 2536*150812a8SEvalZero RAM buffer can be accessed safely by software. */ 2537*150812a8SEvalZero __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition 2538*150812a8SEvalZero has been detected on USB lines */ 2539*150812a8SEvalZero __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific 2540*150812a8SEvalZero events has occurred. Check EVENTCAUSE register 2541*150812a8SEvalZero to find the cause. */ 2542*150812a8SEvalZero __IOM uint32_t EVENTS_EP0SETUP; /*!< (@ 0x0000015C) A valid SETUP token has been received (and acknowledged) 2543*150812a8SEvalZero on the control endpoint */ 2544*150812a8SEvalZero __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint, 2545*150812a8SEvalZero indicated by the EPDATASTATUS register */ 2546*150812a8SEvalZero __IM uint32_t RESERVED2[39]; 2547*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 2548*150812a8SEvalZero __IM uint32_t RESERVED3[63]; 2549*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2550*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2551*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2552*150812a8SEvalZero __IM uint32_t RESERVED4[61]; 2553*150812a8SEvalZero __IOM uint32_t EVENTCAUSE; /*!< (@ 0x00000400) Details on what caused the USBEVENT event */ 2554*150812a8SEvalZero __IM uint32_t RESERVED5[7]; 2555*150812a8SEvalZero __IOM USBD_HALTED_Type HALTED; /*!< (@ 0x00000420) Unspecified */ 2556*150812a8SEvalZero __IM uint32_t RESERVED6; 2557*150812a8SEvalZero __IOM uint32_t EPSTATUS; /*!< (@ 0x00000468) Provides information on which endpoint's EasyDMA 2558*150812a8SEvalZero registers have been captured */ 2559*150812a8SEvalZero __IOM uint32_t EPDATASTATUS; /*!< (@ 0x0000046C) Provides information on which endpoint(s) an 2560*150812a8SEvalZero acknowledged data transfer has occurred 2561*150812a8SEvalZero (EPDATA event) */ 2562*150812a8SEvalZero __IM uint32_t USBADDR; /*!< (@ 0x00000470) Device USB address */ 2563*150812a8SEvalZero __IM uint32_t RESERVED7[3]; 2564*150812a8SEvalZero __IM uint32_t BMREQUESTTYPE; /*!< (@ 0x00000480) SETUP data, byte 0, bmRequestType */ 2565*150812a8SEvalZero __IM uint32_t BREQUEST; /*!< (@ 0x00000484) SETUP data, byte 1, bRequest */ 2566*150812a8SEvalZero __IM uint32_t WVALUEL; /*!< (@ 0x00000488) SETUP data, byte 2, LSB of wValue */ 2567*150812a8SEvalZero __IM uint32_t WVALUEH; /*!< (@ 0x0000048C) SETUP data, byte 3, MSB of wValue */ 2568*150812a8SEvalZero __IM uint32_t WINDEXL; /*!< (@ 0x00000490) SETUP data, byte 4, LSB of wIndex */ 2569*150812a8SEvalZero __IM uint32_t WINDEXH; /*!< (@ 0x00000494) SETUP data, byte 5, MSB of wIndex */ 2570*150812a8SEvalZero __IM uint32_t WLENGTHL; /*!< (@ 0x00000498) SETUP data, byte 6, LSB of wLength */ 2571*150812a8SEvalZero __IM uint32_t WLENGTHH; /*!< (@ 0x0000049C) SETUP data, byte 7, MSB of wLength */ 2572*150812a8SEvalZero __IOM USBD_SIZE_Type SIZE; /*!< (@ 0x000004A0) Unspecified */ 2573*150812a8SEvalZero __IM uint32_t RESERVED8[15]; 2574*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable USB */ 2575*150812a8SEvalZero __IOM uint32_t USBPULLUP; /*!< (@ 0x00000504) Control of the USB pull-up */ 2576*150812a8SEvalZero __IOM uint32_t DPDMVALUE; /*!< (@ 0x00000508) State D+ and D- lines will be forced into by 2577*150812a8SEvalZero the DPDMDRIVE task. The DPDMNODRIVE task 2578*150812a8SEvalZero reverts the control of the lines to MAC 2579*150812a8SEvalZero IP (no forcing). */ 2580*150812a8SEvalZero __IOM uint32_t DTOGGLE; /*!< (@ 0x0000050C) Data toggle control and status */ 2581*150812a8SEvalZero __IOM uint32_t EPINEN; /*!< (@ 0x00000510) Endpoint IN enable */ 2582*150812a8SEvalZero __IOM uint32_t EPOUTEN; /*!< (@ 0x00000514) Endpoint OUT enable */ 2583*150812a8SEvalZero __OM uint32_t EPSTALL; /*!< (@ 0x00000518) STALL endpoints */ 2584*150812a8SEvalZero __IOM uint32_t ISOSPLIT; /*!< (@ 0x0000051C) Controls the split of ISO buffers */ 2585*150812a8SEvalZero __IM uint32_t FRAMECNTR; /*!< (@ 0x00000520) Returns the current value of the start of frame 2586*150812a8SEvalZero counter */ 2587*150812a8SEvalZero __IM uint32_t RESERVED9[2]; 2588*150812a8SEvalZero __IOM uint32_t LOWPOWER; /*!< (@ 0x0000052C) Controls USBD peripheral low power mode during 2589*150812a8SEvalZero USB suspend */ 2590*150812a8SEvalZero __IOM uint32_t ISOINCONFIG; /*!< (@ 0x00000530) Controls the response of the ISO IN endpoint 2591*150812a8SEvalZero to an IN token when no data is ready to 2592*150812a8SEvalZero be sent */ 2593*150812a8SEvalZero __IM uint32_t RESERVED10[51]; 2594*150812a8SEvalZero __IOM USBD_EPIN_Type EPIN[8]; /*!< (@ 0x00000600) Unspecified */ 2595*150812a8SEvalZero __IOM USBD_ISOIN_Type ISOIN; /*!< (@ 0x000006A0) Unspecified */ 2596*150812a8SEvalZero __IM uint32_t RESERVED11[21]; 2597*150812a8SEvalZero __IOM USBD_EPOUT_Type EPOUT[8]; /*!< (@ 0x00000700) Unspecified */ 2598*150812a8SEvalZero __IOM USBD_ISOOUT_Type ISOOUT; /*!< (@ 0x000007A0) Unspecified */ 2599*150812a8SEvalZero } NRF_USBD_Type; /*!< Size = 1964 (0x7ac) */ 2600*150812a8SEvalZero 2601*150812a8SEvalZero 2602*150812a8SEvalZero 2603*150812a8SEvalZero /* =========================================================================================================================== */ 2604*150812a8SEvalZero /* ================ QSPI ================ */ 2605*150812a8SEvalZero /* =========================================================================================================================== */ 2606*150812a8SEvalZero 2607*150812a8SEvalZero 2608*150812a8SEvalZero /** 2609*150812a8SEvalZero * @brief External flash interface (QSPI) 2610*150812a8SEvalZero */ 2611*150812a8SEvalZero 2612*150812a8SEvalZero typedef struct { /*!< (@ 0x40029000) QSPI Structure */ 2613*150812a8SEvalZero __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate QSPI interface */ 2614*150812a8SEvalZero __OM uint32_t TASKS_READSTART; /*!< (@ 0x00000004) Start transfer from external flash memory to 2615*150812a8SEvalZero internal RAM */ 2616*150812a8SEvalZero __OM uint32_t TASKS_WRITESTART; /*!< (@ 0x00000008) Start transfer from internal RAM to external 2617*150812a8SEvalZero flash memory */ 2618*150812a8SEvalZero __OM uint32_t TASKS_ERASESTART; /*!< (@ 0x0000000C) Start external flash memory erase operation */ 2619*150812a8SEvalZero __OM uint32_t TASKS_DEACTIVATE; /*!< (@ 0x00000010) Deactivate QSPI interface */ 2620*150812a8SEvalZero __IM uint32_t RESERVED[59]; 2621*150812a8SEvalZero __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) QSPI peripheral is ready. This event will be 2622*150812a8SEvalZero generated as a response to any QSPI task. */ 2623*150812a8SEvalZero __IM uint32_t RESERVED1[127]; 2624*150812a8SEvalZero __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2625*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2626*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2627*150812a8SEvalZero __IM uint32_t RESERVED2[125]; 2628*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable QSPI peripheral and acquire the pins selected 2629*150812a8SEvalZero in PSELn registers */ 2630*150812a8SEvalZero __IOM QSPI_READ_Type READ; /*!< (@ 0x00000504) Unspecified */ 2631*150812a8SEvalZero __IOM QSPI_WRITE_Type WRITE; /*!< (@ 0x00000510) Unspecified */ 2632*150812a8SEvalZero __IOM QSPI_ERASE_Type ERASE; /*!< (@ 0x0000051C) Unspecified */ 2633*150812a8SEvalZero __IOM QSPI_PSEL_Type PSEL; /*!< (@ 0x00000524) Unspecified */ 2634*150812a8SEvalZero __IOM uint32_t XIPOFFSET; /*!< (@ 0x00000540) Address offset into the external memory for Execute 2635*150812a8SEvalZero in Place operation. */ 2636*150812a8SEvalZero __IOM uint32_t IFCONFIG0; /*!< (@ 0x00000544) Interface configuration. */ 2637*150812a8SEvalZero __IM uint32_t RESERVED3[46]; 2638*150812a8SEvalZero __IOM uint32_t IFCONFIG1; /*!< (@ 0x00000600) Interface configuration. */ 2639*150812a8SEvalZero __IM uint32_t STATUS; /*!< (@ 0x00000604) Status register. */ 2640*150812a8SEvalZero __IM uint32_t RESERVED4[3]; 2641*150812a8SEvalZero __IOM uint32_t DPMDUR; /*!< (@ 0x00000614) Set the duration required to enter/exit deep 2642*150812a8SEvalZero power-down mode (DPM). */ 2643*150812a8SEvalZero __IM uint32_t RESERVED5[3]; 2644*150812a8SEvalZero __IOM uint32_t ADDRCONF; /*!< (@ 0x00000624) Extended address configuration. */ 2645*150812a8SEvalZero __IM uint32_t RESERVED6[3]; 2646*150812a8SEvalZero __IOM uint32_t CINSTRCONF; /*!< (@ 0x00000634) Custom instruction configuration register. */ 2647*150812a8SEvalZero __IOM uint32_t CINSTRDAT0; /*!< (@ 0x00000638) Custom instruction data register 0. */ 2648*150812a8SEvalZero __IOM uint32_t CINSTRDAT1; /*!< (@ 0x0000063C) Custom instruction data register 1. */ 2649*150812a8SEvalZero __IOM uint32_t IFTIMING; /*!< (@ 0x00000640) SPI interface timing. */ 2650*150812a8SEvalZero } NRF_QSPI_Type; /*!< Size = 1604 (0x644) */ 2651*150812a8SEvalZero 2652*150812a8SEvalZero 2653*150812a8SEvalZero 2654*150812a8SEvalZero /* =========================================================================================================================== */ 2655*150812a8SEvalZero /* ================ P0 ================ */ 2656*150812a8SEvalZero /* =========================================================================================================================== */ 2657*150812a8SEvalZero 2658*150812a8SEvalZero 2659*150812a8SEvalZero /** 2660*150812a8SEvalZero * @brief GPIO Port 1 (P0) 2661*150812a8SEvalZero */ 2662*150812a8SEvalZero 2663*150812a8SEvalZero typedef struct { /*!< (@ 0x50000000) P0 Structure */ 2664*150812a8SEvalZero __IM uint32_t RESERVED[321]; 2665*150812a8SEvalZero __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ 2666*150812a8SEvalZero __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ 2667*150812a8SEvalZero __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ 2668*150812a8SEvalZero __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ 2669*150812a8SEvalZero __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ 2670*150812a8SEvalZero __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ 2671*150812a8SEvalZero __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ 2672*150812a8SEvalZero __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that 2673*150812a8SEvalZero have met the criteria set in the PIN_CNF[n].SENSE 2674*150812a8SEvalZero registers */ 2675*150812a8SEvalZero __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour 2676*150812a8SEvalZero and LDETECT mode */ 2677*150812a8SEvalZero __IM uint32_t RESERVED1[118]; 2678*150812a8SEvalZero __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[n]: Configuration of GPIO 2679*150812a8SEvalZero pins */ 2680*150812a8SEvalZero } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 2681*150812a8SEvalZero 2682*150812a8SEvalZero 2683*150812a8SEvalZero 2684*150812a8SEvalZero /* =========================================================================================================================== */ 2685*150812a8SEvalZero /* ================ CC_HOST_RGF ================ */ 2686*150812a8SEvalZero /* =========================================================================================================================== */ 2687*150812a8SEvalZero 2688*150812a8SEvalZero 2689*150812a8SEvalZero /** 2690*150812a8SEvalZero * @brief CRYPTOCELL HOST_RGF interface (CC_HOST_RGF) 2691*150812a8SEvalZero */ 2692*150812a8SEvalZero 2693*150812a8SEvalZero typedef struct { /*!< (@ 0x5002A000) CC_HOST_RGF Structure */ 2694*150812a8SEvalZero __IM uint32_t RESERVED[1678]; 2695*150812a8SEvalZero __IOM uint32_t HOST_CRYPTOKEY_SEL; /*!< (@ 0x00001A38) AES hardware key select */ 2696*150812a8SEvalZero __IM uint32_t RESERVED1[4]; 2697*150812a8SEvalZero __IOM uint32_t HOST_IOT_KPRTL_LOCK; /*!< (@ 0x00001A4C) This write-once register is the K_PRTL lock register. 2698*150812a8SEvalZero When this register is set, K_PRTL can not 2699*150812a8SEvalZero be used and a zeroed key will be used instead. 2700*150812a8SEvalZero The value of this register is saved in the 2701*150812a8SEvalZero CRYPTOCELL AO power domain. */ 2702*150812a8SEvalZero __IOM uint32_t HOST_IOT_KDR0; /*!< (@ 0x00001A50) This register holds bits 31:0 of K_DR. The value 2703*150812a8SEvalZero of this register is saved in the CRYPTOCELL 2704*150812a8SEvalZero AO power domain. Reading from this address 2705*150812a8SEvalZero returns the K_DR valid status indicating 2706*150812a8SEvalZero if K_DR is successfully retained. */ 2707*150812a8SEvalZero __OM uint32_t HOST_IOT_KDR1; /*!< (@ 0x00001A54) This register holds bits 63:32 of K_DR. The value 2708*150812a8SEvalZero of this register is saved in the CRYPTOCELL 2709*150812a8SEvalZero AO power domain. */ 2710*150812a8SEvalZero __OM uint32_t HOST_IOT_KDR2; /*!< (@ 0x00001A58) This register holds bits 95:64 of K_DR. The value 2711*150812a8SEvalZero of this register is saved in the CRYPTOCELL 2712*150812a8SEvalZero AO power domain. */ 2713*150812a8SEvalZero __OM uint32_t HOST_IOT_KDR3; /*!< (@ 0x00001A5C) This register holds bits 127:96 of K_DR. The 2714*150812a8SEvalZero value of this register is saved in the CRYPTOCELL 2715*150812a8SEvalZero AO power domain. */ 2716*150812a8SEvalZero __IOM uint32_t HOST_IOT_LCS; /*!< (@ 0x00001A60) Controls lifecycle state (LCS) for CRYPTOCELL 2717*150812a8SEvalZero subsystem */ 2718*150812a8SEvalZero } NRF_CC_HOST_RGF_Type; /*!< Size = 6756 (0x1a64) */ 2719*150812a8SEvalZero 2720*150812a8SEvalZero 2721*150812a8SEvalZero 2722*150812a8SEvalZero /* =========================================================================================================================== */ 2723*150812a8SEvalZero /* ================ CRYPTOCELL ================ */ 2724*150812a8SEvalZero /* =========================================================================================================================== */ 2725*150812a8SEvalZero 2726*150812a8SEvalZero 2727*150812a8SEvalZero /** 2728*150812a8SEvalZero * @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL) 2729*150812a8SEvalZero */ 2730*150812a8SEvalZero 2731*150812a8SEvalZero typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL Structure */ 2732*150812a8SEvalZero __IM uint32_t RESERVED[320]; 2733*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem */ 2734*150812a8SEvalZero } NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ 2735*150812a8SEvalZero 2736*150812a8SEvalZero 2737*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_peripherals */ 2738*150812a8SEvalZero 2739*150812a8SEvalZero 2740*150812a8SEvalZero /* =========================================================================================================================== */ 2741*150812a8SEvalZero /* ================ Device Specific Peripheral Address Map ================ */ 2742*150812a8SEvalZero /* =========================================================================================================================== */ 2743*150812a8SEvalZero 2744*150812a8SEvalZero 2745*150812a8SEvalZero /** @addtogroup Device_Peripheral_peripheralAddr 2746*150812a8SEvalZero * @{ 2747*150812a8SEvalZero */ 2748*150812a8SEvalZero 2749*150812a8SEvalZero #define NRF_FICR_BASE 0x10000000UL 2750*150812a8SEvalZero #define NRF_UICR_BASE 0x10001000UL 2751*150812a8SEvalZero #define NRF_CLOCK_BASE 0x40000000UL 2752*150812a8SEvalZero #define NRF_POWER_BASE 0x40000000UL 2753*150812a8SEvalZero #define NRF_RADIO_BASE 0x40001000UL 2754*150812a8SEvalZero #define NRF_UART0_BASE 0x40002000UL 2755*150812a8SEvalZero #define NRF_UARTE0_BASE 0x40002000UL 2756*150812a8SEvalZero #define NRF_SPI0_BASE 0x40003000UL 2757*150812a8SEvalZero #define NRF_SPIM0_BASE 0x40003000UL 2758*150812a8SEvalZero #define NRF_SPIS0_BASE 0x40003000UL 2759*150812a8SEvalZero #define NRF_TWI0_BASE 0x40003000UL 2760*150812a8SEvalZero #define NRF_TWIM0_BASE 0x40003000UL 2761*150812a8SEvalZero #define NRF_TWIS0_BASE 0x40003000UL 2762*150812a8SEvalZero #define NRF_SPI1_BASE 0x40004000UL 2763*150812a8SEvalZero #define NRF_SPIM1_BASE 0x40004000UL 2764*150812a8SEvalZero #define NRF_SPIS1_BASE 0x40004000UL 2765*150812a8SEvalZero #define NRF_TWI1_BASE 0x40004000UL 2766*150812a8SEvalZero #define NRF_TWIM1_BASE 0x40004000UL 2767*150812a8SEvalZero #define NRF_TWIS1_BASE 0x40004000UL 2768*150812a8SEvalZero #define NRF_NFCT_BASE 0x40005000UL 2769*150812a8SEvalZero #define NRF_GPIOTE_BASE 0x40006000UL 2770*150812a8SEvalZero #define NRF_SAADC_BASE 0x40007000UL 2771*150812a8SEvalZero #define NRF_TIMER0_BASE 0x40008000UL 2772*150812a8SEvalZero #define NRF_TIMER1_BASE 0x40009000UL 2773*150812a8SEvalZero #define NRF_TIMER2_BASE 0x4000A000UL 2774*150812a8SEvalZero #define NRF_RTC0_BASE 0x4000B000UL 2775*150812a8SEvalZero #define NRF_TEMP_BASE 0x4000C000UL 2776*150812a8SEvalZero #define NRF_RNG_BASE 0x4000D000UL 2777*150812a8SEvalZero #define NRF_ECB_BASE 0x4000E000UL 2778*150812a8SEvalZero #define NRF_AAR_BASE 0x4000F000UL 2779*150812a8SEvalZero #define NRF_CCM_BASE 0x4000F000UL 2780*150812a8SEvalZero #define NRF_WDT_BASE 0x40010000UL 2781*150812a8SEvalZero #define NRF_RTC1_BASE 0x40011000UL 2782*150812a8SEvalZero #define NRF_QDEC_BASE 0x40012000UL 2783*150812a8SEvalZero #define NRF_COMP_BASE 0x40013000UL 2784*150812a8SEvalZero #define NRF_LPCOMP_BASE 0x40013000UL 2785*150812a8SEvalZero #define NRF_EGU0_BASE 0x40014000UL 2786*150812a8SEvalZero #define NRF_SWI0_BASE 0x40014000UL 2787*150812a8SEvalZero #define NRF_EGU1_BASE 0x40015000UL 2788*150812a8SEvalZero #define NRF_SWI1_BASE 0x40015000UL 2789*150812a8SEvalZero #define NRF_EGU2_BASE 0x40016000UL 2790*150812a8SEvalZero #define NRF_SWI2_BASE 0x40016000UL 2791*150812a8SEvalZero #define NRF_EGU3_BASE 0x40017000UL 2792*150812a8SEvalZero #define NRF_SWI3_BASE 0x40017000UL 2793*150812a8SEvalZero #define NRF_EGU4_BASE 0x40018000UL 2794*150812a8SEvalZero #define NRF_SWI4_BASE 0x40018000UL 2795*150812a8SEvalZero #define NRF_EGU5_BASE 0x40019000UL 2796*150812a8SEvalZero #define NRF_SWI5_BASE 0x40019000UL 2797*150812a8SEvalZero #define NRF_TIMER3_BASE 0x4001A000UL 2798*150812a8SEvalZero #define NRF_TIMER4_BASE 0x4001B000UL 2799*150812a8SEvalZero #define NRF_PWM0_BASE 0x4001C000UL 2800*150812a8SEvalZero #define NRF_PDM_BASE 0x4001D000UL 2801*150812a8SEvalZero #define NRF_ACL_BASE 0x4001E000UL 2802*150812a8SEvalZero #define NRF_NVMC_BASE 0x4001E000UL 2803*150812a8SEvalZero #define NRF_PPI_BASE 0x4001F000UL 2804*150812a8SEvalZero #define NRF_MWU_BASE 0x40020000UL 2805*150812a8SEvalZero #define NRF_PWM1_BASE 0x40021000UL 2806*150812a8SEvalZero #define NRF_PWM2_BASE 0x40022000UL 2807*150812a8SEvalZero #define NRF_SPI2_BASE 0x40023000UL 2808*150812a8SEvalZero #define NRF_SPIM2_BASE 0x40023000UL 2809*150812a8SEvalZero #define NRF_SPIS2_BASE 0x40023000UL 2810*150812a8SEvalZero #define NRF_RTC2_BASE 0x40024000UL 2811*150812a8SEvalZero #define NRF_I2S_BASE 0x40025000UL 2812*150812a8SEvalZero #define NRF_FPU_BASE 0x40026000UL 2813*150812a8SEvalZero #define NRF_USBD_BASE 0x40027000UL 2814*150812a8SEvalZero #define NRF_UARTE1_BASE 0x40028000UL 2815*150812a8SEvalZero #define NRF_QSPI_BASE 0x40029000UL 2816*150812a8SEvalZero #define NRF_PWM3_BASE 0x4002D000UL 2817*150812a8SEvalZero #define NRF_SPIM3_BASE 0x4002F000UL 2818*150812a8SEvalZero #define NRF_P0_BASE 0x50000000UL 2819*150812a8SEvalZero #define NRF_P1_BASE 0x50000300UL 2820*150812a8SEvalZero #define NRF_CC_HOST_RGF_BASE 0x5002A000UL 2821*150812a8SEvalZero #define NRF_CRYPTOCELL_BASE 0x5002A000UL 2822*150812a8SEvalZero 2823*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 2824*150812a8SEvalZero 2825*150812a8SEvalZero 2826*150812a8SEvalZero /* =========================================================================================================================== */ 2827*150812a8SEvalZero /* ================ Peripheral declaration ================ */ 2828*150812a8SEvalZero /* =========================================================================================================================== */ 2829*150812a8SEvalZero 2830*150812a8SEvalZero 2831*150812a8SEvalZero /** @addtogroup Device_Peripheral_declaration 2832*150812a8SEvalZero * @{ 2833*150812a8SEvalZero */ 2834*150812a8SEvalZero 2835*150812a8SEvalZero #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 2836*150812a8SEvalZero #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 2837*150812a8SEvalZero #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 2838*150812a8SEvalZero #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 2839*150812a8SEvalZero #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 2840*150812a8SEvalZero #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) 2841*150812a8SEvalZero #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) 2842*150812a8SEvalZero #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) 2843*150812a8SEvalZero #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) 2844*150812a8SEvalZero #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) 2845*150812a8SEvalZero #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) 2846*150812a8SEvalZero #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) 2847*150812a8SEvalZero #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) 2848*150812a8SEvalZero #define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) 2849*150812a8SEvalZero #define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) 2850*150812a8SEvalZero #define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) 2851*150812a8SEvalZero #define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) 2852*150812a8SEvalZero #define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) 2853*150812a8SEvalZero #define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) 2854*150812a8SEvalZero #define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) 2855*150812a8SEvalZero #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 2856*150812a8SEvalZero #define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) 2857*150812a8SEvalZero #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 2858*150812a8SEvalZero #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 2859*150812a8SEvalZero #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 2860*150812a8SEvalZero #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 2861*150812a8SEvalZero #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 2862*150812a8SEvalZero #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 2863*150812a8SEvalZero #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 2864*150812a8SEvalZero #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 2865*150812a8SEvalZero #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 2866*150812a8SEvalZero #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 2867*150812a8SEvalZero #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 2868*150812a8SEvalZero #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 2869*150812a8SEvalZero #define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) 2870*150812a8SEvalZero #define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) 2871*150812a8SEvalZero #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) 2872*150812a8SEvalZero #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) 2873*150812a8SEvalZero #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) 2874*150812a8SEvalZero #define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) 2875*150812a8SEvalZero #define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) 2876*150812a8SEvalZero #define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) 2877*150812a8SEvalZero #define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) 2878*150812a8SEvalZero #define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) 2879*150812a8SEvalZero #define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) 2880*150812a8SEvalZero #define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) 2881*150812a8SEvalZero #define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) 2882*150812a8SEvalZero #define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) 2883*150812a8SEvalZero #define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) 2884*150812a8SEvalZero #define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) 2885*150812a8SEvalZero #define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) 2886*150812a8SEvalZero #define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) 2887*150812a8SEvalZero #define NRF_ACL ((NRF_ACL_Type*) NRF_ACL_BASE) 2888*150812a8SEvalZero #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 2889*150812a8SEvalZero #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 2890*150812a8SEvalZero #define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) 2891*150812a8SEvalZero #define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) 2892*150812a8SEvalZero #define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) 2893*150812a8SEvalZero #define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) 2894*150812a8SEvalZero #define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) 2895*150812a8SEvalZero #define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) 2896*150812a8SEvalZero #define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) 2897*150812a8SEvalZero #define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) 2898*150812a8SEvalZero #define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) 2899*150812a8SEvalZero #define NRF_USBD ((NRF_USBD_Type*) NRF_USBD_BASE) 2900*150812a8SEvalZero #define NRF_UARTE1 ((NRF_UARTE_Type*) NRF_UARTE1_BASE) 2901*150812a8SEvalZero #define NRF_QSPI ((NRF_QSPI_Type*) NRF_QSPI_BASE) 2902*150812a8SEvalZero #define NRF_PWM3 ((NRF_PWM_Type*) NRF_PWM3_BASE) 2903*150812a8SEvalZero #define NRF_SPIM3 ((NRF_SPIM_Type*) NRF_SPIM3_BASE) 2904*150812a8SEvalZero #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) 2905*150812a8SEvalZero #define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE) 2906*150812a8SEvalZero #define NRF_CC_HOST_RGF ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_BASE) 2907*150812a8SEvalZero #define NRF_CRYPTOCELL ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_BASE) 2908*150812a8SEvalZero 2909*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_declaration */ 2910*150812a8SEvalZero 2911*150812a8SEvalZero 2912*150812a8SEvalZero /* ========================================= End of section using anonymous unions ========================================= */ 2913*150812a8SEvalZero #if defined (__CC_ARM) 2914*150812a8SEvalZero #pragma pop 2915*150812a8SEvalZero #elif defined (__ICCARM__) 2916*150812a8SEvalZero /* leave anonymous unions enabled */ 2917*150812a8SEvalZero #elif (__ARMCC_VERSION >= 6010050) 2918*150812a8SEvalZero #pragma clang diagnostic pop 2919*150812a8SEvalZero #elif defined (__GNUC__) 2920*150812a8SEvalZero /* anonymous unions are enabled by default */ 2921*150812a8SEvalZero #elif defined (__TMS470__) 2922*150812a8SEvalZero /* anonymous unions are enabled by default */ 2923*150812a8SEvalZero #elif defined (__TASKING__) 2924*150812a8SEvalZero #pragma warning restore 2925*150812a8SEvalZero #elif defined (__CSMC__) 2926*150812a8SEvalZero /* anonymous unions are enabled by default */ 2927*150812a8SEvalZero #endif 2928*150812a8SEvalZero 2929*150812a8SEvalZero 2930*150812a8SEvalZero #ifdef __cplusplus 2931*150812a8SEvalZero } 2932*150812a8SEvalZero #endif 2933*150812a8SEvalZero 2934*150812a8SEvalZero #endif /* NRF52840_H */ 2935*150812a8SEvalZero 2936*150812a8SEvalZero 2937*150812a8SEvalZero /** @} */ /* End of group nrf52840 */ 2938*150812a8SEvalZero 2939*150812a8SEvalZero /** @} */ /* End of group Nordic Semiconductor */ 2940