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/linux-6.14.4/drivers/gpio/
Dgpio-omap.c78 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) argument
109 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument
112 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
118 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_reg() argument
121 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
125 reg += bank->regs->set_dataout; in omap_set_gpio_dataout_reg()
126 bank->context.dataout |= l; in omap_set_gpio_dataout_reg()
128 reg += bank->regs->clr_dataout; in omap_set_gpio_dataout_reg()
129 bank->context.dataout &= ~l; in omap_set_gpio_dataout_reg()
[all …]
Dgpio-rockchip.c83 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, in rockchip_gpio_writel() argument
86 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
88 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_writel()
94 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, in rockchip_gpio_readl() argument
97 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl()
100 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_readl()
108 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_writel_bit() argument
112 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel_bit()
115 if (bank->gpio_type == GPIO_TYPE_V2) { in rockchip_gpio_writel_bit()
130 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_readl_bit() argument
[all …]
Dgpio-brcmstb.c26 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) argument
27 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) argument
28 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) argument
29 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) argument
30 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) argument
31 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) argument
32 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) argument
33 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) argument
34 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) argument
65 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_gc_to_priv() local
[all …]
/linux-6.14.4/drivers/crypto/intel/qat/qat_common/
Dadf_gen4_hw_csr_data.c11 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
16 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
22 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
27 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
33 static u32 read_csr_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_stat() argument
35 return READ_CSR_STAT(csr_base_addr, bank); in read_csr_stat()
[all …]
Dadf_gen4_hw_csr_data.h37 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
39 ADF_RING_BUNDLE_SIZE * (bank) + \
41 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
43 ADF_RING_BUNDLE_SIZE * (bank) + \
45 #define READ_CSR_STAT(csr_base_addr, bank) \ argument
47 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_STAT)
48 #define READ_CSR_UO_STAT(csr_base_addr, bank) \ argument
50 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_UO_STAT)
51 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
53 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT)
[all …]
Dadf_transport.c40 static int adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_reserve_ring() argument
42 spin_lock(&bank->lock); in adf_reserve_ring()
43 if (bank->ring_mask & (1 << ring)) { in adf_reserve_ring()
44 spin_unlock(&bank->lock); in adf_reserve_ring()
47 bank->ring_mask |= (1 << ring); in adf_reserve_ring()
48 spin_unlock(&bank->lock); in adf_reserve_ring()
52 static void adf_unreserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_unreserve_ring() argument
54 spin_lock(&bank->lock); in adf_unreserve_ring()
55 bank->ring_mask &= ~(1 << ring); in adf_unreserve_ring()
56 spin_unlock(&bank->lock); in adf_unreserve_ring()
[all …]
Dadf_gen2_hw_csr_data.c11 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
16 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
22 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
27 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
33 static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_e_stat() argument
35 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
[all …]
Dadf_gen2_hw_csr_data.h30 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
31 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
33 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
34 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
36 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
37 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
39 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
40 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
42 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
47 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
[all …]
Dadf_transport_debug.c44 struct adf_etr_bank_data *bank = ring->bank; in adf_ring_show() local
45 struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev); in adf_ring_show()
46 void __iomem *csr = ring->bank->csr_addr; in adf_ring_show()
51 head = csr_ops->read_csr_ring_head(csr, bank->bank_number, in adf_ring_show()
53 tail = csr_ops->read_csr_ring_tail(csr, bank->bank_number, in adf_ring_show()
55 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number); in adf_ring_show()
60 seq_printf(sfile, "ring num %d, bank num %d\n", in adf_ring_show()
61 ring->ring_number, ring->bank->bank_number); in adf_ring_show()
104 ring->bank->bank_debug_dir, in adf_ring_debugfs_add()
121 struct adf_etr_bank_data *bank = sfile->private; in adf_bank_start() local
[all …]
Dadf_gen4_hw_data.c235 "ring pair reset for bank:%d\n", bank_number); in adf_gen4_ring_pair_reset()
396 * adf_gen4_bank_quiesce_coal_timer() - quiesce bank coalesced interrupt timer
398 * @bank_idx: Offset to the bank within this device
401 * This function tries to quiesce the coalesced interrupt timer of a bank if
438 "wait for bank %d - coalesced timer expires in %llu us (max=%u ms estat=0x%x intcolen=0x%x)\n", in adf_gen4_bank_quiesce_coal_timer()
446 "coalesced timer for bank %d expired (%llu us)\n", in adf_gen4_bank_quiesce_coal_timer()
481 dev_dbg(&GET_DEV(accel_dev), "Drain bank %d\n", bank_number); in adf_gen4_bank_drain_start()
485 dev_err(&GET_DEV(accel_dev), "Bank drain failed (timeout)\n"); in adf_gen4_bank_drain_start()
487 dev_dbg(&GET_DEV(accel_dev), "Bank drain successful\n"); in adf_gen4_bank_drain_start()
493 u32 bank, struct bank_state *state, u32 num_rings) in bank_state_save() argument
[all …]
/linux-6.14.4/drivers/pinctrl/samsung/
Dpinctrl-exynos.c56 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
61 if (bank->eint_mask_offset) in exynos_irq_mask()
62 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_mask()
64 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
66 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_mask()
67 dev_err(bank->gpio_chip.parent, in exynos_irq_mask()
72 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
74 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
76 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask()
78 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_mask()
[all …]
Dpinctrl-samsung.c351 * given a pin number that is local to a pin controller, find out the pin bank
352 * and the register base of the pin bank.
356 struct samsung_pin_bank **bank) in pin_to_reg_bank() argument
368 if (bank) in pin_to_reg_bank()
369 *bank = b; in pin_to_reg_bank()
378 struct samsung_pin_bank *bank; in samsung_pinmux_setup() local
390 pin_to_reg_bank(drvdata, grp->pins[0], &reg, &pin_offset, &bank); in samsung_pinmux_setup()
391 type = bank->type; in samsung_pinmux_setup()
406 raw_spin_lock_irqsave(&bank->slock, flags); in samsung_pinmux_setup()
413 raw_spin_unlock_irqrestore(&bank->slock, flags); in samsung_pinmux_setup()
[all …]
/linux-6.14.4/tools/testing/selftests/gpio/
Dgpio-sim.sh25 BANK=`basename $FILE`
26 if [ "$BANK" = "live" -o "$BANK" = "dev_name" ]; then
30 LINES=`ls $CONFIGFS_DIR/$CHIP/$BANK/ | grep -E ^line`
33 if [ -e $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog ]; then
34 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog || \
38 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE || \
43 rmdir $CONFIGFS_DIR/$CHIP/$BANK
57 local BANK=$2
59 mkdir $CONFIGFS_DIR/$CHIP/$BANK
64 local BANK=$2
[all …]
/linux-6.14.4/drivers/pinctrl/renesas/
Dsh_pfc.h442 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
443 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
444 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) argument
446 #define PORT_GP_CFG_2(bank, fn, sfx, cfg) \ argument
447 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
448 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
449 #define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0) argument
451 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
452 PORT_GP_CFG_2(bank, fn, sfx, cfg), \
453 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
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/linux-6.14.4/tools/perf/pmu-events/arch/x86/broadwellde/
Duncore-memory.json198 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group th…
208 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major …
218 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major …
228 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode i…
553 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
558 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
562 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
567 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
572 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
577 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
[all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/broadwellx/
Duncore-memory.json235 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group th…
245 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major …
255 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major …
265 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode i…
590 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
595 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
599 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
604 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
609 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
614 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
[all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/haswellx/
Duncore-memory.json227 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group th…
237 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major …
247 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major …
257 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode i…
582 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
587 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
591 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
596 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
601 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
606 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
[all …]
/linux-6.14.4/drivers/net/phy/mscc/
Dmscc_macsec.c23 enum macsec_bank bank, u32 reg) in vsc8584_macsec_phy_read() argument
34 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_read()
36 if (bank >> 2 == 0x1) in vsc8584_macsec_phy_read()
38 bank &= 0x3; in vsc8584_macsec_phy_read()
40 bank = 0; in vsc8584_macsec_phy_read()
45 MSCC_PHY_MACSEC_19_TARGET(bank)); in vsc8584_macsec_phy_read()
62 enum macsec_bank bank, u32 reg, u32 val) in vsc8584_macsec_phy_write() argument
72 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_write()
74 if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3)) in vsc8584_macsec_phy_write()
75 bank &= 0x3; in vsc8584_macsec_phy_write()
[all …]
/linux-6.14.4/drivers/pinctrl/stm32/
Dpinctrl-stm32.c158 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, in stm32_gpio_backup_value() argument
161 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
162 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
165 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_mode() argument
168 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
170 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode()
171 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; in stm32_gpio_backup_mode()
174 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_driving() argument
177 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); in stm32_gpio_backup_driving()
178 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; in stm32_gpio_backup_driving()
[all …]
/linux-6.14.4/drivers/bus/
Duniphier-system-bus.c23 #define UNIPHIER_SBC_STRIDE 0x10 /* register stride to next bank */
25 #define UNIPHIER_SBC_BASE_DUMMY 0xffffffff /* data to squash bank 0, 1 */
35 struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS]; member
39 int bank, u32 addr, u64 paddr, u32 size) in uniphier_system_bus_add_bank() argument
44 "range found: bank = %d, addr = %08x, paddr = %08llx, size = %08x\n", in uniphier_system_bus_add_bank()
45 bank, addr, paddr, size); in uniphier_system_bus_add_bank()
47 if (bank >= ARRAY_SIZE(priv->bank)) { in uniphier_system_bus_add_bank()
48 dev_err(priv->dev, "unsupported bank number %d\n", bank); in uniphier_system_bus_add_bank()
52 if (priv->bank[bank].base || priv->bank[bank].end) { in uniphier_system_bus_add_bank()
54 "range for bank %d has already been specified\n", bank); in uniphier_system_bus_add_bank()
[all …]
/linux-6.14.4/arch/x86/kernel/cpu/mce/
Dthreshold.c35 void mce_inherit_storm(unsigned int bank) in mce_inherit_storm() argument
40 * Previous CPU owning this bank had put it into storm mode, in mce_inherit_storm()
42 * the worst (all recent polls of the bank found a valid error in mce_inherit_storm()
46 storm->banks[bank].history = ~0ull; in mce_inherit_storm()
47 storm->banks[bank].timestamp = jiffies; in mce_inherit_storm()
60 static void mce_handle_storm(unsigned int bank, bool on) in mce_handle_storm() argument
64 mce_intel_handle_storm(bank, on); in mce_handle_storm()
69 void cmci_storm_begin(unsigned int bank) in cmci_storm_begin() argument
73 __set_bit(bank, this_cpu_ptr(mce_poll_banks)); in cmci_storm_begin()
74 storm->banks[bank].in_storm_mode = true; in cmci_storm_begin()
[all …]
Damd.c131 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) in smca_get_bank_type() argument
135 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
138 b = &per_cpu(smca_banks, cpu)[bank]; in smca_get_bank_type()
212 * So to define a unique name for each bank, we use a temp c-string to append
222 /* This block's number within its bank. */
224 /* MCA bank number that contains this block. */
225 unsigned int bank; member
226 /* CPU which controls this block's MCA bank. */
232 /* Bank can generate an interrupt. */
238 /* List of threshold blocks within this block's MCA bank. */
[all …]
Dintel.c31 * CMCI can be delivered to multiple cpus that share a machine check bank
32 * so we need to designate a single cpu to process errors logged in each bank
61 * MCi_CTL2 threshold for each bank when there is no storm.
62 * Default value for each bank may have been set by BIOS.
71 * bank because both corrected and uncorrected errors may be logged
72 * in the same bank and signalled with CMCI. The threshold only applies
138 static void cmci_set_threshold(int bank, int thresh) in cmci_set_threshold() argument
144 rdmsrl(MSR_IA32_MCx_CTL2(bank), val); in cmci_set_threshold()
146 wrmsrl(MSR_IA32_MCx_CTL2(bank), val | thresh); in cmci_set_threshold()
150 void mce_intel_handle_storm(int bank, bool on) in mce_intel_handle_storm() argument
[all …]
/linux-6.14.4/arch/arm64/boot/dts/exynos/
Dexynos9810-pinctrl.dtsi12 etc1: etc1-gpio-bank {
20 gpa0: gpa0-gpio-bank {
37 gpa1: gpa1-gpio-bank {
54 gpa2: gpa2-gpio-bank {
71 gpa3: gpa3-gpio-bank {
88 gpa4: gpa4-gpio-bank {
96 gpq0: gpq0-gpio-bank {
106 gpb0: gpb0-gpio-bank {
114 gpb1: gpb1-gpio-bank {
122 gpb2: gpb2-gpio-bank {
[all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/skylakex/
Duncore-memory.json263 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group th…
274 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major …
285 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major …
296 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode i…
653 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
662 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
672 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
682 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
692 "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
702 "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
[all …]

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