Lines Matching full:bank
56 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
61 if (bank->eint_mask_offset) in exynos_irq_mask()
62 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_mask()
64 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
66 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_mask()
67 dev_err(bank->gpio_chip.parent, in exynos_irq_mask()
72 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
74 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
76 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask()
78 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_mask()
80 clk_disable(bank->drvdata->pclk); in exynos_irq_mask()
87 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_ack() local
90 if (bank->eint_pend_offset) in exynos_irq_ack()
91 reg_pend = bank->pctl_offset + bank->eint_pend_offset; in exynos_irq_ack()
93 reg_pend = our_chip->eint_pend + bank->eint_offset; in exynos_irq_ack()
95 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_ack()
96 dev_err(bank->gpio_chip.parent, in exynos_irq_ack()
101 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); in exynos_irq_ack()
103 clk_disable(bank->drvdata->pclk); in exynos_irq_ack()
110 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_unmask() local
126 if (bank->eint_mask_offset) in exynos_irq_unmask()
127 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_unmask()
129 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_unmask()
131 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_unmask()
132 dev_err(bank->gpio_chip.parent, in exynos_irq_unmask()
137 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_unmask()
139 mask = readl(bank->eint_base + reg_mask); in exynos_irq_unmask()
141 writel(mask, bank->eint_base + reg_mask); in exynos_irq_unmask()
143 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_unmask()
145 clk_disable(bank->drvdata->pclk); in exynos_irq_unmask()
152 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_set_type() local
184 if (bank->eint_con_offset) in exynos_irq_set_type()
185 reg_con = bank->pctl_offset + bank->eint_con_offset; in exynos_irq_set_type()
187 reg_con = our_chip->eint_con + bank->eint_offset; in exynos_irq_set_type()
189 ret = clk_enable(bank->drvdata->pclk); in exynos_irq_set_type()
191 dev_err(bank->gpio_chip.parent, in exynos_irq_set_type()
196 con = readl(bank->eint_base + reg_con); in exynos_irq_set_type()
199 writel(con, bank->eint_base + reg_con); in exynos_irq_set_type()
201 clk_disable(bank->drvdata->pclk); in exynos_irq_set_type()
209 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_set_affinity() local
210 struct samsung_pinctrl_drv_data *d = bank->drvdata; in exynos_irq_set_affinity()
221 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_request_resources() local
222 const struct samsung_pin_bank_type *bank_type = bank->type; in exynos_irq_request_resources()
227 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq); in exynos_irq_request_resources()
229 dev_err(bank->gpio_chip.parent, in exynos_irq_request_resources()
231 bank->name, irqd->hwirq); in exynos_irq_request_resources()
235 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; in exynos_irq_request_resources()
239 ret = clk_enable(bank->drvdata->pclk); in exynos_irq_request_resources()
241 dev_err(bank->gpio_chip.parent, in exynos_irq_request_resources()
243 bank->name, irqd->hwirq); in exynos_irq_request_resources()
247 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_request_resources()
249 con = readl(bank->pctl_base + reg_con); in exynos_irq_request_resources()
252 writel(con, bank->pctl_base + reg_con); in exynos_irq_request_resources()
254 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_request_resources()
256 clk_disable(bank->drvdata->pclk); in exynos_irq_request_resources()
263 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_release_resources() local
264 const struct samsung_pin_bank_type *bank_type = bank->type; in exynos_irq_release_resources()
268 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; in exynos_irq_release_resources()
272 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_release_resources()
273 dev_err(bank->gpio_chip.parent, in exynos_irq_release_resources()
275 bank->name, irqd->hwirq); in exynos_irq_release_resources()
279 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_release_resources()
281 con = readl(bank->pctl_base + reg_con); in exynos_irq_release_resources()
284 writel(con, bank->pctl_base + reg_con); in exynos_irq_release_resources()
286 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_release_resources()
288 clk_disable(bank->drvdata->pclk); in exynos_irq_release_resources()
290 gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq); in exynos_irq_release_resources()
335 struct samsung_pin_bank *bank = d->pin_banks; in exynos_eint_gpio_irq() local
339 if (clk_enable(bank->drvdata->pclk)) { in exynos_eint_gpio_irq()
340 dev_err(bank->gpio_chip.parent, in exynos_eint_gpio_irq()
345 if (bank->eint_con_offset) in exynos_eint_gpio_irq()
346 svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET); in exynos_eint_gpio_irq()
348 svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); in exynos_eint_gpio_irq()
350 clk_disable(bank->drvdata->pclk); in exynos_eint_gpio_irq()
357 bank += (group - 1); in exynos_eint_gpio_irq()
359 ret = generic_handle_domain_irq(bank->irq_domain, pin); in exynos_eint_gpio_irq()
379 struct samsung_pin_bank *bank; in exynos_eint_gpio_init() local
396 bank = d->pin_banks; in exynos_eint_gpio_init()
397 for (i = 0; i < d->nr_banks; ++i, ++bank) { in exynos_eint_gpio_init()
398 if (bank->eint_type != EINT_TYPE_GPIO) in exynos_eint_gpio_init()
401 bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip, in exynos_eint_gpio_init()
402 sizeof(*bank->irq_chip), GFP_KERNEL); in exynos_eint_gpio_init()
403 if (!bank->irq_chip) { in exynos_eint_gpio_init()
407 bank->irq_chip->chip.name = bank->name; in exynos_eint_gpio_init()
409 bank->irq_domain = irq_domain_create_linear(bank->fwnode, in exynos_eint_gpio_init()
410 bank->nr_pins, &exynos_eint_irqd_ops, bank); in exynos_eint_gpio_init()
411 if (!bank->irq_domain) { in exynos_eint_gpio_init()
417 bank->soc_priv = devm_kzalloc(d->dev, in exynos_eint_gpio_init()
419 if (!bank->soc_priv) { in exynos_eint_gpio_init()
420 irq_domain_remove(bank->irq_domain); in exynos_eint_gpio_init()
430 for (--i, --bank; i >= 0; --i, --bank) { in exynos_eint_gpio_init()
431 if (bank->eint_type != EINT_TYPE_GPIO) in exynos_eint_gpio_init()
433 irq_domain_remove(bank->irq_domain); in exynos_eint_gpio_init()
443 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_wkup_irq_set_wake() local
444 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); in exynos_wkup_irq_set_wake()
447 irqd->irq, bank->name, irqd->hwirq); in exynos_wkup_irq_set_wake()
465 …"No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n… in exynos_pinctrl_set_eint_wakeup_mask()
487 …"No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n… in s5pv210_pinctrl_set_eint_wakeup_mask()
597 struct samsung_pin_bank *bank = eintd->bank; in exynos_irq_eint0_15() local
602 generic_handle_domain_irq(bank->irq_domain, eintd->irq); in exynos_irq_eint0_15()
632 * each bank. in exynos_irq_demux_eint16_31()
669 struct samsung_pin_bank *bank; in exynos_eint_wkup_init() local
690 bank = d->pin_banks; in exynos_eint_wkup_init()
691 for (i = 0; i < d->nr_banks; ++i, ++bank) { in exynos_eint_wkup_init()
692 if (bank->eint_type != EINT_TYPE_WKUP) in exynos_eint_wkup_init()
695 bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip), in exynos_eint_wkup_init()
697 if (!bank->irq_chip) in exynos_eint_wkup_init()
699 bank->irq_chip->chip.name = bank->name; in exynos_eint_wkup_init()
701 bank->irq_domain = irq_domain_create_linear(bank->fwnode, in exynos_eint_wkup_init()
702 bank->nr_pins, &exynos_eint_irqd_ops, bank); in exynos_eint_wkup_init()
703 if (!bank->irq_domain) { in exynos_eint_wkup_init()
708 if (!fwnode_property_present(bank->fwnode, "interrupts")) { in exynos_eint_wkup_init()
709 bank->eint_type = EINT_TYPE_WKUP_MUX; in exynos_eint_wkup_init()
715 bank->nr_pins, sizeof(*weint_data), in exynos_eint_wkup_init()
720 for (idx = 0; idx < bank->nr_pins; ++idx) { in exynos_eint_wkup_init()
721 irq = irq_of_parse_and_map(to_of_node(bank->fwnode), idx); in exynos_eint_wkup_init()
724 bank->name, idx); in exynos_eint_wkup_init()
728 weint_data[idx].bank = bank; in exynos_eint_wkup_init()
753 bank = d->pin_banks; in exynos_eint_wkup_init()
755 for (i = 0; i < d->nr_banks; ++i, ++bank) { in exynos_eint_wkup_init()
756 if (bank->eint_type != EINT_TYPE_WKUP_MUX) in exynos_eint_wkup_init()
759 muxed_data->banks[idx++] = bank; in exynos_eint_wkup_init()
767 struct samsung_pin_bank *bank) in exynos_pinctrl_suspend_bank() argument
769 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynos_pinctrl_suspend_bank()
770 const void __iomem *regs = bank->eint_base; in exynos_pinctrl_suspend_bank()
772 if (clk_enable(bank->drvdata->pclk)) { in exynos_pinctrl_suspend_bank()
773 dev_err(bank->gpio_chip.parent, in exynos_pinctrl_suspend_bank()
779 + bank->eint_offset); in exynos_pinctrl_suspend_bank()
781 + 2 * bank->eint_offset); in exynos_pinctrl_suspend_bank()
783 + 2 * bank->eint_offset + 4); in exynos_pinctrl_suspend_bank()
784 save->eint_mask = readl(regs + bank->irq_chip->eint_mask in exynos_pinctrl_suspend_bank()
785 + bank->eint_offset); in exynos_pinctrl_suspend_bank()
787 clk_disable(bank->drvdata->pclk); in exynos_pinctrl_suspend_bank()
789 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); in exynos_pinctrl_suspend_bank()
790 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); in exynos_pinctrl_suspend_bank()
791 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); in exynos_pinctrl_suspend_bank()
792 pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); in exynos_pinctrl_suspend_bank()
796 struct samsung_pin_bank *bank) in exynosauto_pinctrl_suspend_bank() argument
798 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynosauto_pinctrl_suspend_bank()
799 const void __iomem *regs = bank->eint_base; in exynosauto_pinctrl_suspend_bank()
801 if (clk_enable(bank->drvdata->pclk)) { in exynosauto_pinctrl_suspend_bank()
802 dev_err(bank->gpio_chip.parent, in exynosauto_pinctrl_suspend_bank()
807 save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset); in exynosauto_pinctrl_suspend_bank()
808 save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset); in exynosauto_pinctrl_suspend_bank()
810 clk_disable(bank->drvdata->pclk); in exynosauto_pinctrl_suspend_bank()
812 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); in exynosauto_pinctrl_suspend_bank()
813 pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); in exynosauto_pinctrl_suspend_bank()
818 struct samsung_pin_bank *bank = drvdata->pin_banks; in exynos_pinctrl_suspend() local
822 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) { in exynos_pinctrl_suspend()
823 if (bank->eint_type == EINT_TYPE_GPIO) { in exynos_pinctrl_suspend()
824 if (bank->eint_con_offset) in exynos_pinctrl_suspend()
825 exynosauto_pinctrl_suspend_bank(drvdata, bank); in exynos_pinctrl_suspend()
827 exynos_pinctrl_suspend_bank(drvdata, bank); in exynos_pinctrl_suspend()
829 else if (bank->eint_type == EINT_TYPE_WKUP) { in exynos_pinctrl_suspend()
831 irq_chip = bank->irq_chip; in exynos_pinctrl_suspend()
841 struct samsung_pin_bank *bank) in exynos_pinctrl_resume_bank() argument
843 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynos_pinctrl_resume_bank()
844 void __iomem *regs = bank->eint_base; in exynos_pinctrl_resume_bank()
846 if (clk_enable(bank->drvdata->pclk)) { in exynos_pinctrl_resume_bank()
847 dev_err(bank->gpio_chip.parent, in exynos_pinctrl_resume_bank()
852 pr_debug("%s: con %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume_bank()
854 + bank->eint_offset), save->eint_con); in exynos_pinctrl_resume_bank()
855 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume_bank()
857 + 2 * bank->eint_offset), save->eint_fltcon0); in exynos_pinctrl_resume_bank()
858 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume_bank()
860 + 2 * bank->eint_offset + 4), save->eint_fltcon1); in exynos_pinctrl_resume_bank()
861 pr_debug("%s: mask %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume_bank()
862 readl(regs + bank->irq_chip->eint_mask in exynos_pinctrl_resume_bank()
863 + bank->eint_offset), save->eint_mask); in exynos_pinctrl_resume_bank()
866 + bank->eint_offset); in exynos_pinctrl_resume_bank()
868 + 2 * bank->eint_offset); in exynos_pinctrl_resume_bank()
870 + 2 * bank->eint_offset + 4); in exynos_pinctrl_resume_bank()
871 writel(save->eint_mask, regs + bank->irq_chip->eint_mask in exynos_pinctrl_resume_bank()
872 + bank->eint_offset); in exynos_pinctrl_resume_bank()
874 clk_disable(bank->drvdata->pclk); in exynos_pinctrl_resume_bank()
878 struct samsung_pin_bank *bank) in exynosauto_pinctrl_resume_bank() argument
880 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynosauto_pinctrl_resume_bank()
881 void __iomem *regs = bank->eint_base; in exynosauto_pinctrl_resume_bank()
883 if (clk_enable(bank->drvdata->pclk)) { in exynosauto_pinctrl_resume_bank()
884 dev_err(bank->gpio_chip.parent, in exynosauto_pinctrl_resume_bank()
889 pr_debug("%s: con %#010x => %#010x\n", bank->name, in exynosauto_pinctrl_resume_bank()
890 readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con); in exynosauto_pinctrl_resume_bank()
891 pr_debug("%s: mask %#010x => %#010x\n", bank->name, in exynosauto_pinctrl_resume_bank()
892 readl(regs + bank->pctl_offset + bank->eint_mask_offset), save->eint_mask); in exynosauto_pinctrl_resume_bank()
894 writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset); in exynosauto_pinctrl_resume_bank()
895 writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset); in exynosauto_pinctrl_resume_bank()
897 clk_disable(bank->drvdata->pclk); in exynosauto_pinctrl_resume_bank()
902 struct samsung_pin_bank *bank = drvdata->pin_banks; in exynos_pinctrl_resume() local
905 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) in exynos_pinctrl_resume()
906 if (bank->eint_type == EINT_TYPE_GPIO) { in exynos_pinctrl_resume()
907 if (bank->eint_con_offset) in exynos_pinctrl_resume()
908 exynosauto_pinctrl_resume_bank(drvdata, bank); in exynos_pinctrl_resume()
910 exynos_pinctrl_resume_bank(drvdata, bank); in exynos_pinctrl_resume()