158 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,  in stm32_gpio_backup_value()  argument
161 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);  in stm32_gpio_backup_value()
162 	bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;  in stm32_gpio_backup_value()
165 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,  in stm32_gpio_backup_mode()  argument
168 	bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |  in stm32_gpio_backup_mode()
170 	bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;  in stm32_gpio_backup_mode()
171 	bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;  in stm32_gpio_backup_mode()
174 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,  in stm32_gpio_backup_driving()  argument
177 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);  in stm32_gpio_backup_driving()
178 	bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;  in stm32_gpio_backup_driving()
181 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,  in stm32_gpio_backup_speed()  argument
184 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;  in stm32_gpio_backup_speed()
185 	bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;  in stm32_gpio_backup_speed()
188 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,  in stm32_gpio_backup_bias()  argument
191 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;  in stm32_gpio_backup_bias()
192 	bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;  in stm32_gpio_backup_bias()
197 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,  in __stm32_gpio_set()  argument
200 	stm32_gpio_backup_value(bank, offset, value);  in __stm32_gpio_set()
205 	writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);  in __stm32_gpio_set()
210 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_request()  local
211 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_request()
213 	int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);  in stm32_gpio_request()
226 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_get()  local
228 	return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));  in stm32_gpio_get()
233 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_set()  local
235 	__stm32_gpio_set(bank, offset, value);  in stm32_gpio_set()
241 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_direction_output()  local
243 	__stm32_gpio_set(bank, offset, value);  in stm32_gpio_direction_output()
251 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_to_irq()  local
254 	fwspec.fwnode = bank->fwnode;  in stm32_gpio_to_irq()
264 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_get_direction()  local
269 	stm32_pmx_get_mode(bank, pin, &mode, &alt);  in stm32_gpio_get_direction()
284 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_init_valid_mask()  local
285 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_init_valid_mask()
292 	if (bank->secure_control) {  in stm32_gpio_init_valid_mask()
294 		sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR);  in stm32_gpio_init_valid_mask()
299 				dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i);  in stm32_gpio_init_valid_mask()
322 	struct stm32_gpio_bank *bank = d->domain->host_data;  in stm32_gpio_irq_trigger()  local
326 	if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))  in stm32_gpio_irq_trigger()
330 	level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);  in stm32_gpio_irq_trigger()
331 	if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||  in stm32_gpio_irq_trigger()
332 	    (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))  in stm32_gpio_irq_trigger()
344 	struct stm32_gpio_bank *bank = d->domain->host_data;  in stm32_gpio_set_type()  local
363 	bank->irq_type[d->hwirq] = type;  in stm32_gpio_set_type()
370 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;  in stm32_gpio_irq_request_resources()  local
371 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_irq_request_resources()
374 	ret = pinctrl_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);  in stm32_gpio_irq_request_resources()
378 	ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);  in stm32_gpio_irq_request_resources()
390 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;  in stm32_gpio_irq_release_resources()  local
392 	gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);  in stm32_gpio_irq_release_resources()
430 	struct stm32_gpio_bank *bank = d->host_data;  in stm32_gpio_domain_activate()  local
431 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_domain_activate()
443 	regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);  in stm32_gpio_domain_activate()
455 	struct stm32_gpio_bank *bank = d->host_data;  in stm32_gpio_domain_alloc()  local
458 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_domain_alloc()
486 				      bank);  in stm32_gpio_domain_alloc()
494 	struct stm32_gpio_bank *bank = d->host_data;  in stm32_gpio_domain_free()  local
495 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_domain_free()
756 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,  in stm32_pmx_set_mode()  argument
759 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pmx_set_mode()
766 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pmx_set_mode()
777 	val = readl_relaxed(bank->base + alt_offset);  in stm32_pmx_set_mode()
780 	writel_relaxed(val, bank->base + alt_offset);  in stm32_pmx_set_mode()
782 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);  in stm32_pmx_set_mode()
785 	writel_relaxed(val, bank->base + STM32_GPIO_MODER);  in stm32_pmx_set_mode()
790 	stm32_gpio_backup_mode(bank, pin, mode, alt);  in stm32_pmx_set_mode()
793 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pmx_set_mode()
798 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,  in stm32_pmx_get_mode()  argument
806 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pmx_get_mode()
808 	val = readl_relaxed(bank->base + alt_offset);  in stm32_pmx_get_mode()
812 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);  in stm32_pmx_get_mode()
816 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pmx_get_mode()
827 	struct stm32_gpio_bank *bank;  in stm32_pmx_set_mux()  local
841 	bank = gpiochip_get_data(range->gc);  in stm32_pmx_set_mux()
847 	return stm32_pmx_set_mode(bank, pin, mode, alt);  in stm32_pmx_set_mux()
854 	struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);  in stm32_pmx_gpio_set_direction()  local
857 	return stm32_pmx_set_mode(bank, pin, !input, 0);  in stm32_pmx_gpio_set_direction()
891 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,  in stm32_pconf_set_driving()  argument
894 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pconf_set_driving()
899 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_set_driving()
910 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);  in stm32_pconf_set_driving()
913 	writel_relaxed(val, bank->base + STM32_GPIO_TYPER);  in stm32_pconf_set_driving()
918 	stm32_gpio_backup_driving(bank, offset, drive);  in stm32_pconf_set_driving()
921 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_set_driving()
926 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,  in stm32_pconf_get_driving()  argument
932 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get_driving()
934 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);  in stm32_pconf_get_driving()
937 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get_driving()
942 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,  in stm32_pconf_set_speed()  argument
945 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pconf_set_speed()
950 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_set_speed()
961 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);  in stm32_pconf_set_speed()
964 	writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);  in stm32_pconf_set_speed()
969 	stm32_gpio_backup_speed(bank, offset, speed);  in stm32_pconf_set_speed()
972 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_set_speed()
977 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,  in stm32_pconf_get_speed()  argument
983 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get_speed()
985 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);  in stm32_pconf_get_speed()
988 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get_speed()
993 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,  in stm32_pconf_set_bias()  argument
996 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pconf_set_bias()
1001 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_set_bias()
1012 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);  in stm32_pconf_set_bias()
1015 	writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);  in stm32_pconf_set_bias()
1020 	stm32_gpio_backup_bias(bank, offset, bias);  in stm32_pconf_set_bias()
1023 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_set_bias()
1028 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,  in stm32_pconf_get_bias()  argument
1034 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get_bias()
1036 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);  in stm32_pconf_get_bias()
1039 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get_bias()
1044 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,  in stm32_pconf_get()  argument
1050 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get()
1053 		val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &  in stm32_pconf_get()
1056 		val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &  in stm32_pconf_get()
1059 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get()
1070 	struct stm32_gpio_bank *bank;  in stm32_pconf_parse_conf()  local
1079 	bank = gpiochip_get_data(range->gc);  in stm32_pconf_parse_conf()
1089 		ret = stm32_pconf_set_driving(bank, offset, 0);  in stm32_pconf_parse_conf()
1092 		ret = stm32_pconf_set_driving(bank, offset, 1);  in stm32_pconf_parse_conf()
1095 		ret = stm32_pconf_set_speed(bank, offset, arg);  in stm32_pconf_parse_conf()
1098 		ret = stm32_pconf_set_bias(bank, offset, 0);  in stm32_pconf_parse_conf()
1101 		ret = stm32_pconf_set_bias(bank, offset, 1);  in stm32_pconf_parse_conf()
1104 		ret = stm32_pconf_set_bias(bank, offset, 2);  in stm32_pconf_parse_conf()
1107 		__stm32_gpio_set(bank, offset, arg);  in stm32_pconf_parse_conf()
1188 	struct stm32_gpio_bank *bank;  in stm32_pconf_dbg_show()  local
1203 	bank = gpiochip_get_data(range->gc);  in stm32_pconf_dbg_show()
1211 	stm32_pmx_get_mode(bank, offset, &mode, &alt);  in stm32_pconf_dbg_show()
1212 	bias = stm32_pconf_get_bias(bank, offset);  in stm32_pconf_dbg_show()
1219 		val = stm32_pconf_get(bank, offset, true);  in stm32_pconf_dbg_show()
1227 		drive = stm32_pconf_get_driving(bank, offset);  in stm32_pconf_dbg_show()
1228 		speed = stm32_pconf_get_speed(bank, offset);  in stm32_pconf_dbg_show()
1229 		val = stm32_pconf_get(bank, offset, false);  in stm32_pconf_dbg_show()
1239 		drive = stm32_pconf_get_driving(bank, offset);  in stm32_pconf_dbg_show()
1240 		speed = stm32_pconf_get_speed(bank, offset);  in stm32_pconf_dbg_show()
1266 								 struct stm32_gpio_bank *bank,  in stm32_pctrl_get_desc_pin_from_gpio()  argument
1269 	unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset;  in stm32_pctrl_get_desc_pin_from_gpio()
1273 	/* With few exceptions (e.g. bank 'Z'), pin number matches with pin index in array */  in stm32_pctrl_get_desc_pin_from_gpio()
1291 	struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];  in stm32_gpiolib_register_bank()  local
1293 	struct pinctrl_gpio_range *range = &bank->range;  in stm32_gpiolib_register_bank()
1302 	if (!IS_ERR(bank->rstc))  in stm32_gpiolib_register_bank()
1303 		reset_control_deassert(bank->rstc);  in stm32_gpiolib_register_bank()
1308 	bank->base = devm_ioremap_resource(dev, &res);  in stm32_gpiolib_register_bank()
1309 	if (IS_ERR(bank->base))  in stm32_gpiolib_register_bank()
1310 		return PTR_ERR(bank->base);  in stm32_gpiolib_register_bank()
1312 	bank->gpio_chip = stm32_gpio_template;  in stm32_gpiolib_register_bank()
1314 	fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label);  in stm32_gpiolib_register_bank()
1318 		bank->gpio_chip.base = args.args[1];  in stm32_gpiolib_register_bank()
1326 		bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;  in stm32_gpiolib_register_bank()
1327 		range->name = bank->gpio_chip.label;  in stm32_gpiolib_register_bank()
1332 		range->gc = &bank->gpio_chip;  in stm32_gpiolib_register_bank()
1337 	if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr))  in stm32_gpiolib_register_bank()
1340 	bank->gpio_chip.base = -1;  in stm32_gpiolib_register_bank()
1342 	bank->gpio_chip.ngpio = npins;  in stm32_gpiolib_register_bank()
1343 	bank->gpio_chip.fwnode = fwnode;  in stm32_gpiolib_register_bank()
1344 	bank->gpio_chip.parent = dev;  in stm32_gpiolib_register_bank()
1345 	bank->bank_nr = bank_nr;  in stm32_gpiolib_register_bank()
1346 	bank->bank_ioport_nr = bank_ioport_nr;  in stm32_gpiolib_register_bank()
1347 	bank->secure_control = pctl->match_data->secure_control;  in stm32_gpiolib_register_bank()
1348 	spin_lock_init(&bank->lock);  in stm32_gpiolib_register_bank()
1352 		bank->fwnode = fwnode;  in stm32_gpiolib_register_bank()
1354 		bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,  in stm32_gpiolib_register_bank()
1355 							   bank->fwnode, &stm32_gpio_domain_ops,  in stm32_gpiolib_register_bank()
1356 							   bank);  in stm32_gpiolib_register_bank()
1358 		if (!bank->domain)  in stm32_gpiolib_register_bank()
1367 		stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i);  in stm32_gpiolib_register_bank()
1377 	bank->gpio_chip.names = (const char * const *)names;  in stm32_gpiolib_register_bank()
1379 	err = gpiochip_add_data(&bank->gpio_chip, bank);  in stm32_gpiolib_register_bank()
1385 	dev_info(dev, "%s bank added\n", bank->gpio_chip.label);  in stm32_gpiolib_register_bank()
1601 		dev_err(dev, "at least one GPIO bank is required\n");  in stm32_pctl_probe()
1616 		struct stm32_gpio_bank *bank = &pctl->banks[i];  in stm32_pctl_probe()  local
1619 		bank->rstc = of_reset_control_get_exclusive(np, NULL);  in stm32_pctl_probe()
1620 		if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {  in stm32_pctl_probe()
1656 		struct stm32_gpio_bank *bank = &pctl->banks[i];  in stm32_pctl_probe()  local
1658 		gpiochip_remove(&bank->gpio_chip);  in stm32_pctl_probe()
1671 	struct stm32_gpio_bank *bank;  in stm32_pinctrl_restore_gpio_regs()  local
1687 	bank = gpiochip_get_data(range->gc);  in stm32_pinctrl_restore_gpio_regs()
1689 	alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;  in stm32_pinctrl_restore_gpio_regs()
1691 	mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;  in stm32_pinctrl_restore_gpio_regs()
1694 	ret = stm32_pmx_set_mode(bank, offset, mode, alt);  in stm32_pinctrl_restore_gpio_regs()
1699 		val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);  in stm32_pinctrl_restore_gpio_regs()
1701 		__stm32_gpio_set(bank, offset, val);  in stm32_pinctrl_restore_gpio_regs()
1704 	val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);  in stm32_pinctrl_restore_gpio_regs()
1706 	ret = stm32_pconf_set_driving(bank, offset, val);  in stm32_pinctrl_restore_gpio_regs()
1710 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;  in stm32_pinctrl_restore_gpio_regs()
1712 	ret = stm32_pconf_set_speed(bank, offset, val);  in stm32_pinctrl_restore_gpio_regs()
1716 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;  in stm32_pinctrl_restore_gpio_regs()
1718 	ret = stm32_pconf_set_bias(bank, offset, val);  in stm32_pinctrl_restore_gpio_regs()
1723 		regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);  in stm32_pinctrl_restore_gpio_regs()