1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
4 //
5 // Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 // http://www.samsung.com
7 // Copyright (c) 2012 Linaro Ltd
8 // http://www.linaro.org
9 //
10 // Author: Thomas Abraham <[email protected]>
11 //
12 // This file contains the Samsung Exynos specific information required by the
13 // the Samsung pinctrl/gpiolib driver. It also includes the implementation of
14 // external gpio and wakeup interrupt support.
15
16 #include <linux/clk.h>
17 #include <linux/device.h>
18 #include <linux/interrupt.h>
19 #include <linux/irqdomain.h>
20 #include <linux/irq.h>
21 #include <linux/irqchip/chained_irq.h>
22 #include <linux/of.h>
23 #include <linux/of_irq.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/string_choices.h>
27 #include <linux/regmap.h>
28 #include <linux/err.h>
29 #include <linux/soc/samsung/exynos-pmu.h>
30 #include <linux/soc/samsung/exynos-regs-pmu.h>
31
32 #include "pinctrl-samsung.h"
33 #include "pinctrl-exynos.h"
34
35 struct exynos_irq_chip {
36 struct irq_chip chip;
37
38 u32 eint_con;
39 u32 eint_mask;
40 u32 eint_pend;
41 u32 *eint_wake_mask_value;
42 u32 eint_wake_mask_reg;
43 void (*set_eint_wakeup_mask)(struct samsung_pinctrl_drv_data *drvdata,
44 struct exynos_irq_chip *irq_chip);
45 };
46
to_exynos_irq_chip(struct irq_chip * chip)47 static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
48 {
49 return container_of(chip, struct exynos_irq_chip, chip);
50 }
51
exynos_irq_mask(struct irq_data * irqd)52 static void exynos_irq_mask(struct irq_data *irqd)
53 {
54 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
55 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
56 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
57 unsigned long reg_mask;
58 unsigned int mask;
59 unsigned long flags;
60
61 if (bank->eint_mask_offset)
62 reg_mask = bank->pctl_offset + bank->eint_mask_offset;
63 else
64 reg_mask = our_chip->eint_mask + bank->eint_offset;
65
66 if (clk_enable(bank->drvdata->pclk)) {
67 dev_err(bank->gpio_chip.parent,
68 "unable to enable clock for masking IRQ\n");
69 return;
70 }
71
72 raw_spin_lock_irqsave(&bank->slock, flags);
73
74 mask = readl(bank->eint_base + reg_mask);
75 mask |= 1 << irqd->hwirq;
76 writel(mask, bank->eint_base + reg_mask);
77
78 raw_spin_unlock_irqrestore(&bank->slock, flags);
79
80 clk_disable(bank->drvdata->pclk);
81 }
82
exynos_irq_ack(struct irq_data * irqd)83 static void exynos_irq_ack(struct irq_data *irqd)
84 {
85 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
86 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
87 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
88 unsigned long reg_pend;
89
90 if (bank->eint_pend_offset)
91 reg_pend = bank->pctl_offset + bank->eint_pend_offset;
92 else
93 reg_pend = our_chip->eint_pend + bank->eint_offset;
94
95 if (clk_enable(bank->drvdata->pclk)) {
96 dev_err(bank->gpio_chip.parent,
97 "unable to enable clock to ack IRQ\n");
98 return;
99 }
100
101 writel(1 << irqd->hwirq, bank->eint_base + reg_pend);
102
103 clk_disable(bank->drvdata->pclk);
104 }
105
exynos_irq_unmask(struct irq_data * irqd)106 static void exynos_irq_unmask(struct irq_data *irqd)
107 {
108 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
109 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
110 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
111 unsigned long reg_mask;
112 unsigned int mask;
113 unsigned long flags;
114
115 /*
116 * Ack level interrupts right before unmask
117 *
118 * If we don't do this we'll get a double-interrupt. Level triggered
119 * interrupts must not fire an interrupt if the level is not
120 * _currently_ active, even if it was active while the interrupt was
121 * masked.
122 */
123 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
124 exynos_irq_ack(irqd);
125
126 if (bank->eint_mask_offset)
127 reg_mask = bank->pctl_offset + bank->eint_mask_offset;
128 else
129 reg_mask = our_chip->eint_mask + bank->eint_offset;
130
131 if (clk_enable(bank->drvdata->pclk)) {
132 dev_err(bank->gpio_chip.parent,
133 "unable to enable clock for unmasking IRQ\n");
134 return;
135 }
136
137 raw_spin_lock_irqsave(&bank->slock, flags);
138
139 mask = readl(bank->eint_base + reg_mask);
140 mask &= ~(1 << irqd->hwirq);
141 writel(mask, bank->eint_base + reg_mask);
142
143 raw_spin_unlock_irqrestore(&bank->slock, flags);
144
145 clk_disable(bank->drvdata->pclk);
146 }
147
exynos_irq_set_type(struct irq_data * irqd,unsigned int type)148 static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
149 {
150 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
151 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
152 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
153 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
154 unsigned int con, trig_type;
155 unsigned long reg_con;
156 int ret;
157
158 switch (type) {
159 case IRQ_TYPE_EDGE_RISING:
160 trig_type = EXYNOS_EINT_EDGE_RISING;
161 break;
162 case IRQ_TYPE_EDGE_FALLING:
163 trig_type = EXYNOS_EINT_EDGE_FALLING;
164 break;
165 case IRQ_TYPE_EDGE_BOTH:
166 trig_type = EXYNOS_EINT_EDGE_BOTH;
167 break;
168 case IRQ_TYPE_LEVEL_HIGH:
169 trig_type = EXYNOS_EINT_LEVEL_HIGH;
170 break;
171 case IRQ_TYPE_LEVEL_LOW:
172 trig_type = EXYNOS_EINT_LEVEL_LOW;
173 break;
174 default:
175 pr_err("unsupported external interrupt type\n");
176 return -EINVAL;
177 }
178
179 if (type & IRQ_TYPE_EDGE_BOTH)
180 irq_set_handler_locked(irqd, handle_edge_irq);
181 else
182 irq_set_handler_locked(irqd, handle_level_irq);
183
184 if (bank->eint_con_offset)
185 reg_con = bank->pctl_offset + bank->eint_con_offset;
186 else
187 reg_con = our_chip->eint_con + bank->eint_offset;
188
189 ret = clk_enable(bank->drvdata->pclk);
190 if (ret) {
191 dev_err(bank->gpio_chip.parent,
192 "unable to enable clock for configuring IRQ type\n");
193 return ret;
194 }
195
196 con = readl(bank->eint_base + reg_con);
197 con &= ~(EXYNOS_EINT_CON_MASK << shift);
198 con |= trig_type << shift;
199 writel(con, bank->eint_base + reg_con);
200
201 clk_disable(bank->drvdata->pclk);
202
203 return 0;
204 }
205
exynos_irq_set_affinity(struct irq_data * irqd,const struct cpumask * dest,bool force)206 static int exynos_irq_set_affinity(struct irq_data *irqd,
207 const struct cpumask *dest, bool force)
208 {
209 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
210 struct samsung_pinctrl_drv_data *d = bank->drvdata;
211 struct irq_data *parent = irq_get_irq_data(d->irq);
212
213 if (parent)
214 return parent->chip->irq_set_affinity(parent, dest, force);
215
216 return -EINVAL;
217 }
218
exynos_irq_request_resources(struct irq_data * irqd)219 static int exynos_irq_request_resources(struct irq_data *irqd)
220 {
221 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
222 const struct samsung_pin_bank_type *bank_type = bank->type;
223 unsigned long reg_con, flags;
224 unsigned int shift, mask, con;
225 int ret;
226
227 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq);
228 if (ret) {
229 dev_err(bank->gpio_chip.parent,
230 "unable to lock pin %s-%lu IRQ\n",
231 bank->name, irqd->hwirq);
232 return ret;
233 }
234
235 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
236 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
237 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
238
239 ret = clk_enable(bank->drvdata->pclk);
240 if (ret) {
241 dev_err(bank->gpio_chip.parent,
242 "unable to enable clock for configuring pin %s-%lu\n",
243 bank->name, irqd->hwirq);
244 return ret;
245 }
246
247 raw_spin_lock_irqsave(&bank->slock, flags);
248
249 con = readl(bank->pctl_base + reg_con);
250 con &= ~(mask << shift);
251 con |= EXYNOS_PIN_CON_FUNC_EINT << shift;
252 writel(con, bank->pctl_base + reg_con);
253
254 raw_spin_unlock_irqrestore(&bank->slock, flags);
255
256 clk_disable(bank->drvdata->pclk);
257
258 return 0;
259 }
260
exynos_irq_release_resources(struct irq_data * irqd)261 static void exynos_irq_release_resources(struct irq_data *irqd)
262 {
263 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
264 const struct samsung_pin_bank_type *bank_type = bank->type;
265 unsigned long reg_con, flags;
266 unsigned int shift, mask, con;
267
268 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
269 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
270 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
271
272 if (clk_enable(bank->drvdata->pclk)) {
273 dev_err(bank->gpio_chip.parent,
274 "unable to enable clock for deconfiguring pin %s-%lu\n",
275 bank->name, irqd->hwirq);
276 return;
277 }
278
279 raw_spin_lock_irqsave(&bank->slock, flags);
280
281 con = readl(bank->pctl_base + reg_con);
282 con &= ~(mask << shift);
283 con |= PIN_CON_FUNC_INPUT << shift;
284 writel(con, bank->pctl_base + reg_con);
285
286 raw_spin_unlock_irqrestore(&bank->slock, flags);
287
288 clk_disable(bank->drvdata->pclk);
289
290 gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
291 }
292
293 /*
294 * irq_chip for gpio interrupts.
295 */
296 static const struct exynos_irq_chip exynos_gpio_irq_chip __initconst = {
297 .chip = {
298 .name = "exynos_gpio_irq_chip",
299 .irq_unmask = exynos_irq_unmask,
300 .irq_mask = exynos_irq_mask,
301 .irq_ack = exynos_irq_ack,
302 .irq_set_type = exynos_irq_set_type,
303 .irq_set_affinity = exynos_irq_set_affinity,
304 .irq_request_resources = exynos_irq_request_resources,
305 .irq_release_resources = exynos_irq_release_resources,
306 },
307 .eint_con = EXYNOS_GPIO_ECON_OFFSET,
308 .eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
309 .eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
310 /* eint_wake_mask_value not used */
311 };
312
exynos_eint_irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)313 static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
314 irq_hw_number_t hw)
315 {
316 struct samsung_pin_bank *b = h->host_data;
317
318 irq_set_chip_data(virq, b);
319 irq_set_chip_and_handler(virq, &b->irq_chip->chip,
320 handle_level_irq);
321 return 0;
322 }
323
324 /*
325 * irq domain callbacks for external gpio and wakeup interrupt controllers.
326 */
327 static const struct irq_domain_ops exynos_eint_irqd_ops = {
328 .map = exynos_eint_irq_map,
329 .xlate = irq_domain_xlate_twocell,
330 };
331
exynos_eint_gpio_irq(int irq,void * data)332 static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
333 {
334 struct samsung_pinctrl_drv_data *d = data;
335 struct samsung_pin_bank *bank = d->pin_banks;
336 unsigned int svc, group, pin;
337 int ret;
338
339 if (clk_enable(bank->drvdata->pclk)) {
340 dev_err(bank->gpio_chip.parent,
341 "unable to enable clock for handling IRQ\n");
342 return IRQ_NONE;
343 }
344
345 if (bank->eint_con_offset)
346 svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET);
347 else
348 svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
349
350 clk_disable(bank->drvdata->pclk);
351
352 group = EXYNOS_SVC_GROUP(svc);
353 pin = svc & EXYNOS_SVC_NUM_MASK;
354
355 if (!group)
356 return IRQ_HANDLED;
357 bank += (group - 1);
358
359 ret = generic_handle_domain_irq(bank->irq_domain, pin);
360 if (ret)
361 return IRQ_NONE;
362
363 return IRQ_HANDLED;
364 }
365
366 struct exynos_eint_gpio_save {
367 u32 eint_con;
368 u32 eint_fltcon0;
369 u32 eint_fltcon1;
370 u32 eint_mask;
371 };
372
373 /*
374 * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
375 * @d: driver data of samsung pinctrl driver.
376 */
exynos_eint_gpio_init(struct samsung_pinctrl_drv_data * d)377 __init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
378 {
379 struct samsung_pin_bank *bank;
380 struct device *dev = d->dev;
381 int ret;
382 int i;
383
384 if (!d->irq) {
385 dev_err(dev, "irq number not available\n");
386 return -EINVAL;
387 }
388
389 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
390 0, dev_name(dev), d);
391 if (ret) {
392 dev_err(dev, "irq request failed\n");
393 return -ENXIO;
394 }
395
396 bank = d->pin_banks;
397 for (i = 0; i < d->nr_banks; ++i, ++bank) {
398 if (bank->eint_type != EINT_TYPE_GPIO)
399 continue;
400
401 bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip,
402 sizeof(*bank->irq_chip), GFP_KERNEL);
403 if (!bank->irq_chip) {
404 ret = -ENOMEM;
405 goto err_domains;
406 }
407 bank->irq_chip->chip.name = bank->name;
408
409 bank->irq_domain = irq_domain_create_linear(bank->fwnode,
410 bank->nr_pins, &exynos_eint_irqd_ops, bank);
411 if (!bank->irq_domain) {
412 dev_err(dev, "gpio irq domain add failed\n");
413 ret = -ENXIO;
414 goto err_domains;
415 }
416
417 bank->soc_priv = devm_kzalloc(d->dev,
418 sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
419 if (!bank->soc_priv) {
420 irq_domain_remove(bank->irq_domain);
421 ret = -ENOMEM;
422 goto err_domains;
423 }
424
425 }
426
427 return 0;
428
429 err_domains:
430 for (--i, --bank; i >= 0; --i, --bank) {
431 if (bank->eint_type != EINT_TYPE_GPIO)
432 continue;
433 irq_domain_remove(bank->irq_domain);
434 }
435
436 return ret;
437 }
438
exynos_wkup_irq_set_wake(struct irq_data * irqd,unsigned int on)439 static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
440 {
441 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
442 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
443 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
444 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
445
446 pr_info("wake %s for irq %u (%s-%lu)\n", str_enabled_disabled(on),
447 irqd->irq, bank->name, irqd->hwirq);
448
449 if (!on)
450 *our_chip->eint_wake_mask_value |= bit;
451 else
452 *our_chip->eint_wake_mask_value &= ~bit;
453
454 return 0;
455 }
456
457 static void
exynos_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data * drvdata,struct exynos_irq_chip * irq_chip)458 exynos_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata,
459 struct exynos_irq_chip *irq_chip)
460 {
461 struct regmap *pmu_regs;
462
463 if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) {
464 dev_warn(drvdata->dev,
465 "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n");
466 return;
467 }
468
469 pmu_regs = drvdata->retention_ctrl->priv;
470 dev_info(drvdata->dev,
471 "Setting external wakeup interrupt mask: 0x%x\n",
472 *irq_chip->eint_wake_mask_value);
473
474 regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg,
475 *irq_chip->eint_wake_mask_value);
476 }
477
478 static void
s5pv210_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data * drvdata,struct exynos_irq_chip * irq_chip)479 s5pv210_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata,
480 struct exynos_irq_chip *irq_chip)
481
482 {
483 void __iomem *clk_base;
484
485 if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) {
486 dev_warn(drvdata->dev,
487 "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n");
488 return;
489 }
490
491
492 clk_base = (void __iomem *) drvdata->retention_ctrl->priv;
493
494 __raw_writel(*irq_chip->eint_wake_mask_value,
495 clk_base + irq_chip->eint_wake_mask_reg);
496 }
497
498 static u32 eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED;
499 /*
500 * irq_chip for wakeup interrupts
501 */
502 static const struct exynos_irq_chip s5pv210_wkup_irq_chip __initconst = {
503 .chip = {
504 .name = "s5pv210_wkup_irq_chip",
505 .irq_unmask = exynos_irq_unmask,
506 .irq_mask = exynos_irq_mask,
507 .irq_ack = exynos_irq_ack,
508 .irq_set_type = exynos_irq_set_type,
509 .irq_set_wake = exynos_wkup_irq_set_wake,
510 .irq_request_resources = exynos_irq_request_resources,
511 .irq_release_resources = exynos_irq_release_resources,
512 },
513 .eint_con = EXYNOS_WKUP_ECON_OFFSET,
514 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
515 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
516 .eint_wake_mask_value = &eint_wake_mask_value,
517 /* Only differences with exynos4210_wkup_irq_chip: */
518 .eint_wake_mask_reg = S5PV210_EINT_WAKEUP_MASK,
519 .set_eint_wakeup_mask = s5pv210_pinctrl_set_eint_wakeup_mask,
520 };
521
522 static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = {
523 .chip = {
524 .name = "exynos4210_wkup_irq_chip",
525 .irq_unmask = exynos_irq_unmask,
526 .irq_mask = exynos_irq_mask,
527 .irq_ack = exynos_irq_ack,
528 .irq_set_type = exynos_irq_set_type,
529 .irq_set_wake = exynos_wkup_irq_set_wake,
530 .irq_request_resources = exynos_irq_request_resources,
531 .irq_release_resources = exynos_irq_release_resources,
532 },
533 .eint_con = EXYNOS_WKUP_ECON_OFFSET,
534 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
535 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
536 .eint_wake_mask_value = &eint_wake_mask_value,
537 .eint_wake_mask_reg = EXYNOS_EINT_WAKEUP_MASK,
538 .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
539 };
540
541 static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = {
542 .chip = {
543 .name = "exynos7_wkup_irq_chip",
544 .irq_unmask = exynos_irq_unmask,
545 .irq_mask = exynos_irq_mask,
546 .irq_ack = exynos_irq_ack,
547 .irq_set_type = exynos_irq_set_type,
548 .irq_set_wake = exynos_wkup_irq_set_wake,
549 .irq_request_resources = exynos_irq_request_resources,
550 .irq_release_resources = exynos_irq_release_resources,
551 },
552 .eint_con = EXYNOS7_WKUP_ECON_OFFSET,
553 .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
554 .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
555 .eint_wake_mask_value = &eint_wake_mask_value,
556 .eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK,
557 .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
558 };
559
560 static const struct exynos_irq_chip exynosautov920_wkup_irq_chip __initconst = {
561 .chip = {
562 .name = "exynosautov920_wkup_irq_chip",
563 .irq_unmask = exynos_irq_unmask,
564 .irq_mask = exynos_irq_mask,
565 .irq_ack = exynos_irq_ack,
566 .irq_set_type = exynos_irq_set_type,
567 .irq_set_wake = exynos_wkup_irq_set_wake,
568 .irq_request_resources = exynos_irq_request_resources,
569 .irq_release_resources = exynos_irq_release_resources,
570 },
571 .eint_wake_mask_value = &eint_wake_mask_value,
572 .eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK,
573 .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
574 };
575
576 /* list of external wakeup controllers supported */
577 static const struct of_device_id exynos_wkup_irq_ids[] = {
578 { .compatible = "samsung,s5pv210-wakeup-eint",
579 .data = &s5pv210_wkup_irq_chip },
580 { .compatible = "samsung,exynos4210-wakeup-eint",
581 .data = &exynos4210_wkup_irq_chip },
582 { .compatible = "samsung,exynos7-wakeup-eint",
583 .data = &exynos7_wkup_irq_chip },
584 { .compatible = "samsung,exynos850-wakeup-eint",
585 .data = &exynos7_wkup_irq_chip },
586 { .compatible = "samsung,exynosautov9-wakeup-eint",
587 .data = &exynos7_wkup_irq_chip },
588 { .compatible = "samsung,exynosautov920-wakeup-eint",
589 .data = &exynosautov920_wkup_irq_chip },
590 { }
591 };
592
593 /* interrupt handler for wakeup interrupts 0..15 */
exynos_irq_eint0_15(struct irq_desc * desc)594 static void exynos_irq_eint0_15(struct irq_desc *desc)
595 {
596 struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc);
597 struct samsung_pin_bank *bank = eintd->bank;
598 struct irq_chip *chip = irq_desc_get_chip(desc);
599
600 chained_irq_enter(chip, desc);
601
602 generic_handle_domain_irq(bank->irq_domain, eintd->irq);
603
604 chained_irq_exit(chip, desc);
605 }
606
exynos_irq_demux_eint(unsigned int pend,struct irq_domain * domain)607 static inline void exynos_irq_demux_eint(unsigned int pend,
608 struct irq_domain *domain)
609 {
610 unsigned int irq;
611
612 while (pend) {
613 irq = fls(pend) - 1;
614 generic_handle_domain_irq(domain, irq);
615 pend &= ~(1 << irq);
616 }
617 }
618
619 /* interrupt handler for wakeup interrupt 16 */
exynos_irq_demux_eint16_31(struct irq_desc * desc)620 static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
621 {
622 struct irq_chip *chip = irq_desc_get_chip(desc);
623 struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc);
624 unsigned int pend;
625 unsigned int mask;
626 int i;
627
628 chained_irq_enter(chip, desc);
629
630 /*
631 * just enable the clock once here, to avoid an enable/disable dance for
632 * each bank.
633 */
634 if (eintd->nr_banks) {
635 struct samsung_pin_bank *b = eintd->banks[0];
636
637 if (clk_enable(b->drvdata->pclk)) {
638 dev_err(b->gpio_chip.parent,
639 "unable to enable clock for pending IRQs\n");
640 goto out;
641 }
642 }
643
644 for (i = 0; i < eintd->nr_banks; ++i) {
645 struct samsung_pin_bank *b = eintd->banks[i];
646 pend = readl(b->eint_base + b->irq_chip->eint_pend
647 + b->eint_offset);
648 mask = readl(b->eint_base + b->irq_chip->eint_mask
649 + b->eint_offset);
650 exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
651 }
652
653 if (eintd->nr_banks)
654 clk_disable(eintd->banks[0]->drvdata->pclk);
655
656 out:
657 chained_irq_exit(chip, desc);
658 }
659
660 /*
661 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
662 * @d: driver data of samsung pinctrl driver.
663 */
exynos_eint_wkup_init(struct samsung_pinctrl_drv_data * d)664 __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
665 {
666 struct device *dev = d->dev;
667 struct device_node *wkup_np __free(device_node) = NULL;
668 struct device_node *np;
669 struct samsung_pin_bank *bank;
670 struct exynos_weint_data *weint_data;
671 struct exynos_muxed_weint_data *muxed_data;
672 const struct exynos_irq_chip *irq_chip;
673 unsigned int muxed_banks = 0;
674 unsigned int i;
675 int idx, irq;
676
677 for_each_child_of_node(dev->of_node, np) {
678 const struct of_device_id *match;
679
680 match = of_match_node(exynos_wkup_irq_ids, np);
681 if (match) {
682 irq_chip = match->data;
683 wkup_np = np;
684 break;
685 }
686 }
687 if (!wkup_np)
688 return -ENODEV;
689
690 bank = d->pin_banks;
691 for (i = 0; i < d->nr_banks; ++i, ++bank) {
692 if (bank->eint_type != EINT_TYPE_WKUP)
693 continue;
694
695 bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),
696 GFP_KERNEL);
697 if (!bank->irq_chip)
698 return -ENOMEM;
699 bank->irq_chip->chip.name = bank->name;
700
701 bank->irq_domain = irq_domain_create_linear(bank->fwnode,
702 bank->nr_pins, &exynos_eint_irqd_ops, bank);
703 if (!bank->irq_domain) {
704 dev_err(dev, "wkup irq domain add failed\n");
705 return -ENXIO;
706 }
707
708 if (!fwnode_property_present(bank->fwnode, "interrupts")) {
709 bank->eint_type = EINT_TYPE_WKUP_MUX;
710 ++muxed_banks;
711 continue;
712 }
713
714 weint_data = devm_kcalloc(dev,
715 bank->nr_pins, sizeof(*weint_data),
716 GFP_KERNEL);
717 if (!weint_data)
718 return -ENOMEM;
719
720 for (idx = 0; idx < bank->nr_pins; ++idx) {
721 irq = irq_of_parse_and_map(to_of_node(bank->fwnode), idx);
722 if (!irq) {
723 dev_err(dev, "irq number for eint-%s-%d not found\n",
724 bank->name, idx);
725 continue;
726 }
727 weint_data[idx].irq = idx;
728 weint_data[idx].bank = bank;
729 irq_set_chained_handler_and_data(irq,
730 exynos_irq_eint0_15,
731 &weint_data[idx]);
732 }
733 }
734
735 if (!muxed_banks)
736 return 0;
737
738 irq = irq_of_parse_and_map(wkup_np, 0);
739 if (!irq) {
740 dev_err(dev, "irq number for muxed EINTs not found\n");
741 return 0;
742 }
743
744 muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
745 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
746 if (!muxed_data)
747 return -ENOMEM;
748 muxed_data->nr_banks = muxed_banks;
749
750 irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31,
751 muxed_data);
752
753 bank = d->pin_banks;
754 idx = 0;
755 for (i = 0; i < d->nr_banks; ++i, ++bank) {
756 if (bank->eint_type != EINT_TYPE_WKUP_MUX)
757 continue;
758
759 muxed_data->banks[idx++] = bank;
760 }
761
762 return 0;
763 }
764
exynos_pinctrl_suspend_bank(struct samsung_pinctrl_drv_data * drvdata,struct samsung_pin_bank * bank)765 static void exynos_pinctrl_suspend_bank(
766 struct samsung_pinctrl_drv_data *drvdata,
767 struct samsung_pin_bank *bank)
768 {
769 struct exynos_eint_gpio_save *save = bank->soc_priv;
770 const void __iomem *regs = bank->eint_base;
771
772 if (clk_enable(bank->drvdata->pclk)) {
773 dev_err(bank->gpio_chip.parent,
774 "unable to enable clock for saving state\n");
775 return;
776 }
777
778 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
779 + bank->eint_offset);
780 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
781 + 2 * bank->eint_offset);
782 save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
783 + 2 * bank->eint_offset + 4);
784 save->eint_mask = readl(regs + bank->irq_chip->eint_mask
785 + bank->eint_offset);
786
787 clk_disable(bank->drvdata->pclk);
788
789 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
790 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
791 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
792 pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
793 }
794
exynosauto_pinctrl_suspend_bank(struct samsung_pinctrl_drv_data * drvdata,struct samsung_pin_bank * bank)795 static void exynosauto_pinctrl_suspend_bank(struct samsung_pinctrl_drv_data *drvdata,
796 struct samsung_pin_bank *bank)
797 {
798 struct exynos_eint_gpio_save *save = bank->soc_priv;
799 const void __iomem *regs = bank->eint_base;
800
801 if (clk_enable(bank->drvdata->pclk)) {
802 dev_err(bank->gpio_chip.parent,
803 "unable to enable clock for saving state\n");
804 return;
805 }
806
807 save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset);
808 save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset);
809
810 clk_disable(bank->drvdata->pclk);
811
812 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
813 pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
814 }
815
exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data * drvdata)816 void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
817 {
818 struct samsung_pin_bank *bank = drvdata->pin_banks;
819 struct exynos_irq_chip *irq_chip = NULL;
820 int i;
821
822 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) {
823 if (bank->eint_type == EINT_TYPE_GPIO) {
824 if (bank->eint_con_offset)
825 exynosauto_pinctrl_suspend_bank(drvdata, bank);
826 else
827 exynos_pinctrl_suspend_bank(drvdata, bank);
828 }
829 else if (bank->eint_type == EINT_TYPE_WKUP) {
830 if (!irq_chip) {
831 irq_chip = bank->irq_chip;
832 irq_chip->set_eint_wakeup_mask(drvdata,
833 irq_chip);
834 }
835 }
836 }
837 }
838
exynos_pinctrl_resume_bank(struct samsung_pinctrl_drv_data * drvdata,struct samsung_pin_bank * bank)839 static void exynos_pinctrl_resume_bank(
840 struct samsung_pinctrl_drv_data *drvdata,
841 struct samsung_pin_bank *bank)
842 {
843 struct exynos_eint_gpio_save *save = bank->soc_priv;
844 void __iomem *regs = bank->eint_base;
845
846 if (clk_enable(bank->drvdata->pclk)) {
847 dev_err(bank->gpio_chip.parent,
848 "unable to enable clock for restoring state\n");
849 return;
850 }
851
852 pr_debug("%s: con %#010x => %#010x\n", bank->name,
853 readl(regs + EXYNOS_GPIO_ECON_OFFSET
854 + bank->eint_offset), save->eint_con);
855 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
856 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
857 + 2 * bank->eint_offset), save->eint_fltcon0);
858 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
859 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
860 + 2 * bank->eint_offset + 4), save->eint_fltcon1);
861 pr_debug("%s: mask %#010x => %#010x\n", bank->name,
862 readl(regs + bank->irq_chip->eint_mask
863 + bank->eint_offset), save->eint_mask);
864
865 writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
866 + bank->eint_offset);
867 writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
868 + 2 * bank->eint_offset);
869 writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
870 + 2 * bank->eint_offset + 4);
871 writel(save->eint_mask, regs + bank->irq_chip->eint_mask
872 + bank->eint_offset);
873
874 clk_disable(bank->drvdata->pclk);
875 }
876
exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data * drvdata,struct samsung_pin_bank * bank)877 static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvdata,
878 struct samsung_pin_bank *bank)
879 {
880 struct exynos_eint_gpio_save *save = bank->soc_priv;
881 void __iomem *regs = bank->eint_base;
882
883 if (clk_enable(bank->drvdata->pclk)) {
884 dev_err(bank->gpio_chip.parent,
885 "unable to enable clock for restoring state\n");
886 return;
887 }
888
889 pr_debug("%s: con %#010x => %#010x\n", bank->name,
890 readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con);
891 pr_debug("%s: mask %#010x => %#010x\n", bank->name,
892 readl(regs + bank->pctl_offset + bank->eint_mask_offset), save->eint_mask);
893
894 writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset);
895 writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset);
896
897 clk_disable(bank->drvdata->pclk);
898 }
899
exynos_pinctrl_resume(struct samsung_pinctrl_drv_data * drvdata)900 void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
901 {
902 struct samsung_pin_bank *bank = drvdata->pin_banks;
903 int i;
904
905 for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
906 if (bank->eint_type == EINT_TYPE_GPIO) {
907 if (bank->eint_con_offset)
908 exynosauto_pinctrl_resume_bank(drvdata, bank);
909 else
910 exynos_pinctrl_resume_bank(drvdata, bank);
911 }
912 }
913
exynos_retention_enable(struct samsung_pinctrl_drv_data * drvdata)914 static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata)
915 {
916 if (drvdata->retention_ctrl->refcnt)
917 atomic_inc(drvdata->retention_ctrl->refcnt);
918 }
919
exynos_retention_disable(struct samsung_pinctrl_drv_data * drvdata)920 static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
921 {
922 struct samsung_retention_ctrl *ctrl = drvdata->retention_ctrl;
923 struct regmap *pmu_regs = ctrl->priv;
924 int i;
925
926 if (ctrl->refcnt && !atomic_dec_and_test(ctrl->refcnt))
927 return;
928
929 for (i = 0; i < ctrl->nr_regs; i++)
930 regmap_write(pmu_regs, ctrl->regs[i], ctrl->value);
931 }
932
933 struct samsung_retention_ctrl *
exynos_retention_init(struct samsung_pinctrl_drv_data * drvdata,const struct samsung_retention_data * data)934 exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata,
935 const struct samsung_retention_data *data)
936 {
937 struct samsung_retention_ctrl *ctrl;
938 struct regmap *pmu_regs;
939 int i;
940
941 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL);
942 if (!ctrl)
943 return ERR_PTR(-ENOMEM);
944
945 pmu_regs = exynos_get_pmu_regmap();
946 if (IS_ERR(pmu_regs))
947 return ERR_CAST(pmu_regs);
948
949 ctrl->priv = pmu_regs;
950 ctrl->regs = data->regs;
951 ctrl->nr_regs = data->nr_regs;
952 ctrl->value = data->value;
953 ctrl->refcnt = data->refcnt;
954 ctrl->enable = exynos_retention_enable;
955 ctrl->disable = exynos_retention_disable;
956
957 /* Ensure that retention is disabled on driver init */
958 for (i = 0; i < ctrl->nr_regs; i++)
959 regmap_write(pmu_regs, ctrl->regs[i], ctrl->value);
960
961 return ctrl;
962 }
963