Lines Matching full:bank
26 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) argument
27 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) argument
28 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) argument
29 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) argument
30 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) argument
31 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) argument
32 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) argument
33 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) argument
34 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) argument
65 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_gc_to_priv() local
66 return bank->parent_priv; in brcmstb_gpio_gc_to_priv()
70 __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank) in __brcmstb_gpio_get_active_irqs() argument
72 void __iomem *reg_base = bank->parent_priv->reg_base; in __brcmstb_gpio_get_active_irqs()
74 return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) & in __brcmstb_gpio_get_active_irqs()
75 bank->gc.read_reg(reg_base + GIO_MASK(bank->id)); in __brcmstb_gpio_get_active_irqs()
79 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank) in brcmstb_gpio_get_active_irqs() argument
84 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_get_active_irqs()
85 status = __brcmstb_gpio_get_active_irqs(bank); in brcmstb_gpio_get_active_irqs()
86 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_get_active_irqs()
92 struct brcmstb_gpio_bank *bank) in brcmstb_gpio_hwirq_to_offset() argument
94 return hwirq - bank->gc.offset; in brcmstb_gpio_hwirq_to_offset()
97 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, in brcmstb_gpio_set_imask() argument
100 struct gpio_chip *gc = &bank->gc; in brcmstb_gpio_set_imask()
101 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_set_imask()
102 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank)); in brcmstb_gpio_set_imask()
107 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id)); in brcmstb_gpio_set_imask()
112 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask); in brcmstb_gpio_set_imask()
132 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_mask() local
134 brcmstb_gpio_set_imask(bank, d->hwirq, false); in brcmstb_gpio_irq_mask()
140 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_unmask() local
142 brcmstb_gpio_set_imask(bank, d->hwirq, true); in brcmstb_gpio_irq_unmask()
148 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_ack() local
149 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_irq_ack()
150 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); in brcmstb_gpio_irq_ack()
152 gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask); in brcmstb_gpio_irq_ack()
158 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_set_type() local
159 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_irq_set_type()
160 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); in brcmstb_gpio_irq_set_type()
196 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_irq_set_type()
198 iedge_config = bank->gc.read_reg(priv->reg_base + in brcmstb_gpio_irq_set_type()
199 GIO_EC(bank->id)) & ~mask; in brcmstb_gpio_irq_set_type()
200 iedge_insensitive = bank->gc.read_reg(priv->reg_base + in brcmstb_gpio_irq_set_type()
201 GIO_EI(bank->id)) & ~mask; in brcmstb_gpio_irq_set_type()
202 ilevel = bank->gc.read_reg(priv->reg_base + in brcmstb_gpio_irq_set_type()
203 GIO_LEVEL(bank->id)) & ~mask; in brcmstb_gpio_irq_set_type()
205 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id), in brcmstb_gpio_irq_set_type()
207 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id), in brcmstb_gpio_irq_set_type()
209 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id), in brcmstb_gpio_irq_set_type()
212 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_irq_set_type()
234 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_set_wake() local
235 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_irq_set_wake()
236 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); in brcmstb_gpio_irq_set_wake()
243 bank->wake_active |= mask; in brcmstb_gpio_irq_set_wake()
245 bank->wake_active &= ~mask; in brcmstb_gpio_irq_set_wake()
261 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank) in brcmstb_gpio_irq_bank_handler() argument
263 struct brcmstb_gpio_priv *priv = bank->parent_priv; in brcmstb_gpio_irq_bank_handler()
265 int hwbase = bank->gc.offset; in brcmstb_gpio_irq_bank_handler()
268 while ((status = brcmstb_gpio_get_active_irqs(bank))) { in brcmstb_gpio_irq_bank_handler()
272 if (offset >= bank->width) in brcmstb_gpio_irq_bank_handler()
274 "IRQ for invalid GPIO (bank=%d, offset=%d)\n", in brcmstb_gpio_irq_bank_handler()
275 bank->id, offset); in brcmstb_gpio_irq_bank_handler()
286 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_irq_handler() local
292 list_for_each_entry(bank, &priv->bank_list, node) in brcmstb_gpio_irq_handler()
293 brcmstb_gpio_irq_bank_handler(bank); in brcmstb_gpio_irq_handler()
300 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_hwirq_to_bank() local
304 list_for_each_entry_reverse(bank, &priv->bank_list, node) { in brcmstb_gpio_hwirq_to_bank()
305 i += bank->gc.ngpio; in brcmstb_gpio_hwirq_to_bank()
307 return bank; in brcmstb_gpio_hwirq_to_bank()
324 struct brcmstb_gpio_bank *bank = in brcmstb_gpio_irq_map() local
329 if (!bank) in brcmstb_gpio_irq_map()
332 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n", in brcmstb_gpio_irq_map()
333 irq, (int)hwirq, bank->id); in brcmstb_gpio_irq_map()
334 ret = irq_set_chip_data(irq, &bank->gc); in brcmstb_gpio_irq_map()
362 of_property_count_u32_elems(np, "brcm,gpio-bank-widths"); in brcmstb_gpio_sanity_check_banks()
365 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n", in brcmstb_gpio_sanity_check_banks()
376 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_remove() local
395 list_for_each_entry(bank, &priv->bank_list, node) in brcmstb_gpio_remove()
396 gpiochip_remove(&bank->gc); in brcmstb_gpio_remove()
403 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_of_xlate() local
414 offset = gpiospec->args[0] - bank->gc.offset; in brcmstb_gpio_of_xlate()
418 if (unlikely(offset >= bank->width)) { in brcmstb_gpio_of_xlate()
495 struct brcmstb_gpio_bank *bank) in brcmstb_gpio_bank_save() argument
497 struct gpio_chip *gc = &bank->gc; in brcmstb_gpio_bank_save()
501 bank->saved_regs[i] = gc->read_reg(priv->reg_base + in brcmstb_gpio_bank_save()
502 GIO_BANK_OFF(bank->id, i)); in brcmstb_gpio_bank_save()
508 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_quiesce() local
516 list_for_each_entry(bank, &priv->bank_list, node) { in brcmstb_gpio_quiesce()
517 gc = &bank->gc; in brcmstb_gpio_quiesce()
520 brcmstb_gpio_bank_save(priv, bank); in brcmstb_gpio_quiesce()
524 imask = bank->wake_active; in brcmstb_gpio_quiesce()
527 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), in brcmstb_gpio_quiesce()
540 struct brcmstb_gpio_bank *bank) in brcmstb_gpio_bank_restore() argument
542 struct gpio_chip *gc = &bank->gc; in brcmstb_gpio_bank_restore()
546 gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i), in brcmstb_gpio_bank_restore()
547 bank->saved_regs[i]); in brcmstb_gpio_bank_restore()
559 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_resume() local
562 list_for_each_entry(bank, &priv->bank_list, node) { in brcmstb_gpio_resume()
563 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank); in brcmstb_gpio_resume()
564 brcmstb_gpio_bank_restore(priv, bank); in brcmstb_gpio_resume()
637 of_property_for_each_u32(np, "brcm,gpio-bank-widths", bank_width) { in brcmstb_gpio_probe()
638 struct brcmstb_gpio_bank *bank; in brcmstb_gpio_probe() local
642 * If bank_width is 0, then there is an empty bank in the in brcmstb_gpio_probe()
646 dev_dbg(dev, "Width 0 found: Empty bank @ %d\n", in brcmstb_gpio_probe()
653 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); in brcmstb_gpio_probe()
654 if (!bank) { in brcmstb_gpio_probe()
659 bank->parent_priv = priv; in brcmstb_gpio_probe()
660 bank->id = num_banks; in brcmstb_gpio_probe()
662 dev_err(dev, "Invalid bank width %d\n", bank_width); in brcmstb_gpio_probe()
666 bank->width = bank_width; in brcmstb_gpio_probe()
673 gc = &bank->gc; in brcmstb_gpio_probe()
675 reg_base + GIO_DATA(bank->id), in brcmstb_gpio_probe()
677 reg_base + GIO_IODIR(bank->id), flags); in brcmstb_gpio_probe()
691 /* not all ngpio lines are valid, will use bank width later */ in brcmstb_gpio_probe()
693 gc->offset = bank->id * MAX_GPIO_PER_BANK; in brcmstb_gpio_probe()
703 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank); in brcmstb_gpio_probe()
704 gc->write_reg(reg_base + GIO_MASK(bank->id), 0); in brcmstb_gpio_probe()
706 err = gpiochip_add_data(gc, bank); in brcmstb_gpio_probe()
708 dev_err(dev, "Could not add gpiochip for bank %d\n", in brcmstb_gpio_probe()
709 bank->id); in brcmstb_gpio_probe()
714 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id, in brcmstb_gpio_probe()
715 gc->base, gc->ngpio, bank->width); in brcmstb_gpio_probe()
717 /* Everything looks good, so add bank to list */ in brcmstb_gpio_probe()
718 list_add(&bank->node, &priv->bank_list); in brcmstb_gpio_probe()