| /nrf52832-nimble/nordic/nrfx/mdk/ |
| H A D | nrf9160_bitfields.h | 44 /* Bit 0 : Start HFCLK crystal oscillator */
46 …HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLK…
52 /* Bit 0 : Stop HFCLK crystal oscillator */
54 …KS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLK…
60 /* Bit 0 : Start LFCLK source */
62 …LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLK…
68 /* Bit 0 : Stop LFCLK source */
70 …KS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLK…
76 /* Bit 31 : */
78 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos) /*!< Bit mas…
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| H A D | nrf52840_bitfields.h | 44 /* Bit 0 : */
46 #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of…
51 /* Bit 0 : */
53 #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TAS…
58 /* Bit 0 : */
60 #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVE…
65 /* Bit 0 : */
67 …VENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESO…
72 /* Bit 0 : */
74 …RESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTR…
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| H A D | nrf52810_bitfields.h | 44 /* Bit 0 : */
46 #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of…
51 /* Bit 0 : */
53 #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TAS…
58 /* Bit 0 : */
60 #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVE…
65 /* Bit 0 : */
67 …VENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESO…
72 /* Bit 0 : */
74 …RESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTR…
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| H A D | nrf52_bitfields.h | 44 /* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
46 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRE…
51 /* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */
53 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED fi…
58 /* Bit 0 : Write '1' to Enable interrupt for END event */
60 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
68 /* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
70 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRE…
75 /* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */
77 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED fi…
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| H A D | nrf51_bitfields.h | 44 /* Bit 2 : Enable interrupt on NOTRESOLVED event. */
46 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRE…
51 /* Bit 1 : Enable interrupt on RESOLVED event. */
53 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED fi…
58 /* Bit 0 : Enable interrupt on END event. */
60 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
68 /* Bit 2 : Disable interrupt on NOTRESOLVED event. */
70 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRE…
75 /* Bit 1 : Disable interrupt on RESOLVED event. */
77 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED fi…
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| /nrf52832-nimble/nordic/nrfx/drivers/include/ |
| H A D | nrf_bitmask.h | 52 * Function for checking if bit in the multi-byte bit mask is set.
54 * @param bit Bit index.
55 * @param p_mask A pointer to mask with bit fields.
57 * @return 0 if bit is not set, positive value otherwise.
59 __STATIC_INLINE uint32_t nrf_bitmask_bit_is_set(uint32_t bit, void const * p_mask) in nrf_bitmask_bit_is_set() argument
62 uint32_t byte_idx = BITMASK_BYTE_GET(bit); in nrf_bitmask_bit_is_set()
63 bit = BITMASK_RELBIT_GET(bit); in nrf_bitmask_bit_is_set()
64 return (1 << bit) & p_mask8[byte_idx]; in nrf_bitmask_bit_is_set()
68 * Function for setting a bit in the multi-byte bit mask.
70 * @param bit Bit index.
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| /nrf52832-nimble/packages/NimBLE-latest/nimble/host/mesh/src/ |
| H A D | atomic.h | 254 #define ATOMIC_MASK(bit) (1 << ((bit) & (ATOMIC_BITS - 1))) argument
255 #define ATOMIC_ELEM(addr, bit) ((addr) + ((bit) / ATOMIC_BITS)) argument
278 * @brief Atomically test a bit.
280 * This routine tests whether bit number @a bit of @a target is set or not.
284 * @param bit Bit number (starting from 0).
286 * @return 1 if the bit was set, 0 if it wasn't.
289 atomic_test_bit(const atomic_t *target, int bit) in atomic_test_bit() argument
291 atomic_val_t val = atomic_get(ATOMIC_ELEM(target, bit)); in atomic_test_bit()
293 return (1 & (val >> (bit & (ATOMIC_BITS - 1)))); in atomic_test_bit()
297 * @brief Atomically test and clear a bit.
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| /nrf52832-nimble/rt-thread/libcpu/c-sky/common/ |
| H A D | csi_simd.h | 32 \param [in] val1 first 16-bit operands
33 \param [in] val2 second 16-bit operands
50 \param [in] val1 first 16-bit operands
51 \param [in] val2 second 16-bit operands
64 \brief Dual 16-bit signed saturate.
66 \param [in] x two signed 16-bit values to be saturated.
67 …\param [in] y bit position for saturation, an integral constant expression in the range 1 to …
69 … the signed saturation of the low halfword in val1, saturated to the bit position specified in
71 … the signed saturation of the high halfword in val1, saturated to the bit position specified in
85 \brief Dual 16-bit unsigned saturate.
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| H A D | csi_instr.h | 112 \brief Reverse byte order (32 bit)
124 \brief Reverse byte order (16 bit)
155 \brief Rotate Right in unsigned value (32 bit)
178 \brief Reverse bit order of value
179 \details Reverses the bit order of the given value.
217 \param [in] y Bit position to saturate to [1..32]
262 \param [in] sat Bit position to saturate to (0..31)
285 \param [in] sat Bit position to saturate to (0..31)
292 if (value & 0x80000000) /* only overflow set bit-31 */ in __IUSAT()
310 \details This function moves each bit of a bitstring right by one bit.
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| /nrf52832-nimble/packages/NimBLE-latest/nimble/host/mesh/include/mesh/ |
| H A D | main.h | 22 BT_MESH_BLINK = BIT(0),
23 BT_MESH_BEEP = BIT(1),
24 BT_MESH_VIBRATE = BIT(2),
25 BT_MESH_DISPLAY_NUMBER = BIT(3),
26 BT_MESH_DISPLAY_STRING = BIT(4),
31 BT_MESH_PUSH = BIT(0),
32 BT_MESH_TWIST = BIT(1),
33 BT_MESH_ENTER_NUMBER = BIT(2),
34 BT_MESH_ENTER_STRING = BIT(3),
38 BT_MESH_PROV_ADV = BIT(0),
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| /nrf52832-nimble/rt-thread/libcpu/c-sky/ck802/ |
| H A D | core_ck802.h | 156 uint32_t C: 1; /*!< bit: 0 �����룯��λλ */
157 uint32_t _reserved0: 5; /*!< bit: 2.. 5 ���� */
158 uint32_t IE: 1; /*!< bit: 6 �ж���Ч����λ */
159 uint32_t IC: 1; /*!< bit: 7 �жϿ���λ */
160 uint32_t EE: 1; /*!< bit: 8 �쳣��Ч����λ */
161 uint32_t MM: 1; /*!< bit: 9 �������쳣�ڸ�λ */
162 uint32_t _reserved1: 6; /*!< bit: 10..15 ���� */
163 uint32_t VEC: 8; /*!< bit: 16..23 �쳣�¼�����ֵ */
164 uint32_t _reserved2: 7; /*!< bit: 24..30 ���� */
165 uint32_t S: 1; /*!< bit: 31 �����û�ģʽ����λ */
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| /nrf52832-nimble/rt-thread/components/drivers/include/drivers/ |
| H A D | mmc.h | 128 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
129 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
130 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
131 #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
132 #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
139 #define EXT_CSD_SEC_ER_EN BIT(0)
140 #define EXT_CSD_SEC_BD_BLK_EN BIT(2)
141 #define EXT_CSD_SEC_GB_CL_EN BIT(4)
142 #define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */
152 #define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */
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| /nrf52832-nimble/rt-thread/components/CMSIS/Include/ |
| H A D | core_cmInstr.h | 111 /** \brief Reverse byte order (32 bit)
121 /** \brief Reverse byte order (16 bit)
152 /** \brief Rotate Right in unsigned value (32 bit)
176 /** \brief Reverse bit order of value
178 This function reverses the bit order of the given value.
186 /** \brief LDR Exclusive (8 bit)
188 This function performs a exclusive LDR command for 8 bit value.
196 /** \brief LDR Exclusive (16 bit)
198 This function performs a exclusive LDR command for 16 bit values.
206 /** \brief LDR Exclusive (32 bit)
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| /nrf52832-nimble/nordic/cmsis/include/ |
| H A D | cmsis_armcc.h | 162 \details Returns the current state of the priority mask bit from the Priority Mask Register.
188 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
196 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
373 \brief Reverse byte order (32 bit)
382 \brief Reverse byte order (16 bit)
411 \brief Rotate Right in unsigned value (32 bit)
431 \brief Reverse bit order of value
432 \details Reverses the bit order of the given value.
469 \brief LDR Exclusive (8 bit)
470 \details Executes a exclusive LDR instruction for 8 bit value.
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| H A D | cmsis_armcc_V6.h | 47 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
58 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
321 \details Returns the current state of the priority mask bit from the Priority Mask Register.
336 …\details Returns the current state of the non-secure priority mask bit from the Priority Mask Regi…
377 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
388 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
803 \brief Reverse byte order (32 bit)
812 \brief Reverse byte order (16 bit)
846 \brief Rotate Right in unsigned value (32 bit)
869 \brief Reverse bit order of value
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| /nrf52832-nimble/rt-thread/libcpu/risc-v/common/ |
| H A D | riscv-ops.h | 26 #define set_csr(reg, bit) ({ unsigned long __tmp; \ argument
27 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
28 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
30 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
33 #define clear_csr(reg, bit) ({ unsigned long __tmp; \ argument
34 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
35 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
37 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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| /nrf52832-nimble/rt-thread/examples/test/ |
| H A D | mem_test.c | 14 /**< 8bit test */ in mem_test()
27 printf("8bit test fail @ 0x%08X\r\nsystem halt!!!!!",(uint32_t)p_uint8_t); in mem_test()
32 printf("8bit test pass!!\r\n"); in mem_test()
35 /**< 16bit test */ in mem_test()
48 printf("16bit test fail @ 0x%08X\r\nsystem halt!!!!!",(uint32_t)p_uint16_t); in mem_test()
53 printf("16bit test pass!!\r\n"); in mem_test()
56 /**< 32bit test */ in mem_test()
69 printf("32bit test fail @ 0x%08X\r\nsystem halt!!!!!",(uint32_t)p_uint32_t); in mem_test()
74 printf("32bit test pass!!\r\n"); in mem_test()
77 /**< 32bit Loopback test */ in mem_test()
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| /nrf52832-nimble/rt-thread/libcpu/arm/armv6/ |
| H A D | cpuport.c | 29 rt_inline void cache_enable(rt_uint32_t bit) in cache_enable() argument
36 :"r" (bit) \ in cache_enable()
40 rt_inline void cache_disable(rt_uint32_t bit) in cache_disable() argument
47 :"r" (bit) \ in cache_disable()
67 rt_inline void cache_enable(rt_uint32_t bit) in cache_enable() argument
74 orr value, value, bit in cache_enable()
79 rt_inline void cache_disable(rt_uint32_t bit) in cache_disable() argument
86 bic value, value, bit in cache_disable()
180 * This function finds the first bit set (beginning with the least significant bit)
181 * in value and return the index of that bit.
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| /nrf52832-nimble/rt-thread/libcpu/arm/dm36x/ |
| H A D | cpuport.c | 29 rt_inline void cache_enable(rt_uint32_t bit) in cache_enable() argument
36 :"r" (bit) \ in cache_enable()
40 rt_inline void cache_disable(rt_uint32_t bit) in cache_disable() argument
47 :"r" (bit) \ in cache_disable()
65 rt_inline void cache_enable(rt_uint32_t bit) in cache_enable() argument
72 orr value, value, bit in cache_enable()
77 rt_inline void cache_disable(rt_uint32_t bit) in cache_disable() argument
84 bic value, value, bit in cache_disable()
178 * This function finds the first bit set (beginning with the least significant bit)
179 * in value and return the index of that bit.
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| /nrf52832-nimble/rt-thread/libcpu/arm/arm926/ |
| H A D | cpuport.c | 30 rt_inline void cache_enable(rt_uint32_t bit) in cache_enable() argument
37 :"r" (bit) \ in cache_enable()
41 rt_inline void cache_disable(rt_uint32_t bit) in cache_disable() argument
48 :"r" (bit) \ in cache_disable()
66 rt_inline void cache_enable(rt_uint32_t bit) in cache_enable() argument
73 orr value, value, bit in cache_enable()
78 rt_inline void cache_disable(rt_uint32_t bit) in cache_disable() argument
85 bic value, value, bit in cache_disable()
179 * This function finds the first bit set (beginning with the least significant bit)
180 * in value and return the index of that bit.
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| /nrf52832-nimble/rt-thread/components/net/freemodbus/modbus/include/ |
| H A D | mbutils.h | 53 * \param ucByteBuf A buffer where the bit values are stored. Must be a
58 * bit has the offset 0.
61 * \param ucValues Thew new values for the bits. The value for the first bit
68 * // Set bit 4 to 1 (read: set 1 bit starting at bit offset 4 to value 1)
71 * // Set bit 7 to 1 and bit 8 to 0.
83 * This function is used to extract up bit values from an array. Up to eight
84 * bit values can be extracted in one step.
86 * \param ucByteBuf A buffer where the bit values are stored.
88 * bit has the offset 0.
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| /nrf52832-nimble/rt-thread/components/net/lwip-2.1.0/src/include/netif/ppp/ |
| H A D | mppe.h | 49 #define MPPE_MAX_KEY_LEN 16 /* largest key length (128-bit) */
52 #define MPPE_OPT_40 0x01 /* 40 bit */
53 #define MPPE_OPT_128 0x02 /* 128 bit */
56 #define MPPE_OPT_56 0x08 /* 56 bit */
65 * names above since C and H are the same bit. We could do a u_int32
71 #define MPPE_L_BIT 0x20 /* 40-bit */
72 #define MPPE_S_BIT 0x40 /* 128-bit */
73 #define MPPE_M_BIT 0x80 /* 56-bit, not supported */
76 /* Does not include H bit; used for least significant octet only. */
84 /* H bit */ \
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| /nrf52832-nimble/rt-thread/components/net/lwip-2.0.2/src/include/netif/ppp/ |
| H A D | mppe.h | 45 #define MPPE_MAX_KEY_LEN 16 /* largest key length (128-bit) */
48 #define MPPE_OPT_40 0x01 /* 40 bit */
49 #define MPPE_OPT_128 0x02 /* 128 bit */
52 #define MPPE_OPT_56 0x08 /* 56 bit */
61 * names above since C and H are the same bit. We could do a u_int32
67 #define MPPE_L_BIT 0x20 /* 40-bit */
68 #define MPPE_S_BIT 0x40 /* 128-bit */
69 #define MPPE_M_BIT 0x80 /* 56-bit, not supported */
72 /* Does not include H bit; used for least significant octet only. */
80 /* H bit */ \
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| /nrf52832-nimble/rt-thread/components/drivers/spi/ |
| H A D | enc28j60.h | 23 // - MAC/PHY indicator (bit 7)
131 // ENC28J60 ERXFCON Register Bit Definitions
140 // ENC28J60 EIE Register Bit Definitions
149 // ENC28J60 EIR Register Bit Definitions
157 // ENC28J60 ESTAT Register Bit Definitions
163 // ENC28J60 ECON2 Register Bit Definitions
168 // ENC28J60 ECON1 Register Bit Definitions
177 // ENC28J60 MACON1 Register Bit Definitions
183 // ENC28J60 MACON2 Register Bit Definitions
190 // ENC28J60 MACON3 Register Bit Definitions
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| /nrf52832-nimble/rt-thread/libcpu/arm/am335x/ |
| H A D | cpu.c | 36 rt_inline void cache_enable(rt_uint32_t bit) in cache_enable() argument
43 orr value, value, bit in cache_enable()
48 rt_inline void cache_disable(rt_uint32_t bit) in cache_disable() argument
55 bic value, value, bit in cache_disable()
68 rt_inline void cache_enable(rt_uint32_t bit) in cache_enable() argument
75 :"r" (bit) \ in cache_enable()
79 rt_inline void cache_disable(rt_uint32_t bit) in cache_disable() argument
86 :"r" (bit) \ in cache_disable()
|