1*10465441SEvalZero /* 2*10465441SEvalZero * Copyright (c) 2006-2018, RT-Thread Development Team 3*10465441SEvalZero * 4*10465441SEvalZero * SPDX-License-Identifier: Apache-2.0 5*10465441SEvalZero * 6*10465441SEvalZero * Change Logs: 7*10465441SEvalZero * Date Author Notes 8*10465441SEvalZero * 2018-10-03 Bernard The first version 9*10465441SEvalZero */ 10*10465441SEvalZero 11*10465441SEvalZero #ifndef RISCV_OPS_H__ 12*10465441SEvalZero #define RISCV_OPS_H__ 13*10465441SEvalZero 14*10465441SEvalZero #if defined(__GNUC__) && !defined(__ASSEMBLER__) 15*10465441SEvalZero 16*10465441SEvalZero #define read_csr(reg) ({ unsigned long __tmp; \ 17*10465441SEvalZero asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 18*10465441SEvalZero __tmp; }) 19*10465441SEvalZero 20*10465441SEvalZero #define write_csr(reg, val) ({ \ 21*10465441SEvalZero if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 22*10465441SEvalZero asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ 23*10465441SEvalZero else \ 24*10465441SEvalZero asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) 25*10465441SEvalZero 26*10465441SEvalZero #define set_csr(reg, bit) ({ unsigned long __tmp; \ 27*10465441SEvalZero if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 28*10465441SEvalZero asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ 29*10465441SEvalZero else \ 30*10465441SEvalZero asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ 31*10465441SEvalZero __tmp; }) 32*10465441SEvalZero 33*10465441SEvalZero #define clear_csr(reg, bit) ({ unsigned long __tmp; \ 34*10465441SEvalZero if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 35*10465441SEvalZero asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ 36*10465441SEvalZero else \ 37*10465441SEvalZero asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ 38*10465441SEvalZero __tmp; }) 39*10465441SEvalZero #endif /* end of __GNUC__ */ 40*10465441SEvalZero 41*10465441SEvalZero #endif 42