1 /* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-10-03 Bernard The first version 9 */ 10 11 #ifndef RISCV_OPS_H__ 12 #define RISCV_OPS_H__ 13 14 #if defined(__GNUC__) && !defined(__ASSEMBLER__) 15 16 #define read_csr(reg) ({ unsigned long __tmp; \ 17 asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 18 __tmp; }) 19 20 #define write_csr(reg, val) ({ \ 21 if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 22 asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ 23 else \ 24 asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) 25 26 #define set_csr(reg, bit) ({ unsigned long __tmp; \ 27 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 28 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ 29 else \ 30 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ 31 __tmp; }) 32 33 #define clear_csr(reg, bit) ({ unsigned long __tmp; \ 34 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 35 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ 36 else \ 37 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ 38 __tmp; }) 39 #endif /* end of __GNUC__ */ 40 41 #endif 42