1 /* 2 * File : core_ck802.h 3 * This file is part of RT-Thread RTOS 4 * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Change Logs: 21 * Date Author Notes 22 * 2017-01-01 Urey first version 23 */ 24 25 #ifndef __CORE_CK802_H_GENERIC 26 #define __CORE_CK802_H_GENERIC 27 28 #include <stdint.h> 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /******************************************************************************* 35 * CSI definitions 36 ******************************************************************************/ 37 /** 38 \ingroup Ck802 39 @{ 40 */ 41 42 /* CSI CK802 definitions */ 43 #define __CK802_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */ 44 #define __CK802_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */ 45 #define __CK802_CSI_VERSION ((__CK802_CSI_VERSION_MAIN << 16U) | \ 46 __CK802_CSI_VERSION_SUB ) /*!< CSI HAL version number */ 47 48 #define __CK80X (0x02U) /*!< CK80X Core */ 49 50 /** __FPU_USED indicates whether an FPU is used or not. 51 This core does not support an FPU at all 52 */ 53 #define __FPU_USED 0U 54 55 #if defined ( __GNUC__ ) 56 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 57 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 58 #endif 59 #endif 60 61 #include "csi_gcc.h" 62 63 #ifdef __cplusplus 64 } 65 #endif 66 67 #endif /* __CORE_CK802_H_GENERIC */ 68 69 #ifndef __CSI_GENERIC 70 71 #ifndef __CORE_CK802_H_DEPENDANT 72 #define __CORE_CK802_H_DEPENDANT 73 74 #ifdef __cplusplus 75 extern "C" { 76 #endif 77 78 /* check device defines and use defaults */ 79 //#if defined __CHECK_DEVICE_DEFINES 80 #ifndef __CK802_REV 81 #define __CK802_REV 0x0000U 82 //#warning "__CK802_REV not defined in device header file; using default!" 83 #endif 84 85 #ifndef __NVIC_PRIO_BITS 86 #define __NVIC_PRIO_BITS 2U 87 //#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 88 #endif 89 90 #ifndef __Vendor_SysTickConfig 91 #define __Vendor_SysTickConfig 0U 92 //#warning "__Vendor_SysTickConfig not defined in device header file; using default!" 93 #endif 94 95 #ifndef __GSR_GCR_PRESENT 96 #define __GSR_GCR_PRESENT 0U 97 //#warning "__GSR_GCR_PRESENT not defined in device header file; using default!" 98 #endif 99 100 #ifndef __MGU_PRESENT 101 #define __MGU_PRESENT 0U 102 //#warning "__MGU_PRESENT not defined in device header file; using default!" 103 #endif 104 //#endif 105 106 /* IO definitions (access restrictions to peripheral registers) */ 107 /** 108 \defgroup CSI_glob_defs CSI Global Defines 109 110 <strong>IO Type Qualifiers</strong> are used 111 \li to specify the access to peripheral variables. 112 \li for automatic generation of peripheral register debug information. 113 */ 114 #ifdef __cplusplus 115 #define __I volatile /*!< Defines 'read only' permissions */ 116 #else 117 #define __I volatile const /*!< Defines 'read only' permissions */ 118 #endif 119 #define __O volatile /*!< Defines 'write only' permissions */ 120 #define __IO volatile /*!< Defines 'read / write' permissions */ 121 122 /* following defines should be used for structure members */ 123 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 124 #define __OM volatile /*! Defines 'write only' structure member permissions */ 125 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 126 127 /*@} end of group CK802 */ 128 129 /******************************************************************************* 130 * Register Abstraction 131 Core Register contain: 132 - Core Register 133 - Core NVIC Register 134 - Core SCB Register 135 - Core SysTick Register 136 ******************************************************************************/ 137 /** 138 \defgroup CSI_core_register Defines and Type Definitions 139 \brief Type definitions and defines for CK80X processor based devices. 140 */ 141 142 /** 143 \ingroup CSI_core_register 144 \defgroup CSI_CORE Status and Control Registers 145 \brief Core Register type definitions. 146 @{ 147 */ 148 149 /** 150 \brief ���ʴ�����״̬�Ĵ���(PSR)�������嶨��. 151 */ 152 typedef union 153 { 154 struct 155 { 156 uint32_t C: 1; /*!< bit: 0 �����룯��λλ */ 157 uint32_t _reserved0: 5; /*!< bit: 2.. 5 ���� */ 158 uint32_t IE: 1; /*!< bit: 6 �ж���Ч����λ */ 159 uint32_t IC: 1; /*!< bit: 7 �жϿ���λ */ 160 uint32_t EE: 1; /*!< bit: 8 �쳣��Ч����λ */ 161 uint32_t MM: 1; /*!< bit: 9 �������쳣�ڸ�λ */ 162 uint32_t _reserved1: 6; /*!< bit: 10..15 ���� */ 163 uint32_t VEC: 8; /*!< bit: 16..23 �쳣�¼�����ֵ */ 164 uint32_t _reserved2: 7; /*!< bit: 24..30 ���� */ 165 uint32_t S: 1; /*!< bit: 31 �����û�ģʽ����λ */ 166 } b; /*!< Structure ������λ���� */ 167 uint32_t w; /*!< Type �����Ĵ������� */ 168 } PSR_Type; 169 170 /* PSR Register Definitions */ 171 #define PSR_S_Pos 31U /*!< PSR: S Position */ 172 #define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */ 173 174 #define PSR_VEC_Pos 16U /*!< PSR: VEC Position */ 175 #define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */ 176 177 #define PSR_MM_Pos 9U /*!< PSR: MM Position */ 178 #define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */ 179 180 #define PSR_EE_Pos 8U /*!< PSR: EE Position */ 181 #define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */ 182 183 #define PSR_IC_Pos 7U /*!< PSR: IC Position */ 184 #define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */ 185 186 #define PSR_IE_Pos 6U /*!< PSR: IE Position */ 187 #define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */ 188 189 #define PSR_C_Pos 0U /*!< PSR: C Position */ 190 #define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */ 191 192 /** 193 \brief ���ʸ��ٻ������üĴ���(CCR, CR<18, 0>)�������嶨��. 194 */ 195 typedef union 196 { 197 struct 198 { 199 uint32_t MP: 1; /*!< bit: 0 �ڴ汣������λ */ 200 uint32_t _reserved0: 6; /*!< bit: 1.. 6 ���� */ 201 uint32_t BE: 1; /*!< bit: 7 Endianģʽ */ 202 uint32_t SCK: 3; /*!< bit: 8..10 ϵͳ�ʹ�������ʱ�ӱ� */ 203 uint32_t _reserved1: 2; /*!< bit: 11..12 ���� */ 204 uint32_t BE_V2: 1; /*!< bit: 13 V2�汾��С�� */ 205 uint32_t _reserved2: 18; /*!< bit: 14..31 ���� */ 206 } b; /*!< Structure ������λ���� */ 207 uint32_t w; /*!< Type �����Ĵ������� */ 208 } CCR_Type; 209 210 /* CCR Register Definitions */ 211 #define CCR_BE_V2_Pos 13U /*!< CCR: BE_V2 Position */ 212 #define CCR_BE_V2_Msk (0x1UL << CCR_ISR_Pos) /*!< CCR: BE_V2 Mask */ 213 214 #define CCR_SCK_Pos 8U /*!< CCR: SCK Position */ 215 #define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */ 216 217 #define CCR_BE_Pos 7U /*!< CCR: BE Position */ 218 #define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */ 219 220 #define CCR_MP_Pos 0U /*!< CCR: MP Position */ 221 #define CCR_MP_Msk (0x1UL << CCR_MP_Pos) /*!< CCR: MP Mask */ 222 223 /** 224 \brief ���ʿɸ��ͷ���Ȩ�����üĴ���(CAPR, CR<19,0>)�������嶨��.. 225 */ 226 typedef union 227 { 228 struct 229 { 230 uint32_t X0: 1; /*!< bit: 0 ����ִ����������λ */ 231 uint32_t X1: 1; /*!< bit: 1 ����ִ����������λ */ 232 uint32_t X2: 1; /*!< bit: 2 ����ִ����������λ */ 233 uint32_t X3: 1; /*!< bit: 3 ����ִ����������λ */ 234 uint32_t X4: 1; /*!< bit: 4 ����ִ����������λ */ 235 uint32_t X5: 1; /*!< bit: 5 ����ִ����������λ */ 236 uint32_t X6: 1; /*!< bit: 6 ����ִ����������λ */ 237 uint32_t X7: 1; /*!< bit: 7 ����ִ����������λ */ 238 uint32_t AP0: 2; /*!< bit: 8.. 9 ����Ȩ������λ */ 239 uint32_t AP1: 2; /*!< bit: 10..11 ����Ȩ������λ */ 240 uint32_t AP2: 2; /*!< bit: 12..13 ����Ȩ������λ */ 241 uint32_t AP3: 2; /*!< bit: 14..15 ����Ȩ������λ */ 242 uint32_t AP4: 2; /*!< bit: 16..17 ����Ȩ������λ */ 243 uint32_t AP5: 2; /*!< bit: 18..19 ����Ȩ������λ */ 244 uint32_t AP6: 2; /*!< bit: 20..21 ����Ȩ������λ */ 245 uint32_t AP7: 2; /*!< bit: 22..23 ����Ȩ������λ */ 246 uint32_t S0: 1; /*!< bit: 24 ��ȫ��������λ */ 247 uint32_t S1: 1; /*!< bit: 25 ��ȫ��������λ */ 248 uint32_t S2: 1; /*!< bit: 26 ��ȫ��������λ */ 249 uint32_t S3: 1; /*!< bit: 27 ��ȫ��������λ */ 250 uint32_t S4: 1; /*!< bit: 28 ��ȫ��������λ */ 251 uint32_t S5: 1; /*!< bit: 29 ��ȫ��������λ */ 252 uint32_t S6: 1; /*!< bit: 30 ��ȫ��������λ */ 253 uint32_t S7: 1; /*!< bit: 31 ��ȫ��������λ */ 254 } b; /*!< Structure ������λ���� */ 255 uint32_t w; /*!< Type �����Ĵ������� */ 256 } CAPR_Type; 257 258 /* CAPR Register Definitions */ 259 #define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */ 260 #define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */ 261 262 #define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */ 263 #define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */ 264 265 #define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */ 266 #define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */ 267 268 #define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */ 269 #define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */ 270 271 #define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */ 272 #define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */ 273 274 #define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */ 275 #define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */ 276 277 #define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */ 278 #define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */ 279 280 #define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */ 281 #define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */ 282 283 #define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */ 284 #define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */ 285 286 #define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */ 287 #define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */ 288 289 #define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */ 290 #define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */ 291 292 #define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */ 293 #define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */ 294 295 #define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */ 296 #define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */ 297 298 #define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */ 299 #define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */ 300 301 #define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */ 302 #define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */ 303 304 #define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */ 305 #define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */ 306 307 #define CAPR_X7_Pos 7U /*!< CAPR: X7 Position */ 308 #define CAPR_X7_Msk (0x1UL << CAPR_X7_Pos) /*!< CAPR: X7 Mask */ 309 310 #define CAPR_X6_Pos 6U /*!< CAPR: X6 Position */ 311 #define CAPR_X6_Msk (0x1UL << CAPR_X6_Pos) /*!< CAPR: X6 Mask */ 312 313 #define CAPR_X5_Pos 5U /*!< CAPR: X5 Position */ 314 #define CAPR_X5_Msk (0x1UL << CAPR_X5_Pos) /*!< CAPR: X5 Mask */ 315 316 #define CAPR_X4_Pos 4U /*!< CAPR: X4 Position */ 317 #define CAPR_X4_Msk (0x1UL << CAPR_X4_Pos) /*!< CAPR: X4 Mask */ 318 319 #define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */ 320 #define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */ 321 322 #define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */ 323 #define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */ 324 325 #define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */ 326 #define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */ 327 328 #define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */ 329 #define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */ 330 331 /** 332 \brief ���ʱ��������ƼĴ���(PACR, CR<20,0>)�������嶨��. 333 */ 334 typedef union 335 { 336 struct 337 { 338 uint32_t E: 1; /*!< bit: 0 ��������Ч���� */ 339 uint32_t Size: 5; /*!< bit: 1.. 5 ��������С */ 340 uint32_t _reserved0: 4; /*!< bit: 6.. 9 ���� */ 341 uint32_t base_addr: 22; /*!< bit: 10..31 ��������ַ�ĸ�λ */ 342 } b; /*!< Structure ������λ���� */ 343 uint32_t w; /*!< Type �����Ĵ������� */ 344 } PACR_Type; 345 346 /* PACR Register Definitions */ 347 #define PACR_BASE_ADDR_Pos 10U /*!< PACR: base_addr Position */ 348 #define PACK_BASE_ADDR_Msk (0x3FFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */ 349 350 #define PACR_SIZE_Pos 1U /*!< PACR: Size Position */ 351 #define PACK_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */ 352 353 #define PACR_E_Pos 0U /*!< PACR: E Position */ 354 #define PACK_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */ 355 356 /** 357 \brief ���ʱ�����ѡ��Ĵ���(PRSR,CR<21,0>)�������嶨��. 358 */ 359 typedef union 360 { 361 struct 362 { 363 uint32_t RID: 3; /*!< bit: 0.. 2 ����������ֵ */ 364 uint32_t _reserved0: 30; /*!< bit: 3..31 ���� */ 365 } b; /*!< Structure ������λ���� */ 366 uint32_t w; /*!< Type �����Ĵ������� */ 367 } PRSR_Type; 368 369 /* PRSR Register Definitions */ 370 #define PRSR_RID_Pos 0U /*!< PRSR: RID Position */ 371 #define PRSR_RID_Msk (0x7UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */ 372 373 /*@} end of group CSI_CORE */ 374 375 376 /** 377 \ingroup CSI_core_register 378 \defgroup CSI_NVIC Vectored Interrupt Controller (NVIC) 379 \brief Type definitions for the NVIC Registers 380 @{ 381 */ 382 383 /** 384 \brief ����ʸ���жϿ������Ľṹ��. 385 */ 386 typedef struct 387 { 388 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) �ж�ʹ�����üĴ��� */ 389 uint32_t RESERVED0[15U]; 390 __IOM uint32_t IWER[1U]; /*!< Offset: 0x040 (R/W) �жϵ��Ļ������üĴ��� */ 391 uint32_t RESERVED1[15U]; 392 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) �ж�ʹ������Ĵ��� */ 393 uint32_t RESERVED2[15U]; 394 __IOM uint32_t IWDR[1U]; /*!< Offset: 0x0c0 (R/W) �жϵ��Ļ�������Ĵ��� */ 395 uint32_t RESERVED3[15U]; 396 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) �жϵȴ����üĴ��� */ 397 uint32_t RESERVED4[15U]; 398 __IOM uint32_t ISSR[1U]; /*!< Offset: 0x140 (R/W) ��ȫ�ж�ʹ�����üĴ��� */ 399 uint32_t RESERVED5[15U]; 400 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) �жϵȴ�����Ĵ��� */ 401 uint32_t RESERVED6[31U]; 402 __IOM uint32_t IABR[1U]; /*!< Offset: 0x200 (R/W) �ж���Ӧ״̬�Ĵ��� */ 403 uint32_t RESERVED7[63U]; 404 __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) �ж����ȼ����üĴ��� */ 405 uint32_t RESERVED8[504U]; 406 __IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) �ж�״̬�Ĵ��� */ 407 __IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) �ж����ȼ���ֵ�Ĵ��� */ 408 } NVIC_Type; 409 410 /*@} end of group CSI_NVIC */ 411 412 /** 413 \ingroup CSI_core_register 414 \defgroup CSI_SysTick System Tick Timer (CORET) 415 \brief Type definitions for the System Timer Registers. 416 @{ 417 */ 418 419 /** 420 \brief ����ϵͳ��ʱ�������ݽṹ. 421 */ 422 typedef struct 423 { 424 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) ����״̬�Ĵ��� */ 425 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) ����ֵ�Ĵ��� */ 426 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) ��ǰֵ�Ĵ��� */ 427 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) У�Ĵ��� */ 428 } CORET_Type; 429 430 /* CORET Control / Status Register Definitions */ 431 #define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */ 432 #define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */ 433 434 #define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */ 435 #define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */ 436 437 #define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */ 438 #define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */ 439 440 #define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */ 441 #define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */ 442 443 /* CORET Reload Register Definitions */ 444 #define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */ 445 #define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */ 446 447 /* CORET Current Register Definitions */ 448 #define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */ 449 #define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */ 450 451 /* CORET Calibration Register Definitions */ 452 #define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */ 453 #define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */ 454 455 #define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */ 456 #define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */ 457 458 #define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */ 459 #define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */ 460 461 /*@} end of group CSI_SysTick */ 462 463 /** 464 \ingroup CSI_core_register 465 \defgroup CSI_DCC 466 \brief Type definitions for the DCC. 467 @{ 468 */ 469 470 /** 471 \brief ����DCC�����ݽṹ. 472 */ 473 typedef struct 474 { 475 uint32_t RESERVED0[13U]; 476 __IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */ 477 __IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */ 478 uint32_t RESERVED1[6U]; 479 union 480 { 481 __IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) ���ݽ����Ĵ��� CPU��*/ 482 __OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) ���ݽ����Ĵ��� CPUд*/ 483 }; 484 485 } DCC_Type; 486 487 #define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */ 488 #define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */ 489 490 #define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */ 491 #define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */ 492 493 #define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */ 494 #define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */ 495 496 #define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */ 497 #define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */ 498 499 /*@} end of group CSI_DCC */ 500 501 502 /** 503 \ingroup CSI_core_register 504 \defgroup CSI_core_bitfield Core register bit field macros 505 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 506 @{ 507 */ 508 509 /** 510 \brief Mask and shift a bit field value for use in a register bit range. 511 \param[in] field Name of the register bit field. 512 \param[in] value Value of the bit field. 513 \return Masked and shifted value. 514 */ 515 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) 516 517 /** 518 \brief Mask and shift a register value to extract a bit filed value. 519 \param[in] field Name of the register bit field. 520 \param[in] value Value of register. 521 \return Masked and shifted bit field value. 522 */ 523 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) 524 525 /*@} end of group CSI_core_bitfield */ 526 527 /** 528 \ingroup CSI_core_register 529 \defgroup CSI_core_base Core Definitions 530 \brief Definitions for base addresses, unions, and structures. 531 @{ 532 */ 533 534 /* Memory mapping of CK802 Hardware */ 535 #define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */ 536 #define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */ 537 #define NVIC_BASE (TCIP_BASE + 0x0100UL) /*!< NVIC Base Address */ 538 #define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */ 539 540 #define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */ 541 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 542 #define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */ 543 544 /*@} */ 545 546 #ifdef __cplusplus 547 } 548 #endif 549 550 #endif /* __CORE_CK802_H_DEPENDANT */ 551 552 #endif /* __CSI_GENERIC */ 553