1 /* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 */ 9 #ifndef EN28J60_H_INCLUDED 10 #define EN28J60_H_INCLUDED 11 12 #include <stdint.h> 13 14 #include <rtthread.h> 15 #include <drivers/spi.h> 16 #include <netif/ethernetif.h> 17 18 // ENC28J60 Control Registers 19 // Control register definitions are a combination of address, 20 // bank number, and Ethernet/MAC/PHY indicator bits. 21 // - Register address (bits 0-4) 22 // - Bank number (bits 5-6) 23 // - MAC/PHY indicator (bit 7) 24 #define ADDR_MASK 0x1F 25 #define BANK_MASK 0x60 26 #define SPRD_MASK 0x80 27 // All-bank registers 28 #define EIE 0x1B 29 #define EIR 0x1C 30 #define ESTAT 0x1D 31 #define ECON2 0x1E 32 #define ECON1 0x1F 33 // Bank 0 registers 34 #define ERDPTL (0x00|0x00) 35 #define ERDPTH (0x01|0x00) 36 #define EWRPTL (0x02|0x00) 37 #define EWRPTH (0x03|0x00) 38 #define ETXSTL (0x04|0x00) 39 #define ETXSTH (0x05|0x00) 40 #define ETXNDL (0x06|0x00) 41 #define ETXNDH (0x07|0x00) 42 #define ERXSTL (0x08|0x00) 43 #define ERXSTH (0x09|0x00) 44 #define ERXNDL (0x0A|0x00) 45 #define ERXNDH (0x0B|0x00) 46 #define ERXRDPTL (0x0C|0x00) 47 #define ERXRDPTH (0x0D|0x00) 48 #define ERXWRPTL (0x0E|0x00) 49 #define ERXWRPTH (0x0F|0x00) 50 #define EDMASTL (0x10|0x00) 51 #define EDMASTH (0x11|0x00) 52 #define EDMANDL (0x12|0x00) 53 #define EDMANDH (0x13|0x00) 54 #define EDMADSTL (0x14|0x00) 55 #define EDMADSTH (0x15|0x00) 56 #define EDMACSL (0x16|0x00) 57 #define EDMACSH (0x17|0x00) 58 // Bank 1 registers 59 #define EHT0 (0x00|0x20) 60 #define EHT1 (0x01|0x20) 61 #define EHT2 (0x02|0x20) 62 #define EHT3 (0x03|0x20) 63 #define EHT4 (0x04|0x20) 64 #define EHT5 (0x05|0x20) 65 #define EHT6 (0x06|0x20) 66 #define EHT7 (0x07|0x20) 67 #define EPMM0 (0x08|0x20) 68 #define EPMM1 (0x09|0x20) 69 #define EPMM2 (0x0A|0x20) 70 #define EPMM3 (0x0B|0x20) 71 #define EPMM4 (0x0C|0x20) 72 #define EPMM5 (0x0D|0x20) 73 #define EPMM6 (0x0E|0x20) 74 #define EPMM7 (0x0F|0x20) 75 #define EPMCSL (0x10|0x20) 76 #define EPMCSH (0x11|0x20) 77 #define EPMOL (0x14|0x20) 78 #define EPMOH (0x15|0x20) 79 #define EWOLIE (0x16|0x20) 80 #define EWOLIR (0x17|0x20) 81 #define ERXFCON (0x18|0x20) 82 #define EPKTCNT (0x19|0x20) 83 // Bank 2 registers 84 #define MACON1 (0x00|0x40|0x80) 85 #define MACON2 (0x01|0x40|0x80) 86 #define MACON3 (0x02|0x40|0x80) 87 #define MACON4 (0x03|0x40|0x80) 88 #define MABBIPG (0x04|0x40|0x80) 89 #define MAIPGL (0x06|0x40|0x80) 90 #define MAIPGH (0x07|0x40|0x80) 91 #define MACLCON1 (0x08|0x40|0x80) 92 #define MACLCON2 (0x09|0x40|0x80) 93 #define MAMXFLL (0x0A|0x40|0x80) 94 #define MAMXFLH (0x0B|0x40|0x80) 95 #define MAPHSUP (0x0D|0x40|0x80) 96 #define MICON (0x11|0x40|0x80) 97 #define MICMD (0x12|0x40|0x80) 98 #define MIREGADR (0x14|0x40|0x80) 99 #define MIWRL (0x16|0x40|0x80) 100 #define MIWRH (0x17|0x40|0x80) 101 #define MIRDL (0x18|0x40|0x80) 102 #define MIRDH (0x19|0x40|0x80) 103 // Bank 3 registers 104 #define MAADR1 (0x00|0x60|0x80) 105 #define MAADR0 (0x01|0x60|0x80) 106 #define MAADR3 (0x02|0x60|0x80) 107 #define MAADR2 (0x03|0x60|0x80) 108 #define MAADR5 (0x04|0x60|0x80) 109 #define MAADR4 (0x05|0x60|0x80) 110 #define EBSTSD (0x06|0x60) 111 #define EBSTCON (0x07|0x60) 112 #define EBSTCSL (0x08|0x60) 113 #define EBSTCSH (0x09|0x60) 114 #define MISTAT (0x0A|0x60|0x80) 115 #define EREVID (0x12|0x60) 116 #define ECOCON (0x15|0x60) 117 #define EFLOCON (0x17|0x60) 118 #define EPAUSL (0x18|0x60) 119 #define EPAUSH (0x19|0x60) 120 // PHY registers 121 #define PHCON1 0x00 122 #define PHSTAT1 0x01 123 #define PHHID1 0x02 124 #define PHHID2 0x03 125 #define PHCON2 0x10 126 #define PHSTAT2 0x11 127 #define PHIE 0x12 128 #define PHIR 0x13 129 #define PHLCON 0x14 130 131 // ENC28J60 ERXFCON Register Bit Definitions 132 #define ERXFCON_UCEN 0x80 133 #define ERXFCON_ANDOR 0x40 134 #define ERXFCON_CRCEN 0x20 135 #define ERXFCON_PMEN 0x10 136 #define ERXFCON_MPEN 0x08 137 #define ERXFCON_HTEN 0x04 138 #define ERXFCON_MCEN 0x02 139 #define ERXFCON_BCEN 0x01 140 // ENC28J60 EIE Register Bit Definitions 141 #define EIE_INTIE 0x80 142 #define EIE_PKTIE 0x40 143 #define EIE_DMAIE 0x20 144 #define EIE_LINKIE 0x10 145 #define EIE_TXIE 0x08 146 #define EIE_WOLIE 0x04 147 #define EIE_TXERIE 0x02 148 #define EIE_RXERIE 0x01 149 // ENC28J60 EIR Register Bit Definitions 150 #define EIR_PKTIF 0x40 151 #define EIR_DMAIF 0x20 152 #define EIR_LINKIF 0x10 153 #define EIR_TXIF 0x08 154 #define EIR_WOLIF 0x04 155 #define EIR_TXERIF 0x02 156 #define EIR_RXERIF 0x01 157 // ENC28J60 ESTAT Register Bit Definitions 158 #define ESTAT_INT 0x80 159 #define ESTAT_LATECOL 0x10 160 #define ESTAT_RXBUSY 0x04 161 #define ESTAT_TXABRT 0x02 162 #define ESTAT_CLKRDY 0x01 163 // ENC28J60 ECON2 Register Bit Definitions 164 #define ECON2_AUTOINC 0x80 165 #define ECON2_PKTDEC 0x40 166 #define ECON2_PWRSV 0x20 167 #define ECON2_VRPS 0x08 168 // ENC28J60 ECON1 Register Bit Definitions 169 #define ECON1_TXRST 0x80 170 #define ECON1_RXRST 0x40 171 #define ECON1_DMAST 0x20 172 #define ECON1_CSUMEN 0x10 173 #define ECON1_TXRTS 0x08 174 #define ECON1_RXEN 0x04 175 #define ECON1_BSEL1 0x02 176 #define ECON1_BSEL0 0x01 177 // ENC28J60 MACON1 Register Bit Definitions 178 #define MACON1_LOOPBK 0x10 179 #define MACON1_TXPAUS 0x08 180 #define MACON1_RXPAUS 0x04 181 #define MACON1_PASSALL 0x02 182 #define MACON1_MARXEN 0x01 183 // ENC28J60 MACON2 Register Bit Definitions 184 #define MACON2_MARST 0x80 185 #define MACON2_RNDRST 0x40 186 #define MACON2_MARXRST 0x08 187 #define MACON2_RFUNRST 0x04 188 #define MACON2_MATXRST 0x02 189 #define MACON2_TFUNRST 0x01 190 // ENC28J60 MACON3 Register Bit Definitions 191 #define MACON3_PADCFG2 0x80 192 #define MACON3_PADCFG1 0x40 193 #define MACON3_PADCFG0 0x20 194 #define MACON3_TXCRCEN 0x10 195 #define MACON3_PHDRLEN 0x08 196 #define MACON3_HFRMLEN 0x04 197 #define MACON3_FRMLNEN 0x02 198 #define MACON3_FULDPX 0x01 199 // ENC28J60 MACON4 Register Bit Definitions 200 #define MACON4_DEFER (1<<6) 201 #define MACON4_BPEN (1<<5) 202 #define MACON4_NOBKOFF (1<<4) 203 // ENC28J60 MICMD Register Bit Definitions 204 #define MICMD_MIISCAN 0x02 205 #define MICMD_MIIRD 0x01 206 // ENC28J60 MISTAT Register Bit Definitions 207 #define MISTAT_NVALID 0x04 208 #define MISTAT_SCAN 0x02 209 #define MISTAT_BUSY 0x01 210 // ENC28J60 PHY PHCON1 Register Bit Definitions 211 #define PHCON1_PRST 0x8000 212 #define PHCON1_PLOOPBK 0x4000 213 #define PHCON1_PPWRSV 0x0800 214 #define PHCON1_PDPXMD 0x0100 215 // ENC28J60 PHY PHSTAT1 Register Bit Definitions 216 #define PHSTAT1_PFDPX 0x1000 217 #define PHSTAT1_PHDPX 0x0800 218 #define PHSTAT1_LLSTAT 0x0004 219 #define PHSTAT1_JBSTAT 0x0002 220 /* ENC28J60 PHY PHSTAT2 Register Bit Definitions */ 221 #define PHSTAT2_TXSTAT (1 << 13) 222 #define PHSTAT2_RXSTAT (1 << 12) 223 #define PHSTAT2_COLSTAT (1 << 11) 224 #define PHSTAT2_LSTAT (1 << 10) 225 #define PHSTAT2_DPXSTAT (1 << 9) 226 #define PHSTAT2_PLRITY (1 << 5) 227 // ENC28J60 PHY PHCON2 Register Bit Definitions 228 #define PHCON2_FRCLINK 0x4000 229 #define PHCON2_TXDIS 0x2000 230 #define PHCON2_JABBER 0x0400 231 #define PHCON2_HDLDIS 0x0100 232 /* ENC28J60 PHY PHIE Register Bit Definitions */ 233 #define PHIE_PLNKIE (1 << 4) 234 #define PHIE_PGEIE (1 << 1) 235 /* ENC28J60 PHY PHIR Register Bit Definitions */ 236 #define PHIR_PLNKIF (1 << 4) 237 #define PHIR_PGEIF (1 << 1) 238 239 // ENC28J60 Packet Control Byte Bit Definitions 240 #define PKTCTRL_PHUGEEN 0x08 241 #define PKTCTRL_PPADEN 0x04 242 #define PKTCTRL_PCRCEN 0x02 243 #define PKTCTRL_POVERRIDE 0x01 244 245 /* ENC28J60 Transmit Status Vector */ 246 #define TSV_TXBYTECNT 0 247 #define TSV_TXCOLLISIONCNT 16 248 #define TSV_TXCRCERROR 20 249 #define TSV_TXLENCHKERROR 21 250 #define TSV_TXLENOUTOFRANGE 22 251 #define TSV_TXDONE 23 252 #define TSV_TXMULTICAST 24 253 #define TSV_TXBROADCAST 25 254 #define TSV_TXPACKETDEFER 26 255 #define TSV_TXEXDEFER 27 256 #define TSV_TXEXCOLLISION 28 257 #define TSV_TXLATECOLLISION 29 258 #define TSV_TXGIANT 30 259 #define TSV_TXUNDERRUN 31 260 #define TSV_TOTBYTETXONWIRE 32 261 #define TSV_TXCONTROLFRAME 48 262 #define TSV_TXPAUSEFRAME 49 263 #define TSV_BACKPRESSUREAPP 50 264 #define TSV_TXVLANTAGFRAME 51 265 266 #define TSV_SIZE 7 267 #define TSV_BYTEOF(x) ((x) / 8) 268 #define TSV_BITMASK(x) (1 << ((x) % 8)) 269 #define TSV_GETBIT(x, y) (((x)[TSV_BYTEOF(y)] & TSV_BITMASK(y)) ? 1 : 0) 270 271 /* ENC28J60 Receive Status Vector */ 272 #define RSV_RXLONGEVDROPEV 16 273 #define RSV_CARRIEREV 18 274 #define RSV_CRCERROR 20 275 #define RSV_LENCHECKERR 21 276 #define RSV_LENOUTOFRANGE 22 277 #define RSV_RXOK 23 278 #define RSV_RXMULTICAST 24 279 #define RSV_RXBROADCAST 25 280 #define RSV_DRIBBLENIBBLE 26 281 #define RSV_RXCONTROLFRAME 27 282 #define RSV_RXPAUSEFRAME 28 283 #define RSV_RXUNKNOWNOPCODE 29 284 #define RSV_RXTYPEVLAN 30 285 286 #define RSV_SIZE 6 287 #define RSV_BITMASK(x) (1 << ((x) - 16)) 288 #define RSV_GETBIT(x, y) (((x) & RSV_BITMASK(y)) ? 1 : 0) 289 290 // SPI operation codes 291 #define ENC28J60_READ_CTRL_REG 0x00 292 #define ENC28J60_READ_BUF_MEM 0x3A 293 #define ENC28J60_WRITE_CTRL_REG 0x40 294 #define ENC28J60_WRITE_BUF_MEM 0x7A 295 #define ENC28J60_BIT_FIELD_SET 0x80 296 #define ENC28J60_BIT_FIELD_CLR 0xA0 297 #define ENC28J60_SOFT_RESET 0xFF 298 299 // The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata 300 // buffer boundaries applied to internal 8K ram 301 // the entire available packet buffer space is allocated 302 // 303 304 #define MAX_TX_PACKAGE_SIZE (1536) 305 306 // start with recbuf at 0/ 307 #define RXSTART_INIT 0x0 308 // receive buffer end 309 #define RXSTOP_INIT (0x1FFF - MAX_TX_PACKAGE_SIZE*2) - 1 310 // start TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (~1500 bytes) 311 312 #define TXSTART_INIT (0x1FFF - MAX_TX_PACKAGE_SIZE*2) 313 // stp TX buffer at end of mem 314 #define TXSTOP_INIT 0x1FFF 315 316 // max frame length which the conroller will accept: 317 #define MAX_FRAMELEN 1518 318 319 #define MAX_ADDR_LEN 6 320 321 struct net_device 322 { 323 /* inherit from ethernet device */ 324 struct eth_device parent; 325 326 /* interface address info. */ 327 rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ 328 329 rt_uint8_t emac_rev; 330 rt_uint8_t phy_rev; 331 rt_uint8_t phy_pn; 332 rt_uint32_t phy_id; 333 334 /* spi device */ 335 struct rt_spi_device *spi_device; 336 struct rt_mutex lock; 337 }; 338 339 /* export function */ 340 extern rt_err_t enc28j60_attach(const char *spi_device_name); 341 extern void enc28j60_isr(void); 342 343 #endif // EN28J60_H_INCLUDED 344