Decoder: Add demo of vector decoder

SrcType: refactor and add vp type

issue: add alu and jump[csr] rs

More modification:
1. parameter RSMod to generate different submodules
add case class RSMod for a list of rs's submodule's generator methods
2. remove [submodule]RSIO

issue: add alu and jump[csr] rs

More modification:
1. parameter RSMod to generate different submodules
add case class RSMod for a list of rs's submodule's generator methods
2. remove [submodule]RSIO
remove ALU[Jump..]RSIO, add RSExtraIO to contain all the extra
io of different child class. Ugly codes. Assign DontCare to the extra
io.
3. Same with 2. The submodule's io should contain all the io.

For jump:
move pcMem part code into JumpRS from BaseRS

For jump and alu:
add immExtractorGen for jump/alu and other child class

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issue: fix typo

issue: add submodule for each type rs, not acutually implimented

There are several kinds of reservation station type. Name them with
coresponding exu name:
1. ALU
2. Jump[/CSR/i2f/fence]
3. Mul[Div]

issue: add submodule for each type rs, not acutually implimented

There are several kinds of reservation station type. Name them with
coresponding exu name:
1. ALU
2. Jump[/CSR/i2f/fence]
3. Mul[Div]
4. Load
5. Sta
6. Std
7. FMA[c]
8. FMisc

They have only a few differences with each other. The main body of
rs is the same. To make rs more easy to read and understand, we
keep the 'common body' in the BaseRS, move the difference into the
submodules.

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fu: enable input buffer bypass for divSqrt

fu: allow bypass from input buffer

div: enable input buffer to allow more inflights

Fix exception priorities for load/store address misaligned (#1753)

l1tlb: tlb's req port can be configured to be block or non-blocked (#1656)

each tlb's port can be configured to be block or non-blocked.
For blocked port, there will be a req miss slot stored in tl

l1tlb: tlb's req port can be configured to be block or non-blocked (#1656)

each tlb's port can be configured to be block or non-blocked.
For blocked port, there will be a req miss slot stored in tlb, but belong to
core pipeline, which means only core pipeline flush will invalid them.

For another, itlb also use PTW Filter but with only 4 entries.
Last, keep svinval extension as usual, still work.


* tlb: add blocked-tlb support, miss frontend changes

* tlb: remove tlb's sameCycle support, result will return at next cycle

* tlb: remove param ShouldBlock, move block method into TLB module

* tlb: fix handle_block's miss_req logic

* mmu.filter: change filter's req.ready to canEnqueue

when filter can't let all the req enqueue, set the req.ready to false.
canEnqueue after filtering has long latency, so we use **_fake
without filtering, but the filter will still receive the reqs if
it can(after filtering).

* mmu.tlb: change name from BTlbPtwIO to VectorTlbPtwIO

* mmu: replace itlb's repeater to filter&repeaternb

* mmu.tlb: add TlbStorageWrapper to make TLB cleaner

more: BlockTlbRequestorIO is same with TlbRequestorIO, rm it

* mmu.tlb: rm unused param in function r_req_apply, fix syntax bug

* [WIP]icache: itlb usage from non-blocked to blocked

* mmu.tlb: change parameter NBWidth to Seq of boolean

* icache.mainpipe: fix itlb's resp.ready, not always true

* mmu.tlb: add kill sigal to blocked req that needs sync but fail

in frontend, icache,itlb,next pipe may not able to sync.
blocked tlb will store miss req ang blocks req, which makes itlb
couldn't work. So add kill logic to let itlb not to store reqs.

One more thing: fix icache's blocked tlb handling logic

* icache.mainpipe: fix tlb's ready_recv logic

icache mainpipe has two ports, but these two ports may not valid
all the same time. So add new signals tlb_need_recv to record whether
stage s1 should wait for the tlb.

* tlb: when flush, just set resp.valid and pf, pf for don't use it

* tlb: flush should concern satp.changed(for blocked io now)

* mmu.tlb: add new flush that doesn't flush reqs

Sfence.vma will flush inflight reqs and flushPipe
But some other sfence(svinval...) will not. So add new flush to
distinguish these two kinds of sfence signal

morw: forget to assign resp result when ptw back, fix it

* mmu.tlb: beautify miss_req_v and miss_v relative logic

* mmu.tlb: fix bug, when ptw back and bypass, concern level to genPPN

bug: when ptw back and bypass, forgot to concern level(1GB/2MB/4KB)
when genPPN.

by the way: some funtions need ": Unit = ", add it.

* mmu.filter: fix bug of canEnqueue, mixed with tlb_req and tlb.req

* icache.mainpipe: fix bug of tlbExcp's usage, & with tlb_need_back

Icache's mainpipe has two ports, but may only port 0 is valid.
When a port is invalid, the tlbexcp should be false.(Actually, should
be ignored).
So & tlb_need_back to fix this bug.

* sfence: instr in svinval ext will also flush pipe

A difficult problem to handle:
Sfence and Svinval will flush MMU, but only Sfence(some svinval)
will flush pipe. For itlb that some requestors are blocked and
icache doesn't recv flush for simplicity, itlb's blocked ptw req
should not be flushed.
It's a huge problem for MMU to handle for good or bad solutions. But
svinval is seldom used, so disable it's effiency.

* mmu: add parameter to control mmu's sfence delay latency

Difficult problem:
itlb's blocked req should not be abandoned, but sfence will flush
all infight reqs. when itlb and itlb repeater's delay is not same(itlb
is flushed, two cycles later, itlb repeater is flushed, then itlb's
ptw req after flushing will be also flushed sliently.
So add one parameter to control the flush delay to be the same.

* mmu.tlb: fix bug of csr.priv's delay & sfence valid when req fire

1. csr.priv's delay
csr.priv should not be delayed, csr.satp should be delayed.
for excep/intr will change csr.priv, which will be changed at one
instruction's (commit?). but csrrw satp will not, so satp has more
cycles to delay.
2. sfence
when sfence valid but blocked req fire, resp should still fire.
3. satp in TlbCsrBundle
let high bits of satp.ppn to be 0.U

* tlb&icache.mainpipe: rm commented codes

* mmu: move method genPPN to entry bundle

* l1tlb: divide l1tlb flush into flush_mmu and flush_pipe

Problem:
For l1tlb, there are blocked and non-blocked req ports.
For blocked ports, there are req slots to store missed reqs.
Some mmu flush like Sfence should not flush miss slots for outside
may still need get tlb resp, no matter wrong and correct resp.
For example. sfence will flush mmu and flush pipe, but won't flush
reqs inside icache, which waiting for tlb resp.
For example, svinval instr will flush mmu, but not flush pipe. so
tlb should return correct resp, althrough the ptw req is flushed
when tlb miss.

Solution:
divide l1tlb flush into flush_mmu and flush_pipe.
The req slot is considered to be a part of core pipeline and should
only be flushed by flush_pipe.
flush_mmu will flush mmu entries and inflight ptw reqs.
When miss but sfence flushed its ptw req, re-send.

* l1tlb: code clean, correct comments and rm unused codes

* l2tlb: divide filterSize into ifiterSize and dfilterSize

* l2tlb: prefetch req won't enter miss queue. Rename MSHR to missqueue

* l1tlb: when disable vm, ptw back should not bypass tlb and should let miss req go ahead

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decode: Replace dontcare field with signal x (#1615)

* Remove unused field isRVF
* Replace 3rd srcType of non-fp insts and FuType.{fmisc, i2f} insts with SrcType.X

dcache: repipeline ecc check logic for timing (#1582)

This commit re-pipelines ECC check logic in data cache and exception generate logic for better timing.
Now ecc error is checked 1 cycle after r

dcache: repipeline ecc check logic for timing (#1582)

This commit re-pipelines ECC check logic in data cache and exception generate logic for better timing.
Now ecc error is checked 1 cycle after reading result from data sram. An extra cycle is added for load
writeback to ROB.

Future work: move the pipeline to https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/backend/CtrlBlock.scala#L266-L277, which add a regnext.

* dcache: repipeline ecc check logic for timing

* chore: fix normal loadAccessFault logic

* wbu: delay load unit wb for 1 cycle

* dcache: add 1 extra cycle for beu error report

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perfcnt: keep strict regularity of perf counter name (#1585)

* buspmu: avoid inner space in perf-cnt name

* perfcnt: judge regularity of perfname

* perfcnt: fix some irregular perfname

* bu

perfcnt: keep strict regularity of perf counter name (#1585)

* buspmu: avoid inner space in perf-cnt name

* perfcnt: judge regularity of perfname

* perfcnt: fix some irregular perfname

* bump huancun

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fix for chipsalliance/rocket-chip#2967 (#1562)

* fix for chipsalliance/rocket-chip#2967

* decode: fix width of BitPat(?) in decode logic

Co-authored-by: Yinan Xu <[email protected]>

csr: check WFI and other illegal instructions

core,rob: support the WFI instruction

The RISC-V WFI instruction is previously decoded as NOP. This commit
adds support for the real wait-for-interrupt (WFI).

We add a state_wfi FSM in the ROB. Aft

core,rob: support the WFI instruction

The RISC-V WFI instruction is previously decoded as NOP. This commit
adds support for the real wait-for-interrupt (WFI).

We add a state_wfi FSM in the ROB. After WFI leaves the ROB, the next
instruction will wait in the ROB until an interrupt.

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core: refactor writeback parameters (#1327)

This commit adds WritebackSink and WritebackSource parameters for
multiple modules. These traits hide implementation details from
other modules by defin

core: refactor writeback parameters (#1327)

This commit adds WritebackSink and WritebackSource parameters for
multiple modules. These traits hide implementation details from
other modules by defining IO-related functions in modules.

By using WritebackSink, ROB is able to choose the writeback sources.
Now fflags and exceptions are connected from exe units to reduce write
ports and optimize timing.

Further optimizations on write-back to RS and better coding style to
be added later.

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bku: fix sm4 instructions (#1263)

fdiv: enable fast uop to reduce latency (#1275)

div: enable fast uop out to reduce latency (#1273)

mem: simplify software prefetch logic (#1176)

* mem: update lsu op encoding
* decode: remove prefetch bits from CtrlSignals
* mem: simplify software prefetch logic in loadpipe
* mem: fix wrong dc

mem: simplify software prefetch logic (#1176)

* mem: update lsu op encoding
* decode: remove prefetch bits from CtrlSignals
* mem: simplify software prefetch logic in loadpipe
* mem: fix wrong dcacheShouldResp assertion

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Svinval (#1055)

* Svinval: implement Svinval
* add three new instructions(SINVAL_VMA SFENCE_W_INVAL SFENCE_INVAL_IR)
* TODO : test

* Prevent illegal software code by adding an assert
* make sure th

Svinval (#1055)

* Svinval: implement Svinval
* add three new instructions(SINVAL_VMA SFENCE_W_INVAL SFENCE_INVAL_IR)
* TODO : test

* Prevent illegal software code by adding an assert
* make sure the software runs as follow:
begin instruction of svinval extension
svinval xxxx
svinval xxxx
...
end instruction of svinval extension

* Svinval: add an CSR to control it and some annotations

* Roq: fix assert bug of Svinval

* Svinval: fix svinval.vma's rs2 type
* make it reg instead of imm

* Svinval: change assert logic and fix bug
* fix the condition judging Svinval.vma instruction
* using doingSvinval in assert

* ci: add rv64mi-p-svinval to ci

* fix typo

* fix bug that lost ','

* when svinval disable, raise illegal instr excep

* CSR: mv svinval ctl to srnctl(1)

* rob: when excep, do not set dosvinval

* decode: when disable svinval, do not set flushpipe

* bump ready-to-run

Co-authored-by: ZhangZifei <[email protected]>

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rob: optimize bits width in storage (#1155)

This PR optimizes out isFused and crossPageIPFFix usages in Rob's DispatchData. They will not be stored in ROB. Now DispatchData has only 38 bits.

* is

rob: optimize bits width in storage (#1155)

This PR optimizes out isFused and crossPageIPFFix usages in Rob's DispatchData. They will not be stored in ROB. Now DispatchData has only 38 bits.

* isFused is merged with commitType (2 bits reduced)
* crossPageIPFFix is used only in ExceptionGen (1 bit reduced)
* rename: reduce ldest usages
* decode: set isMove to false if ldest is zero

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asid: add asid, mainly work when hit check, not in sfence.vma (#1090)

add mmu's asid support.
1. put asid inside sram (if the entry is sram), or it will take too many sources.
2. when sfence, just

asid: add asid, mainly work when hit check, not in sfence.vma (#1090)

add mmu's asid support.
1. put asid inside sram (if the entry is sram), or it will take too many sources.
2. when sfence, just flush it all, don't care asid.
3. when hit check, check asid.
4. when asid changed, flush all the inflight ptw req for safety
5. simple asid unit test:
asid 1 write, asid 2 read and check, asid 2 write, asid 1 read and check. same va, different pa

* ASID: make satp's asid bits configurable to RW
* use AsidLength to control it

* ASID: implement asid refilling and hit checking
* TODO: sfence flush with asid

* ASID: implement sfence with asid
* TODO: extract asid from SRAMTemplate

* ASID: extract asid from SRAMTemplate
* all is down
* TODO: test

* fix write to asid

* Sfence: support rs2 of sfence and fix Fence Unit
* rs2 of Sfence should be Reg and pass it to Fence Unit
* judge the value of reg instead of the index in Fence Unit

* mmu: re-write asid

now, asid is stored inside sram, so sfence just flush it
it's a complex job to handle the problem that asid is changed but
no sfence.vma is executed. when asid is changed, all the inflight
mmu reqs are flushed but entries in storage is not influenced.
so the inflight reqs do not need to record asid, just use satp.asid

* tlb: fix bug of refill mask

* ci: add asid unit test

Co-authored-by: ZhangZifei <[email protected]>

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mem: add Zicbom and Zicboz support (#1145)

Now we merge them for timing opt, unit test to be added later