1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.exu._ 25import xiangshan.backend.Std 26 27package object xiangshan { 28 object SrcType { 29 def reg = "b00".U 30 def pc = "b01".U 31 def imm = "b01".U 32 def fp = "b10".U 33 34 def DC = imm // Don't Care 35 36 def isReg(srcType: UInt) = srcType===reg 37 def isPc(srcType: UInt) = srcType===pc 38 def isImm(srcType: UInt) = srcType===imm 39 def isFp(srcType: UInt) = srcType(1) 40 def isPcOrImm(srcType: UInt) = srcType(0) 41 def isRegOrFp(srcType: UInt) = !srcType(0) 42 def regIsFp(srcType: UInt) = srcType(1) 43 44 def apply() = UInt(2.W) 45 } 46 47 object SrcState { 48 def busy = "b0".U 49 def rdy = "b1".U 50 // def specRdy = "b10".U // speculative ready, for future use 51 def apply() = UInt(1.W) 52 } 53 54 object FuType { 55 def jmp = "b0000".U 56 def i2f = "b0001".U 57 def csr = "b0010".U 58 def alu = "b0110".U 59 def mul = "b0100".U 60 def div = "b0101".U 61 def fence = "b0011".U 62 def bku = "b0111".U 63 64 def fmac = "b1000".U 65 def fmisc = "b1011".U 66 def fDivSqrt = "b1010".U 67 68 def ldu = "b1100".U 69 def stu = "b1101".U 70 def mou = "b1111".U // for amo, lr, sc, fence 71 72 def num = 14 73 74 def apply() = UInt(log2Up(num).W) 75 76 def isIntExu(fuType: UInt) = !fuType(3) 77 def isJumpExu(fuType: UInt) = fuType === jmp 78 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 79 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 80 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 81 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 82 def isAMO(fuType: UInt) = fuType(1) 83 def isFence(fuType: UInt) = fuType === fence 84 def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 85 def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 86 def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 87 88 89 def jmpCanAccept(fuType: UInt) = !fuType(2) 90 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 91 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 92 93 def fmacCanAccept(fuType: UInt) = !fuType(1) 94 def fmiscCanAccept(fuType: UInt) = fuType(1) 95 96 def loadCanAccept(fuType: UInt) = !fuType(0) 97 def storeCanAccept(fuType: UInt) = fuType(0) 98 99 def storeIsAMO(fuType: UInt) = fuType(1) 100 101 val functionNameMap = Map( 102 jmp.litValue() -> "jmp", 103 i2f.litValue() -> "int_to_float", 104 csr.litValue() -> "csr", 105 alu.litValue() -> "alu", 106 mul.litValue() -> "mul", 107 div.litValue() -> "div", 108 fence.litValue() -> "fence", 109 bku.litValue() -> "bku", 110 fmac.litValue() -> "fmac", 111 fmisc.litValue() -> "fmisc", 112 fDivSqrt.litValue() -> "fdiv/fsqrt", 113 ldu.litValue() -> "load", 114 stu.litValue() -> "store", 115 mou.litValue() -> "mou" 116 ) 117 } 118 119 object FuOpType { 120 def apply() = UInt(7.W) 121 } 122 123 object CommitType { 124 def NORMAL = "b000".U // int/fp 125 def BRANCH = "b001".U // branch 126 def LOAD = "b010".U // load 127 def STORE = "b011".U // store 128 129 def apply() = UInt(3.W) 130 def isFused(commitType: UInt): Bool = commitType(2) 131 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 132 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 133 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 134 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 135 } 136 137 object RedirectLevel { 138 def flushAfter = "b0".U 139 def flush = "b1".U 140 141 def apply() = UInt(1.W) 142 // def isUnconditional(level: UInt) = level(1) 143 def flushItself(level: UInt) = level(0) 144 // def isException(level: UInt) = level(1) && level(0) 145 } 146 147 object ExceptionVec { 148 def apply() = Vec(16, Bool()) 149 } 150 151 object PMAMode { 152 def R = "b1".U << 0 //readable 153 def W = "b1".U << 1 //writeable 154 def X = "b1".U << 2 //executable 155 def I = "b1".U << 3 //cacheable: icache 156 def D = "b1".U << 4 //cacheable: dcache 157 def S = "b1".U << 5 //enable speculative access 158 def A = "b1".U << 6 //enable atomic operation, A imply R & W 159 def C = "b1".U << 7 //if it is cacheable is configable 160 def Reserved = "b0".U 161 162 def apply() = UInt(7.W) 163 164 def read(mode: UInt) = mode(0) 165 def write(mode: UInt) = mode(1) 166 def execute(mode: UInt) = mode(2) 167 def icache(mode: UInt) = mode(3) 168 def dcache(mode: UInt) = mode(4) 169 def speculate(mode: UInt) = mode(5) 170 def atomic(mode: UInt) = mode(6) 171 def configable_cache(mode: UInt) = mode(7) 172 173 def strToMode(s: String) = { 174 var result = 0.U(8.W) 175 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 176 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 177 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 178 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 179 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 180 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 181 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 182 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 183 result 184 } 185 } 186 187 188 object CSROpType { 189 def jmp = "b000".U 190 def wrt = "b001".U 191 def set = "b010".U 192 def clr = "b011".U 193 def wfi = "b100".U 194 def wrti = "b101".U 195 def seti = "b110".U 196 def clri = "b111".U 197 } 198 199 // jump 200 object JumpOpType { 201 def jal = "b00".U 202 def jalr = "b01".U 203 def auipc = "b10".U 204// def call = "b11_011".U 205// def ret = "b11_100".U 206 def jumpOpisJalr(op: UInt) = op(0) 207 def jumpOpisAuipc(op: UInt) = op(1) 208 } 209 210 object FenceOpType { 211 def fence = "b10000".U 212 def sfence = "b10001".U 213 def fencei = "b10010".U 214 def nofence= "b00000".U 215 } 216 217 object ALUOpType { 218 // shift optype 219 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 220 def sll = "b000_0001".U // sll: src1 << src2 221 222 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 223 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 224 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 225 226 def srl = "b000_0101".U // srl: src1 >> src2 227 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 228 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 229 230 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 231 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 232 233 // RV64 32bit optype 234 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 235 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 236 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 237 238 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 239 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 240 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 241 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 242 243 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 244 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 245 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 246 def rolw = "b001_1100".U 247 def rorw = "b001_1101".U 248 249 // ADD-op 250 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 251 def add = "b010_0001".U // add: src1 + src2 252 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 253 254 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 255 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 256 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 257 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 258 259 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 260 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 261 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 262 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 263 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 264 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 265 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 266 267 // SUB-op: src1 - src2 268 def sub = "b011_0000".U 269 def sltu = "b011_0001".U 270 def slt = "b011_0010".U 271 def maxu = "b011_0100".U 272 def minu = "b011_0101".U 273 def max = "b011_0110".U 274 def min = "b011_0111".U 275 276 // branch 277 def beq = "b111_0000".U 278 def bne = "b111_0010".U 279 def blt = "b111_1000".U 280 def bge = "b111_1010".U 281 def bltu = "b111_1100".U 282 def bgeu = "b111_1110".U 283 284 // misc optype 285 def and = "b100_0000".U 286 def andn = "b100_0001".U 287 def or = "b100_0010".U 288 def orn = "b100_0011".U 289 def xor = "b100_0100".U 290 def xnor = "b100_0101".U 291 def orcb = "b100_0110".U 292 293 def sextb = "b100_1000".U 294 def packh = "b100_1001".U 295 def sexth = "b100_1010".U 296 def packw = "b100_1011".U 297 298 def revb = "b101_0000".U 299 def rev8 = "b101_0001".U 300 def pack = "b101_0010".U 301 def orh48 = "b101_0011".U 302 303 def szewl1 = "b101_1000".U 304 def szewl2 = "b101_1001".U 305 def szewl3 = "b101_1010".U 306 def byte2 = "b101_1011".U 307 308 def andlsb = "b110_0000".U 309 def andzexth = "b110_0001".U 310 def orlsb = "b110_0010".U 311 def orzexth = "b110_0011".U 312 def xorlsb = "b110_0100".U 313 def xorzexth = "b110_0101".U 314 def orcblsb = "b110_0110".U 315 def orcbzexth = "b110_0111".U 316 317 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 318 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 319 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 320 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 321 def isBranch(func: UInt) = func(6, 4) === "b111".U 322 def getBranchType(func: UInt) = func(3, 2) 323 def isBranchInvert(func: UInt) = func(1) 324 325 def apply() = UInt(7.W) 326 } 327 328 object MDUOpType { 329 // mul 330 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 331 def mul = "b00000".U 332 def mulh = "b00001".U 333 def mulhsu = "b00010".U 334 def mulhu = "b00011".U 335 def mulw = "b00100".U 336 337 def mulw7 = "b01100".U 338 339 // div 340 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 341 def div = "b10000".U 342 def divu = "b10010".U 343 def rem = "b10001".U 344 def remu = "b10011".U 345 346 def divw = "b10100".U 347 def divuw = "b10110".U 348 def remw = "b10101".U 349 def remuw = "b10111".U 350 351 def isMul(op: UInt) = !op(4) 352 def isDiv(op: UInt) = op(4) 353 354 def isDivSign(op: UInt) = isDiv(op) && !op(1) 355 def isW(op: UInt) = op(2) 356 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 357 def getMulOp(op: UInt) = op(1, 0) 358 } 359 360 object LSUOpType { 361 // load pipeline 362 363 // normal load 364 // Note: bit(1, 0) are size, DO NOT CHANGE 365 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 366 def lb = "b0000".U 367 def lh = "b0001".U 368 def lw = "b0010".U 369 def ld = "b0011".U 370 def lbu = "b0100".U 371 def lhu = "b0101".U 372 def lwu = "b0110".U 373 374 // Zicbop software prefetch 375 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 376 def prefetch_i = "b1000".U // TODO 377 def prefetch_r = "b1001".U 378 def prefetch_w = "b1010".U 379 380 def isPrefetch(op: UInt): Bool = op(3) 381 382 // store pipeline 383 // normal store 384 // bit encoding: | store 00 | size(2bit) | 385 def sb = "b0000".U 386 def sh = "b0001".U 387 def sw = "b0010".U 388 def sd = "b0011".U 389 390 // l1 cache op 391 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 392 def cbo_zero = "b0111".U 393 394 // llc op 395 // bit encoding: | prefetch 11 | suboptype(2bit) | 396 def cbo_clean = "b1100".U 397 def cbo_flush = "b1101".U 398 def cbo_inval = "b1110".U 399 400 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 401 402 // atomics 403 // bit(1, 0) are size 404 // since atomics use a different fu type 405 // so we can safely reuse other load/store's encodings 406 // bit encoding: | optype(4bit) | size (2bit) | 407 def lr_w = "b000010".U 408 def sc_w = "b000110".U 409 def amoswap_w = "b001010".U 410 def amoadd_w = "b001110".U 411 def amoxor_w = "b010010".U 412 def amoand_w = "b010110".U 413 def amoor_w = "b011010".U 414 def amomin_w = "b011110".U 415 def amomax_w = "b100010".U 416 def amominu_w = "b100110".U 417 def amomaxu_w = "b101010".U 418 419 def lr_d = "b000011".U 420 def sc_d = "b000111".U 421 def amoswap_d = "b001011".U 422 def amoadd_d = "b001111".U 423 def amoxor_d = "b010011".U 424 def amoand_d = "b010111".U 425 def amoor_d = "b011011".U 426 def amomin_d = "b011111".U 427 def amomax_d = "b100011".U 428 def amominu_d = "b100111".U 429 def amomaxu_d = "b101011".U 430 431 def size(op: UInt) = op(1,0) 432 } 433 434 object BKUOpType { 435 436 def clmul = "b000000".U 437 def clmulh = "b000001".U 438 def clmulr = "b000010".U 439 def xpermn = "b000100".U 440 def xpermb = "b000101".U 441 442 def clz = "b001000".U 443 def clzw = "b001001".U 444 def ctz = "b001010".U 445 def ctzw = "b001011".U 446 def cpop = "b001100".U 447 def cpopw = "b001101".U 448 449 // 01xxxx is reserve 450 def aes64es = "b100000".U 451 def aes64esm = "b100001".U 452 def aes64ds = "b100010".U 453 def aes64dsm = "b100011".U 454 def aes64im = "b100100".U 455 def aes64ks1i = "b100101".U 456 def aes64ks2 = "b100110".U 457 458 // merge to two instruction sm4ks & sm4ed 459 def sm4ed0 = "b101000".U 460 def sm4ed1 = "b101001".U 461 def sm4ed2 = "b101010".U 462 def sm4ed3 = "b101011".U 463 def sm4ks0 = "b101100".U 464 def sm4ks1 = "b101101".U 465 def sm4ks2 = "b101110".U 466 def sm4ks3 = "b101111".U 467 468 def sha256sum0 = "b110000".U 469 def sha256sum1 = "b110001".U 470 def sha256sig0 = "b110010".U 471 def sha256sig1 = "b110011".U 472 def sha512sum0 = "b110100".U 473 def sha512sum1 = "b110101".U 474 def sha512sig0 = "b110110".U 475 def sha512sig1 = "b110111".U 476 477 def sm3p0 = "b111000".U 478 def sm3p1 = "b111001".U 479 } 480 481 object BTBtype { 482 def B = "b00".U // branch 483 def J = "b01".U // jump 484 def I = "b10".U // indirect 485 def R = "b11".U // return 486 487 def apply() = UInt(2.W) 488 } 489 490 object SelImm { 491 def IMM_X = "b0111".U 492 def IMM_S = "b0000".U 493 def IMM_SB = "b0001".U 494 def IMM_U = "b0010".U 495 def IMM_UJ = "b0011".U 496 def IMM_I = "b0100".U 497 def IMM_Z = "b0101".U 498 def INVALID_INSTR = "b0110".U 499 def IMM_B6 = "b1000".U 500 501 def apply() = UInt(4.W) 502 } 503 504 object ExceptionNO { 505 def instrAddrMisaligned = 0 506 def instrAccessFault = 1 507 def illegalInstr = 2 508 def breakPoint = 3 509 def loadAddrMisaligned = 4 510 def loadAccessFault = 5 511 def storeAddrMisaligned = 6 512 def storeAccessFault = 7 513 def ecallU = 8 514 def ecallS = 9 515 def ecallM = 11 516 def instrPageFault = 12 517 def loadPageFault = 13 518 // def singleStep = 14 519 def storePageFault = 15 520 def priorities = Seq( 521 breakPoint, // TODO: different BP has different priority 522 instrPageFault, 523 instrAccessFault, 524 illegalInstr, 525 instrAddrMisaligned, 526 ecallM, ecallS, ecallU, 527 storePageFault, 528 loadPageFault, 529 storeAccessFault, 530 loadAccessFault, 531 storeAddrMisaligned, 532 loadAddrMisaligned 533 ) 534 def all = priorities.distinct.sorted 535 def frontendSet = Seq( 536 instrAddrMisaligned, 537 instrAccessFault, 538 illegalInstr, 539 instrPageFault 540 ) 541 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 542 val new_vec = Wire(ExceptionVec()) 543 new_vec.foreach(_ := false.B) 544 select.foreach(i => new_vec(i) := vec(i)) 545 new_vec 546 } 547 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 548 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 549 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 550 partialSelect(vec, fuConfig.exceptionOut) 551 def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 552 partialSelect(vec, exuConfig.exceptionOut) 553 def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 554 partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 555 } 556 557 def dividerGen(p: Parameters) = new SRT16Divider(p(XLen))(p) 558 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 559 def aluGen(p: Parameters) = new Alu()(p) 560 def bkuGen(p: Parameters) = new Bku()(p) 561 def jmpGen(p: Parameters) = new Jump()(p) 562 def fenceGen(p: Parameters) = new Fence()(p) 563 def csrGen(p: Parameters) = new CSR()(p) 564 def i2fGen(p: Parameters) = new IntToFP()(p) 565 def fmacGen(p: Parameters) = new FMA()(p) 566 def f2iGen(p: Parameters) = new FPToInt()(p) 567 def f2fGen(p: Parameters) = new FPToFP()(p) 568 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 569 def stdGen(p: Parameters) = new Std()(p) 570 def mouDataGen(p: Parameters) = new Std()(p) 571 572 def f2iSel(uop: MicroOp): Bool = { 573 uop.ctrl.rfWen 574 } 575 576 def i2fSel(uop: MicroOp): Bool = { 577 uop.ctrl.fpu.fromInt 578 } 579 580 def f2fSel(uop: MicroOp): Bool = { 581 val ctrl = uop.ctrl.fpu 582 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 583 } 584 585 def fdivSqrtSel(uop: MicroOp): Bool = { 586 val ctrl = uop.ctrl.fpu 587 ctrl.div || ctrl.sqrt 588 } 589 590 val aluCfg = FuConfig( 591 name = "alu", 592 fuGen = aluGen, 593 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 594 fuType = FuType.alu, 595 numIntSrc = 2, 596 numFpSrc = 0, 597 writeIntRf = true, 598 writeFpRf = false, 599 hasRedirect = true, 600 ) 601 602 val jmpCfg = FuConfig( 603 name = "jmp", 604 fuGen = jmpGen, 605 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 606 fuType = FuType.jmp, 607 numIntSrc = 1, 608 numFpSrc = 0, 609 writeIntRf = true, 610 writeFpRf = false, 611 hasRedirect = true, 612 ) 613 614 val fenceCfg = FuConfig( 615 name = "fence", 616 fuGen = fenceGen, 617 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 618 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 619 latency = UncertainLatency(), exceptionOut = Seq(illegalInstr) // TODO: need rewrite latency structure, not just this value, 620 ) 621 622 val csrCfg = FuConfig( 623 name = "csr", 624 fuGen = csrGen, 625 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 626 fuType = FuType.csr, 627 numIntSrc = 1, 628 numFpSrc = 0, 629 writeIntRf = true, 630 writeFpRf = false, 631 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 632 flushPipe = true 633 ) 634 635 val i2fCfg = FuConfig( 636 name = "i2f", 637 fuGen = i2fGen, 638 fuSel = i2fSel, 639 FuType.i2f, 640 numIntSrc = 1, 641 numFpSrc = 0, 642 writeIntRf = false, 643 writeFpRf = true, 644 writeFflags = true, 645 latency = CertainLatency(2), 646 fastUopOut = true, fastImplemented = true 647 ) 648 649 val divCfg = FuConfig( 650 name = "div", 651 fuGen = dividerGen, 652 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 653 FuType.div, 654 2, 655 0, 656 writeIntRf = true, 657 writeFpRf = false, 658 latency = UncertainLatency(), 659 fastUopOut = true, 660 fastImplemented = true 661 ) 662 663 val mulCfg = FuConfig( 664 name = "mul", 665 fuGen = multiplierGen, 666 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 667 FuType.mul, 668 2, 669 0, 670 writeIntRf = true, 671 writeFpRf = false, 672 latency = CertainLatency(2), 673 fastUopOut = true, 674 fastImplemented = true 675 ) 676 677 val bkuCfg = FuConfig( 678 name = "bku", 679 fuGen = bkuGen, 680 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 681 fuType = FuType.bku, 682 numIntSrc = 2, 683 numFpSrc = 0, 684 writeIntRf = true, 685 writeFpRf = false, 686 latency = CertainLatency(1), 687 fastUopOut = true, 688 fastImplemented = true 689 ) 690 691 val fmacCfg = FuConfig( 692 name = "fmac", 693 fuGen = fmacGen, 694 fuSel = _ => true.B, 695 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 696 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 697 ) 698 699 val f2iCfg = FuConfig( 700 name = "f2i", 701 fuGen = f2iGen, 702 fuSel = f2iSel, 703 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 704 fastUopOut = true, fastImplemented = true 705 ) 706 707 val f2fCfg = FuConfig( 708 name = "f2f", 709 fuGen = f2fGen, 710 fuSel = f2fSel, 711 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 712 fastUopOut = true, fastImplemented = true 713 ) 714 715 val fdivSqrtCfg = FuConfig( 716 name = "fdivSqrt", 717 fuGen = fdivSqrtGen, 718 fuSel = fdivSqrtSel, 719 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 720 fastUopOut = true, fastImplemented = true, hasInputBuffer = true 721 ) 722 723 val lduCfg = FuConfig( 724 "ldu", 725 null, // DontCare 726 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 727 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 728 latency = UncertainLatency(), 729 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 730 flushPipe = true, 731 replayInst = true 732 ) 733 734 val staCfg = FuConfig( 735 "sta", 736 null, 737 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 738 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 739 latency = UncertainLatency(), 740 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 741 ) 742 743 val stdCfg = FuConfig( 744 "std", 745 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 746 writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 747 ) 748 749 val mouCfg = FuConfig( 750 "mou", 751 null, 752 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 753 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 754 latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 755 ) 756 757 val mouDataCfg = FuConfig( 758 "mou", 759 mouDataGen, 760 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 761 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 762 latency = UncertainLatency() 763 ) 764 765 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 766 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 767 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 768 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 769 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg), Int.MaxValue, 0) 770 val FmiscExeUnitCfg = ExuConfig( 771 "FmiscExeUnit", 772 "Fp", 773 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 774 Int.MaxValue, 1 775 ) 776 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 777 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 778 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 779} 780