1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.backend.fu._ 22import xiangshan.backend.fu.fpu._ 23import xiangshan.backend.exu._ 24import xiangshan.backend.{AmoData, Std} 25 26package object xiangshan { 27 object SrcType { 28 def reg = "b00".U 29 def pc = "b01".U 30 def imm = "b01".U 31 def fp = "b10".U 32 33 def DC = imm // Don't Care 34 35 def isReg(srcType: UInt) = srcType===reg 36 def isPc(srcType: UInt) = srcType===pc 37 def isImm(srcType: UInt) = srcType===imm 38 def isFp(srcType: UInt) = srcType(1) 39 def isPcOrImm(srcType: UInt) = srcType(0) 40 def isRegOrFp(srcType: UInt) = !srcType(0) 41 def regIsFp(srcType: UInt) = srcType(1) 42 43 def apply() = UInt(2.W) 44 } 45 46 object SrcState { 47 def busy = "b0".U 48 def rdy = "b1".U 49 // def specRdy = "b10".U // speculative ready, for future use 50 def apply() = UInt(1.W) 51 } 52 53 object FuType { 54 def jmp = "b0000".U 55 def i2f = "b0001".U 56 def csr = "b0010".U 57 def alu = "b0110".U 58 def mul = "b0100".U 59 def div = "b0101".U 60 def fence = "b0011".U 61 def bku = "b0111".U 62 63 def fmac = "b1000".U 64 def fmisc = "b1011".U 65 def fDivSqrt = "b1010".U 66 67 def ldu = "b1100".U 68 def stu = "b1101".U 69 def mou = "b1111".U // for amo, lr, sc, fence 70 71 def num = 14 72 73 def apply() = UInt(log2Up(num).W) 74 75 def isIntExu(fuType: UInt) = !fuType(3) 76 def isJumpExu(fuType: UInt) = fuType === jmp 77 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 78 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 79 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 80 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 81 def isAMO(fuType: UInt) = fuType(1) 82 def isFence(fuType: UInt) = fuType === fence 83 def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 84 def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 85 def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 86 87 88 def jmpCanAccept(fuType: UInt) = !fuType(2) 89 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 90 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 91 92 def fmacCanAccept(fuType: UInt) = !fuType(1) 93 def fmiscCanAccept(fuType: UInt) = fuType(1) 94 95 def loadCanAccept(fuType: UInt) = !fuType(0) 96 def storeCanAccept(fuType: UInt) = fuType(0) 97 98 def storeIsAMO(fuType: UInt) = fuType(1) 99 100 val functionNameMap = Map( 101 jmp.litValue() -> "jmp", 102 i2f.litValue() -> "int_to_float", 103 csr.litValue() -> "csr", 104 alu.litValue() -> "alu", 105 mul.litValue() -> "mul", 106 div.litValue() -> "div", 107 fence.litValue() -> "fence", 108 bku.litValue() -> "bku", 109 fmac.litValue() -> "fmac", 110 fmisc.litValue() -> "fmisc", 111 fDivSqrt.litValue() -> "fdiv/fsqrt", 112 ldu.litValue() -> "load", 113 stu.litValue() -> "store", 114 mou.litValue() -> "mou" 115 ) 116 } 117 118 object FuOpType { 119 def apply() = UInt(7.W) 120 } 121 122 object CommitType { 123 def NORMAL = "b000".U // int/fp 124 def BRANCH = "b001".U // branch 125 def LOAD = "b010".U // load 126 def STORE = "b011".U // store 127 128 def apply() = UInt(3.W) 129 def isFused(commitType: UInt): Bool = commitType(2) 130 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 131 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 132 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 133 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 134 } 135 136 object RedirectLevel { 137 def flushAfter = "b0".U 138 def flush = "b1".U 139 140 def apply() = UInt(1.W) 141 // def isUnconditional(level: UInt) = level(1) 142 def flushItself(level: UInt) = level(0) 143 // def isException(level: UInt) = level(1) && level(0) 144 } 145 146 object ExceptionVec { 147 def apply() = Vec(16, Bool()) 148 } 149 150 object PMAMode { 151 def R = "b1".U << 0 //readable 152 def W = "b1".U << 1 //writeable 153 def X = "b1".U << 2 //executable 154 def I = "b1".U << 3 //cacheable: icache 155 def D = "b1".U << 4 //cacheable: dcache 156 def S = "b1".U << 5 //enable speculative access 157 def A = "b1".U << 6 //enable atomic operation, A imply R & W 158 def C = "b1".U << 7 //if it is cacheable is configable 159 def Reserved = "b0".U 160 161 def apply() = UInt(7.W) 162 163 def read(mode: UInt) = mode(0) 164 def write(mode: UInt) = mode(1) 165 def execute(mode: UInt) = mode(2) 166 def icache(mode: UInt) = mode(3) 167 def dcache(mode: UInt) = mode(4) 168 def speculate(mode: UInt) = mode(5) 169 def atomic(mode: UInt) = mode(6) 170 def configable_cache(mode: UInt) = mode(7) 171 172 def strToMode(s: String) = { 173 var result = 0.U(8.W) 174 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 175 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 176 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 177 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 178 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 179 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 180 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 181 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 182 result 183 } 184 } 185 186 187 object CSROpType { 188 def jmp = "b000".U 189 def wrt = "b001".U 190 def set = "b010".U 191 def clr = "b011".U 192 def wrti = "b101".U 193 def seti = "b110".U 194 def clri = "b111".U 195 } 196 197 // jump 198 object JumpOpType { 199 def jal = "b00".U 200 def jalr = "b01".U 201 def auipc = "b10".U 202// def call = "b11_011".U 203// def ret = "b11_100".U 204 def jumpOpisJalr(op: UInt) = op(0) 205 def jumpOpisAuipc(op: UInt) = op(1) 206 } 207 208 object FenceOpType { 209 def fence = "b10000".U 210 def sfence = "b10001".U 211 def fencei = "b10010".U 212 def nofence= "b00000".U 213 } 214 215 object ALUOpType { 216 // shift optype 217 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 218 def sll = "b000_0001".U // sll: src1 << src2 219 220 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 221 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 222 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 223 224 def srl = "b000_0101".U // srl: src1 >> src2 225 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 226 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 227 228 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 229 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 230 231 // RV64 32bit optype 232 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 233 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 234 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 235 236 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 237 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 238 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 239 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 240 241 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 242 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 243 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 244 def rolw = "b001_1100".U 245 def rorw = "b001_1101".U 246 247 // ADD-op 248 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 249 def add = "b010_0001".U // add: src1 + src2 250 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 251 252 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 253 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 254 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 255 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 256 257 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 258 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 259 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 260 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 261 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 262 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 263 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 264 265 // SUB-op: src1 - src2 266 def sub = "b011_0000".U 267 def sltu = "b011_0001".U 268 def slt = "b011_0010".U 269 def maxu = "b011_0100".U 270 def minu = "b011_0101".U 271 def max = "b011_0110".U 272 def min = "b011_0111".U 273 274 // branch 275 def beq = "b111_0000".U 276 def bne = "b111_0010".U 277 def blt = "b111_1000".U 278 def bge = "b111_1010".U 279 def bltu = "b111_1100".U 280 def bgeu = "b111_1110".U 281 282 // misc optype 283 def and = "b100_0000".U 284 def andn = "b100_0001".U 285 def or = "b100_0010".U 286 def orn = "b100_0011".U 287 def xor = "b100_0100".U 288 def xnor = "b100_0101".U 289 def orcb = "b100_0110".U 290 291 def sextb = "b100_1000".U 292 def packh = "b100_1001".U 293 def sexth = "b100_1010".U 294 def packw = "b100_1011".U 295 296 def revb = "b101_0000".U 297 def rev8 = "b101_0001".U 298 def pack = "b101_0010".U 299 def orh48 = "b101_0011".U 300 301 def szewl1 = "b101_1000".U 302 def szewl2 = "b101_1001".U 303 def szewl3 = "b101_1010".U 304 def byte2 = "b101_1011".U 305 306 def andlsb = "b110_0000".U 307 def andzexth = "b110_0001".U 308 def orlsb = "b110_0010".U 309 def orzexth = "b110_0011".U 310 def xorlsb = "b110_0100".U 311 def xorzexth = "b110_0101".U 312 def orcblsb = "b110_0110".U 313 def orcbzexth = "b110_0111".U 314 315 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 316 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 317 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 318 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 319 def isBranch(func: UInt) = func(6, 4) === "b111".U 320 def getBranchType(func: UInt) = func(3, 2) 321 def isBranchInvert(func: UInt) = func(1) 322 323 def apply() = UInt(7.W) 324 } 325 326 object MDUOpType { 327 // mul 328 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 329 def mul = "b00000".U 330 def mulh = "b00001".U 331 def mulhsu = "b00010".U 332 def mulhu = "b00011".U 333 def mulw = "b00100".U 334 335 def mulw7 = "b01100".U 336 337 // div 338 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 339 def div = "b10000".U 340 def divu = "b10010".U 341 def rem = "b10001".U 342 def remu = "b10011".U 343 344 def divw = "b10100".U 345 def divuw = "b10110".U 346 def remw = "b10101".U 347 def remuw = "b10111".U 348 349 def isMul(op: UInt) = !op(4) 350 def isDiv(op: UInt) = op(4) 351 352 def isDivSign(op: UInt) = isDiv(op) && !op(1) 353 def isW(op: UInt) = op(2) 354 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 355 def getMulOp(op: UInt) = op(1, 0) 356 } 357 358 object LSUOpType { 359 // normal load/store 360 // bit(1, 0) are size 361 def lb = "b000000".U 362 def lh = "b000001".U 363 def lw = "b000010".U 364 def ld = "b000011".U 365 def lbu = "b000100".U 366 def lhu = "b000101".U 367 def lwu = "b000110".U 368 def sb = "b001000".U 369 def sh = "b001001".U 370 def sw = "b001010".U 371 def sd = "b001011".U 372 373 def cbo_zero = "b001111".U // l1 cache op 374 375 def cbo_clean = "b011111".U // llc op 376 def cbo_flush = "b101111".U // llc op 377 def cbo_inval = "b111111".U // llc op 378 379 def isLoad(op: UInt): Bool = !op(3) 380 def isStore(op: UInt): Bool = op(3) 381 def isCbo(op: UInt): Bool = op(3, 0) === "b1111".U 382 383 // atomics 384 // bit(1, 0) are size 385 // since atomics use a different fu type 386 // so we can safely reuse other load/store's encodings 387 def lr_w = "b000010".U 388 def sc_w = "b000110".U 389 def amoswap_w = "b001010".U 390 def amoadd_w = "b001110".U 391 def amoxor_w = "b010010".U 392 def amoand_w = "b010110".U 393 def amoor_w = "b011010".U 394 def amomin_w = "b011110".U 395 def amomax_w = "b100010".U 396 def amominu_w = "b100110".U 397 def amomaxu_w = "b101010".U 398 399 def lr_d = "b000011".U 400 def sc_d = "b000111".U 401 def amoswap_d = "b001011".U 402 def amoadd_d = "b001111".U 403 def amoxor_d = "b010011".U 404 def amoand_d = "b010111".U 405 def amoor_d = "b011011".U 406 def amomin_d = "b011111".U 407 def amomax_d = "b100011".U 408 def amominu_d = "b100111".U 409 def amomaxu_d = "b101011".U 410 411 def size(op: UInt) = op(1,0) 412 } 413 414 object BKUOpType { 415 416 def clmul = "b000000".U 417 def clmulh = "b000001".U 418 def clmulr = "b000010".U 419 def xpermn = "b000100".U 420 def xpermb = "b000101".U 421 422 def clz = "b001000".U 423 def clzw = "b001001".U 424 def ctz = "b001010".U 425 def ctzw = "b001011".U 426 def cpop = "b001100".U 427 def cpopw = "b001101".U 428 429 // 01xxxx is reserve 430 def aes64es = "b100000".U 431 def aes64esm = "b100001".U 432 def aes64ds = "b100010".U 433 def aes64dsm = "b100011".U 434 def aes64im = "b100100".U 435 def aes64ks1i = "b100101".U 436 def aes64ks2 = "b100110".U 437 438 // merge to two instruction sm4ks & sm4ed 439 def sm4ks0 = "b101000".U 440 def sm4ks1 = "b101001".U 441 def sm4ks2 = "b101010".U 442 def sm4ks3 = "b101011".U 443 def sm4ed0 = "b101100".U 444 def sm4ed1 = "b101101".U 445 def sm4ed2 = "b101110".U 446 def sm4ed3 = "b101111".U 447 448 def sha256sum0 = "b110000".U 449 def sha256sum1 = "b110001".U 450 def sha256sig0 = "b110010".U 451 def sha256sig1 = "b110011".U 452 def sha512sum0 = "b110100".U 453 def sha512sum1 = "b110101".U 454 def sha512sig0 = "b110110".U 455 def sha512sig1 = "b110111".U 456 457 def sm3p0 = "b111000".U 458 def sm3p1 = "b111001".U 459 } 460 461 object BTBtype { 462 def B = "b00".U // branch 463 def J = "b01".U // jump 464 def I = "b10".U // indirect 465 def R = "b11".U // return 466 467 def apply() = UInt(2.W) 468 } 469 470 object SelImm { 471 def IMM_X = "b0111".U 472 def IMM_S = "b0000".U 473 def IMM_SB = "b0001".U 474 def IMM_U = "b0010".U 475 def IMM_UJ = "b0011".U 476 def IMM_I = "b0100".U 477 def IMM_Z = "b0101".U 478 def INVALID_INSTR = "b0110".U 479 def IMM_B6 = "b1000".U 480 481 def apply() = UInt(4.W) 482 } 483 484 def dividerGen(p: Parameters) = new SRT16Divider(p(XLen))(p) 485 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 486 def aluGen(p: Parameters) = new Alu()(p) 487 def bkuGen(p: Parameters) = new Bku()(p) 488 def jmpGen(p: Parameters) = new Jump()(p) 489 def fenceGen(p: Parameters) = new Fence()(p) 490 def csrGen(p: Parameters) = new CSR()(p) 491 def i2fGen(p: Parameters) = new IntToFP()(p) 492 def fmacGen(p: Parameters) = new FMA()(p) 493 def f2iGen(p: Parameters) = new FPToInt()(p) 494 def f2fGen(p: Parameters) = new FPToFP()(p) 495 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 496 def stdGen(p: Parameters) = new Std()(p) 497 def mouDataGen(p: Parameters) = new AmoData()(p) 498 499 def f2iSel(uop: MicroOp): Bool = { 500 uop.ctrl.rfWen 501 } 502 503 def i2fSel(uop: MicroOp): Bool = { 504 uop.ctrl.fpu.fromInt 505 } 506 507 def f2fSel(uop: MicroOp): Bool = { 508 val ctrl = uop.ctrl.fpu 509 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 510 } 511 512 def fdivSqrtSel(uop: MicroOp): Bool = { 513 val ctrl = uop.ctrl.fpu 514 ctrl.div || ctrl.sqrt 515 } 516 517 val aluCfg = FuConfig( 518 name = "alu", 519 fuGen = aluGen, 520 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 521 fuType = FuType.alu, 522 numIntSrc = 2, 523 numFpSrc = 0, 524 writeIntRf = true, 525 writeFpRf = false, 526 hasRedirect = true, 527 ) 528 529 val jmpCfg = FuConfig( 530 name = "jmp", 531 fuGen = jmpGen, 532 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 533 fuType = FuType.jmp, 534 numIntSrc = 1, 535 numFpSrc = 0, 536 writeIntRf = true, 537 writeFpRf = false, 538 hasRedirect = true, 539 ) 540 541 val fenceCfg = FuConfig( 542 name = "fence", 543 fuGen = fenceGen, 544 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 545 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 546 latency = UncertainLatency(), // TODO: need rewrite latency structure, not just this value, 547 hasExceptionOut = true 548 ) 549 550 val csrCfg = FuConfig( 551 name = "csr", 552 fuGen = csrGen, 553 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 554 fuType = FuType.csr, 555 numIntSrc = 1, 556 numFpSrc = 0, 557 writeIntRf = true, 558 writeFpRf = false, 559 hasRedirect = false, 560 hasExceptionOut = true 561 ) 562 563 val i2fCfg = FuConfig( 564 name = "i2f", 565 fuGen = i2fGen, 566 fuSel = i2fSel, 567 FuType.i2f, 568 numIntSrc = 1, 569 numFpSrc = 0, 570 writeIntRf = false, 571 writeFpRf = true, 572 hasRedirect = false, 573 latency = CertainLatency(2), 574 fastUopOut = true, fastImplemented = true 575 ) 576 577 val divCfg = FuConfig( 578 name = "div", 579 fuGen = dividerGen, 580 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 581 FuType.div, 582 2, 583 0, 584 writeIntRf = true, 585 writeFpRf = false, 586 hasRedirect = false, 587 latency = UncertainLatency(), 588 fastUopOut = true, 589 fastImplemented = false 590 ) 591 592 val mulCfg = FuConfig( 593 name = "mul", 594 fuGen = multiplierGen, 595 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 596 FuType.mul, 597 2, 598 0, 599 writeIntRf = true, 600 writeFpRf = false, 601 hasRedirect = false, 602 latency = CertainLatency(2), 603 fastUopOut = true, 604 fastImplemented = true 605 ) 606 607 val bkuCfg = FuConfig( 608 name = "bku", 609 fuGen = bkuGen, 610 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 611 fuType = FuType.bku, 612 numIntSrc = 2, 613 numFpSrc = 0, 614 writeIntRf = true, 615 writeFpRf = false, 616 hasRedirect = false, 617 latency = CertainLatency(1), 618 fastUopOut = true, 619 fastImplemented = true 620 ) 621 622 val fmacCfg = FuConfig( 623 name = "fmac", 624 fuGen = fmacGen, 625 fuSel = _ => true.B, 626 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, hasRedirect = false, 627 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 628 ) 629 630 val f2iCfg = FuConfig( 631 name = "f2i", 632 fuGen = f2iGen, 633 fuSel = f2iSel, 634 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, hasRedirect = false, CertainLatency(2), 635 fastUopOut = true, fastImplemented = true 636 ) 637 638 val f2fCfg = FuConfig( 639 name = "f2f", 640 fuGen = f2fGen, 641 fuSel = f2fSel, 642 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, hasRedirect = false, CertainLatency(2), 643 fastUopOut = true, fastImplemented = true 644 ) 645 646 val fdivSqrtCfg = FuConfig( 647 name = "fdivSqrt", 648 fuGen = fdivSqrtGen, 649 fuSel = fdivSqrtSel, 650 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false, UncertainLatency(), 651 fastUopOut = true, fastImplemented = false, hasInputBuffer = true 652 ) 653 654 val lduCfg = FuConfig( 655 "ldu", 656 null, // DontCare 657 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 658 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, hasRedirect = false, 659 latency = UncertainLatency(), hasExceptionOut = true 660 ) 661 662 val staCfg = FuConfig( 663 "sta", 664 null, 665 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 666 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 667 latency = UncertainLatency(), hasExceptionOut = true 668 ) 669 670 val stdCfg = FuConfig( 671 "std", 672 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 673 writeIntRf = false, writeFpRf = false, hasRedirect = false, latency = CertainLatency(1) 674 ) 675 676 val mouCfg = FuConfig( 677 "mou", 678 null, 679 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 680 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 681 latency = UncertainLatency(), hasExceptionOut = true 682 ) 683 684 val mouDataCfg = FuConfig( 685 "mou", 686 mouDataGen, 687 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 688 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 689 latency = UncertainLatency(), hasExceptionOut = true 690 ) 691 692 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 693 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 694 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 695 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 696 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg), Int.MaxValue, 0) 697 val FmiscExeUnitCfg = ExuConfig( 698 "FmiscExeUnit", 699 "Fp", 700 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 701 Int.MaxValue, 1 702 ) 703 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 704 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 705 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 706} 707