1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.issue._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.exu._ 26import xiangshan.backend.{Std, ScheLaneConfig} 27 28package object xiangshan { 29 object SrcType { 30 def imm = "b000".U 31 def pc = "b000".U 32 def xp = "b001".U 33 def fp = "b010".U 34 def vp = "b100".U 35 36 // alias 37 def reg = this.xp 38 def DC = imm // Don't Care 39 def X = BitPat("b???") 40 41 def isPc(srcType: UInt) = srcType===pc 42 def isImm(srcType: UInt) = srcType===imm 43 def isReg(srcType: UInt) = srcType(0) 44 def isFp(srcType: UInt) = srcType(1) 45 def isVp(srcType: UInt) = srcType(2) 46 def isPcOrImm(srcType: UInt) = isPc(srcType) || isImm(srcType) 47 48 def apply() = UInt(3.W) 49 } 50 51 object SrcState { 52 def busy = "b0".U 53 def rdy = "b1".U 54 // def specRdy = "b10".U // speculative ready, for future use 55 def apply() = UInt(1.W) 56 } 57 58 object FuType { 59 def jmp = "b0000".U 60 def i2f = "b0001".U 61 def csr = "b0010".U 62 def alu = "b0110".U 63 def mul = "b0100".U 64 def div = "b0101".U 65 def fence = "b0011".U 66 def bku = "b0111".U 67 68 def fmac = "b1000".U 69 def fmisc = "b1011".U 70 def fDivSqrt = "b1010".U 71 72 def ldu = "b1100".U 73 def stu = "b1101".U 74 def mou = "b1111".U // for amo, lr, sc, fence 75 76 def X = BitPat("b????") 77 78 def num = 14 79 80 def apply() = UInt(log2Up(num).W) 81 82 def isIntExu(fuType: UInt) = !fuType(3) 83 def isJumpExu(fuType: UInt) = fuType === jmp 84 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 85 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 86 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 87 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 88 def isAMO(fuType: UInt) = fuType(1) 89 def isFence(fuType: UInt) = fuType === fence 90 def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 91 def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 92 def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 93 94 95 def jmpCanAccept(fuType: UInt) = !fuType(2) 96 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 97 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 98 99 def fmacCanAccept(fuType: UInt) = !fuType(1) 100 def fmiscCanAccept(fuType: UInt) = fuType(1) 101 102 def loadCanAccept(fuType: UInt) = !fuType(0) 103 def storeCanAccept(fuType: UInt) = fuType(0) 104 105 def storeIsAMO(fuType: UInt) = fuType(1) 106 107 val functionNameMap = Map( 108 jmp.litValue() -> "jmp", 109 i2f.litValue() -> "int_to_float", 110 csr.litValue() -> "csr", 111 alu.litValue() -> "alu", 112 mul.litValue() -> "mul", 113 div.litValue() -> "div", 114 fence.litValue() -> "fence", 115 bku.litValue() -> "bku", 116 fmac.litValue() -> "fmac", 117 fmisc.litValue() -> "fmisc", 118 fDivSqrt.litValue() -> "fdiv_fsqrt", 119 ldu.litValue() -> "load", 120 stu.litValue() -> "store", 121 mou.litValue() -> "mou" 122 ) 123 } 124 125 object FuOpType { 126 def apply() = UInt(7.W) 127 def X = BitPat("b???????") 128 } 129 130 object CommitType { 131 def NORMAL = "b000".U // int/fp 132 def BRANCH = "b001".U // branch 133 def LOAD = "b010".U // load 134 def STORE = "b011".U // store 135 136 def apply() = UInt(3.W) 137 def isFused(commitType: UInt): Bool = commitType(2) 138 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 139 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 140 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 141 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 142 } 143 144 object RedirectLevel { 145 def flushAfter = "b0".U 146 def flush = "b1".U 147 148 def apply() = UInt(1.W) 149 // def isUnconditional(level: UInt) = level(1) 150 def flushItself(level: UInt) = level(0) 151 // def isException(level: UInt) = level(1) && level(0) 152 } 153 154 object ExceptionVec { 155 def apply() = Vec(16, Bool()) 156 } 157 158 object PMAMode { 159 def R = "b1".U << 0 //readable 160 def W = "b1".U << 1 //writeable 161 def X = "b1".U << 2 //executable 162 def I = "b1".U << 3 //cacheable: icache 163 def D = "b1".U << 4 //cacheable: dcache 164 def S = "b1".U << 5 //enable speculative access 165 def A = "b1".U << 6 //enable atomic operation, A imply R & W 166 def C = "b1".U << 7 //if it is cacheable is configable 167 def Reserved = "b0".U 168 169 def apply() = UInt(7.W) 170 171 def read(mode: UInt) = mode(0) 172 def write(mode: UInt) = mode(1) 173 def execute(mode: UInt) = mode(2) 174 def icache(mode: UInt) = mode(3) 175 def dcache(mode: UInt) = mode(4) 176 def speculate(mode: UInt) = mode(5) 177 def atomic(mode: UInt) = mode(6) 178 def configable_cache(mode: UInt) = mode(7) 179 180 def strToMode(s: String) = { 181 var result = 0.U(8.W) 182 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 183 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 184 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 185 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 186 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 187 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 188 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 189 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 190 result 191 } 192 } 193 194 195 object CSROpType { 196 def jmp = "b000".U 197 def wrt = "b001".U 198 def set = "b010".U 199 def clr = "b011".U 200 def wfi = "b100".U 201 def wrti = "b101".U 202 def seti = "b110".U 203 def clri = "b111".U 204 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 205 } 206 207 // jump 208 object JumpOpType { 209 def jal = "b00".U 210 def jalr = "b01".U 211 def auipc = "b10".U 212// def call = "b11_011".U 213// def ret = "b11_100".U 214 def jumpOpisJalr(op: UInt) = op(0) 215 def jumpOpisAuipc(op: UInt) = op(1) 216 } 217 218 object FenceOpType { 219 def fence = "b10000".U 220 def sfence = "b10001".U 221 def fencei = "b10010".U 222 def nofence= "b00000".U 223 } 224 225 object ALUOpType { 226 // shift optype 227 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 228 def sll = "b000_0001".U // sll: src1 << src2 229 230 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 231 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 232 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 233 234 def srl = "b000_0101".U // srl: src1 >> src2 235 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 236 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 237 238 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 239 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 240 241 // RV64 32bit optype 242 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 243 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 244 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 245 246 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 247 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 248 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 249 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 250 251 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 252 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 253 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 254 def rolw = "b001_1100".U 255 def rorw = "b001_1101".U 256 257 // ADD-op 258 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 259 def add = "b010_0001".U // add: src1 + src2 260 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 261 262 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 263 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 264 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 265 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 266 267 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 268 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 269 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 270 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 271 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 272 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 273 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 274 275 // SUB-op: src1 - src2 276 def sub = "b011_0000".U 277 def sltu = "b011_0001".U 278 def slt = "b011_0010".U 279 def maxu = "b011_0100".U 280 def minu = "b011_0101".U 281 def max = "b011_0110".U 282 def min = "b011_0111".U 283 284 // branch 285 def beq = "b111_0000".U 286 def bne = "b111_0010".U 287 def blt = "b111_1000".U 288 def bge = "b111_1010".U 289 def bltu = "b111_1100".U 290 def bgeu = "b111_1110".U 291 292 // misc optype 293 def and = "b100_0000".U 294 def andn = "b100_0001".U 295 def or = "b100_0010".U 296 def orn = "b100_0011".U 297 def xor = "b100_0100".U 298 def xnor = "b100_0101".U 299 def orcb = "b100_0110".U 300 301 def sextb = "b100_1000".U 302 def packh = "b100_1001".U 303 def sexth = "b100_1010".U 304 def packw = "b100_1011".U 305 306 def revb = "b101_0000".U 307 def rev8 = "b101_0001".U 308 def pack = "b101_0010".U 309 def orh48 = "b101_0011".U 310 311 def szewl1 = "b101_1000".U 312 def szewl2 = "b101_1001".U 313 def szewl3 = "b101_1010".U 314 def byte2 = "b101_1011".U 315 316 def andlsb = "b110_0000".U 317 def andzexth = "b110_0001".U 318 def orlsb = "b110_0010".U 319 def orzexth = "b110_0011".U 320 def xorlsb = "b110_0100".U 321 def xorzexth = "b110_0101".U 322 def orcblsb = "b110_0110".U 323 def orcbzexth = "b110_0111".U 324 325 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 326 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 327 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 328 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 329 def isBranch(func: UInt) = func(6, 4) === "b111".U 330 def getBranchType(func: UInt) = func(3, 2) 331 def isBranchInvert(func: UInt) = func(1) 332 333 def apply() = UInt(7.W) 334 } 335 336 object MDUOpType { 337 // mul 338 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 339 def mul = "b00000".U 340 def mulh = "b00001".U 341 def mulhsu = "b00010".U 342 def mulhu = "b00011".U 343 def mulw = "b00100".U 344 345 def mulw7 = "b01100".U 346 347 // div 348 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 349 def div = "b10000".U 350 def divu = "b10010".U 351 def rem = "b10001".U 352 def remu = "b10011".U 353 354 def divw = "b10100".U 355 def divuw = "b10110".U 356 def remw = "b10101".U 357 def remuw = "b10111".U 358 359 def isMul(op: UInt) = !op(4) 360 def isDiv(op: UInt) = op(4) 361 362 def isDivSign(op: UInt) = isDiv(op) && !op(1) 363 def isW(op: UInt) = op(2) 364 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 365 def getMulOp(op: UInt) = op(1, 0) 366 } 367 368 object LSUOpType { 369 // load pipeline 370 371 // normal load 372 // Note: bit(1, 0) are size, DO NOT CHANGE 373 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 374 def lb = "b0000".U 375 def lh = "b0001".U 376 def lw = "b0010".U 377 def ld = "b0011".U 378 def lbu = "b0100".U 379 def lhu = "b0101".U 380 def lwu = "b0110".U 381 382 // Zicbop software prefetch 383 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 384 def prefetch_i = "b1000".U // TODO 385 def prefetch_r = "b1001".U 386 def prefetch_w = "b1010".U 387 388 def isPrefetch(op: UInt): Bool = op(3) 389 390 // store pipeline 391 // normal store 392 // bit encoding: | store 00 | size(2bit) | 393 def sb = "b0000".U 394 def sh = "b0001".U 395 def sw = "b0010".U 396 def sd = "b0011".U 397 398 // l1 cache op 399 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 400 def cbo_zero = "b0111".U 401 402 // llc op 403 // bit encoding: | prefetch 11 | suboptype(2bit) | 404 def cbo_clean = "b1100".U 405 def cbo_flush = "b1101".U 406 def cbo_inval = "b1110".U 407 408 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 409 410 // atomics 411 // bit(1, 0) are size 412 // since atomics use a different fu type 413 // so we can safely reuse other load/store's encodings 414 // bit encoding: | optype(4bit) | size (2bit) | 415 def lr_w = "b000010".U 416 def sc_w = "b000110".U 417 def amoswap_w = "b001010".U 418 def amoadd_w = "b001110".U 419 def amoxor_w = "b010010".U 420 def amoand_w = "b010110".U 421 def amoor_w = "b011010".U 422 def amomin_w = "b011110".U 423 def amomax_w = "b100010".U 424 def amominu_w = "b100110".U 425 def amomaxu_w = "b101010".U 426 427 def lr_d = "b000011".U 428 def sc_d = "b000111".U 429 def amoswap_d = "b001011".U 430 def amoadd_d = "b001111".U 431 def amoxor_d = "b010011".U 432 def amoand_d = "b010111".U 433 def amoor_d = "b011011".U 434 def amomin_d = "b011111".U 435 def amomax_d = "b100011".U 436 def amominu_d = "b100111".U 437 def amomaxu_d = "b101011".U 438 439 def size(op: UInt) = op(1,0) 440 } 441 442 object BKUOpType { 443 444 def clmul = "b000000".U 445 def clmulh = "b000001".U 446 def clmulr = "b000010".U 447 def xpermn = "b000100".U 448 def xpermb = "b000101".U 449 450 def clz = "b001000".U 451 def clzw = "b001001".U 452 def ctz = "b001010".U 453 def ctzw = "b001011".U 454 def cpop = "b001100".U 455 def cpopw = "b001101".U 456 457 // 01xxxx is reserve 458 def aes64es = "b100000".U 459 def aes64esm = "b100001".U 460 def aes64ds = "b100010".U 461 def aes64dsm = "b100011".U 462 def aes64im = "b100100".U 463 def aes64ks1i = "b100101".U 464 def aes64ks2 = "b100110".U 465 466 // merge to two instruction sm4ks & sm4ed 467 def sm4ed0 = "b101000".U 468 def sm4ed1 = "b101001".U 469 def sm4ed2 = "b101010".U 470 def sm4ed3 = "b101011".U 471 def sm4ks0 = "b101100".U 472 def sm4ks1 = "b101101".U 473 def sm4ks2 = "b101110".U 474 def sm4ks3 = "b101111".U 475 476 def sha256sum0 = "b110000".U 477 def sha256sum1 = "b110001".U 478 def sha256sig0 = "b110010".U 479 def sha256sig1 = "b110011".U 480 def sha512sum0 = "b110100".U 481 def sha512sum1 = "b110101".U 482 def sha512sig0 = "b110110".U 483 def sha512sig1 = "b110111".U 484 485 def sm3p0 = "b111000".U 486 def sm3p1 = "b111001".U 487 } 488 489 object BTBtype { 490 def B = "b00".U // branch 491 def J = "b01".U // jump 492 def I = "b10".U // indirect 493 def R = "b11".U // return 494 495 def apply() = UInt(2.W) 496 } 497 498 object SelImm { 499 def IMM_X = "b0111".U 500 def IMM_S = "b0000".U 501 def IMM_SB = "b0001".U 502 def IMM_U = "b0010".U 503 def IMM_UJ = "b0011".U 504 def IMM_I = "b0100".U 505 def IMM_Z = "b0101".U 506 def INVALID_INSTR = "b0110".U 507 def IMM_B6 = "b1000".U 508 509 def X = BitPat("b????") 510 511 def apply() = UInt(4.W) 512 } 513 514 object ExceptionNO { 515 def instrAddrMisaligned = 0 516 def instrAccessFault = 1 517 def illegalInstr = 2 518 def breakPoint = 3 519 def loadAddrMisaligned = 4 520 def loadAccessFault = 5 521 def storeAddrMisaligned = 6 522 def storeAccessFault = 7 523 def ecallU = 8 524 def ecallS = 9 525 def ecallM = 11 526 def instrPageFault = 12 527 def loadPageFault = 13 528 // def singleStep = 14 529 def storePageFault = 15 530 def priorities = Seq( 531 breakPoint, // TODO: different BP has different priority 532 instrPageFault, 533 instrAccessFault, 534 illegalInstr, 535 instrAddrMisaligned, 536 ecallM, ecallS, ecallU, 537 storeAddrMisaligned, 538 loadAddrMisaligned, 539 storePageFault, 540 loadPageFault, 541 storeAccessFault, 542 loadAccessFault 543 ) 544 def all = priorities.distinct.sorted 545 def frontendSet = Seq( 546 instrAddrMisaligned, 547 instrAccessFault, 548 illegalInstr, 549 instrPageFault 550 ) 551 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 552 val new_vec = Wire(ExceptionVec()) 553 new_vec.foreach(_ := false.B) 554 select.foreach(i => new_vec(i) := vec(i)) 555 new_vec 556 } 557 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 558 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 559 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 560 partialSelect(vec, fuConfig.exceptionOut) 561 def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 562 partialSelect(vec, exuConfig.exceptionOut) 563 def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 564 partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 565 } 566 567 def dividerGen(p: Parameters) = new DividerWrapper(p(XLen))(p) 568 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 569 def aluGen(p: Parameters) = new Alu()(p) 570 def bkuGen(p: Parameters) = new Bku()(p) 571 def jmpGen(p: Parameters) = new Jump()(p) 572 def fenceGen(p: Parameters) = new Fence()(p) 573 def csrGen(p: Parameters) = new CSR()(p) 574 def i2fGen(p: Parameters) = new IntToFP()(p) 575 def fmacGen(p: Parameters) = new FMA()(p) 576 def f2iGen(p: Parameters) = new FPToInt()(p) 577 def f2fGen(p: Parameters) = new FPToFP()(p) 578 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 579 def stdGen(p: Parameters) = new Std()(p) 580 def mouDataGen(p: Parameters) = new Std()(p) 581 582 def f2iSel(uop: MicroOp): Bool = { 583 uop.ctrl.rfWen 584 } 585 586 def i2fSel(uop: MicroOp): Bool = { 587 uop.ctrl.fpu.fromInt 588 } 589 590 def f2fSel(uop: MicroOp): Bool = { 591 val ctrl = uop.ctrl.fpu 592 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 593 } 594 595 def fdivSqrtSel(uop: MicroOp): Bool = { 596 val ctrl = uop.ctrl.fpu 597 ctrl.div || ctrl.sqrt 598 } 599 600 val aluCfg = FuConfig( 601 name = "alu", 602 fuGen = aluGen, 603 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 604 fuType = FuType.alu, 605 numIntSrc = 2, 606 numFpSrc = 0, 607 writeIntRf = true, 608 writeFpRf = false, 609 hasRedirect = true, 610 ) 611 612 val jmpCfg = FuConfig( 613 name = "jmp", 614 fuGen = jmpGen, 615 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 616 fuType = FuType.jmp, 617 numIntSrc = 1, 618 numFpSrc = 0, 619 writeIntRf = true, 620 writeFpRf = false, 621 hasRedirect = true, 622 ) 623 624 val fenceCfg = FuConfig( 625 name = "fence", 626 fuGen = fenceGen, 627 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 628 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 629 latency = UncertainLatency(), exceptionOut = Seq(illegalInstr), // TODO: need rewrite latency structure, not just this value, 630 flushPipe = true 631 ) 632 633 val csrCfg = FuConfig( 634 name = "csr", 635 fuGen = csrGen, 636 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 637 fuType = FuType.csr, 638 numIntSrc = 1, 639 numFpSrc = 0, 640 writeIntRf = true, 641 writeFpRf = false, 642 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 643 flushPipe = true 644 ) 645 646 val i2fCfg = FuConfig( 647 name = "i2f", 648 fuGen = i2fGen, 649 fuSel = i2fSel, 650 FuType.i2f, 651 numIntSrc = 1, 652 numFpSrc = 0, 653 writeIntRf = false, 654 writeFpRf = true, 655 writeFflags = true, 656 latency = CertainLatency(2), 657 fastUopOut = true, fastImplemented = true 658 ) 659 660 val divCfg = FuConfig( 661 name = "div", 662 fuGen = dividerGen, 663 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 664 FuType.div, 665 2, 666 0, 667 writeIntRf = true, 668 writeFpRf = false, 669 latency = UncertainLatency(), 670 fastUopOut = true, 671 fastImplemented = true, 672 hasInputBuffer = (true, 4, true) 673 ) 674 675 val mulCfg = FuConfig( 676 name = "mul", 677 fuGen = multiplierGen, 678 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 679 FuType.mul, 680 2, 681 0, 682 writeIntRf = true, 683 writeFpRf = false, 684 latency = CertainLatency(2), 685 fastUopOut = true, 686 fastImplemented = true 687 ) 688 689 val bkuCfg = FuConfig( 690 name = "bku", 691 fuGen = bkuGen, 692 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 693 fuType = FuType.bku, 694 numIntSrc = 2, 695 numFpSrc = 0, 696 writeIntRf = true, 697 writeFpRf = false, 698 latency = CertainLatency(1), 699 fastUopOut = true, 700 fastImplemented = true 701 ) 702 703 val fmacCfg = FuConfig( 704 name = "fmac", 705 fuGen = fmacGen, 706 fuSel = _ => true.B, 707 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 708 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 709 ) 710 711 val f2iCfg = FuConfig( 712 name = "f2i", 713 fuGen = f2iGen, 714 fuSel = f2iSel, 715 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 716 fastUopOut = true, fastImplemented = true 717 ) 718 719 val f2fCfg = FuConfig( 720 name = "f2f", 721 fuGen = f2fGen, 722 fuSel = f2fSel, 723 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 724 fastUopOut = true, fastImplemented = true 725 ) 726 727 val fdivSqrtCfg = FuConfig( 728 name = "fdivSqrt", 729 fuGen = fdivSqrtGen, 730 fuSel = fdivSqrtSel, 731 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 732 fastUopOut = true, fastImplemented = true, hasInputBuffer = (true, 8, true) 733 ) 734 735 val lduCfg = FuConfig( 736 "ldu", 737 null, // DontCare 738 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 739 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 740 latency = UncertainLatency(), 741 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 742 flushPipe = true, 743 replayInst = true, 744 hasLoadError = true 745 ) 746 747 val staCfg = FuConfig( 748 "sta", 749 null, 750 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 751 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 752 latency = UncertainLatency(), 753 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 754 ) 755 756 val stdCfg = FuConfig( 757 "std", 758 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 759 writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 760 ) 761 762 val mouCfg = FuConfig( 763 "mou", 764 null, 765 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 766 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 767 latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 768 ) 769 770 val mouDataCfg = FuConfig( 771 "mou", 772 mouDataGen, 773 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 774 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 775 latency = UncertainLatency() 776 ) 777 778 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 779 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 780 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 781 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 782 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg), Int.MaxValue, 0) 783 val FmiscExeUnitCfg = ExuConfig( 784 "FmiscExeUnit", 785 "Fp", 786 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 787 Int.MaxValue, 1 788 ) 789 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 790 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 791 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 792 793 // def jumpRSWrapperGen(p: Parameters) = new JumpRSWrapper()(p) 794 // def mulRSWrapperGen(p: Parameters) = new MulRSWrapper()(p) 795 // def loadRSWrapperGen(p: Parameters) = new LoadRSWrapper()(p) 796 // def stdRSWrapperGen(p: Parameters) = new StdRSWrapper()(p) 797 // def staRSWrapperGen(p: Parameters) = new StaRSWrapper()(p) 798 // def fmaRSWrapperGen(p: Parameters) = new FMARSWrapper()(p) 799 // def fmiscRSWrapperGen(p: Parameters) = new FMiscRSWrapper()(p) 800 801 val aluRSMod = new RSMod( 802 rsWrapperGen = (modGen: RSMod, p: Parameters) => new ALURSWrapper(modGen)(p), 803 rsGen = (a: RSParams, b: Parameters) => new ALURS(a)(b), 804 immExtractorGen = (src: Int, width: Int, p: Parameters) => new AluImmExtractor()(p) 805 ) 806 val fmaRSMod = new RSMod( 807 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMARSWrapper(modGen)(p), 808 rsGen = (a: RSParams, b: Parameters) => new FMARS(a)(b), 809 ) 810 val fmiscRSMod = new RSMod( 811 rsWrapperGen = (modGen: RSMod, p: Parameters) => new FMiscRSWrapper(modGen)(p), 812 rsGen = (a: RSParams, b: Parameters) => new FMiscRS(a)(b), 813 ) 814 val jumpRSMod = new RSMod( 815 rsWrapperGen = (modGen: RSMod, p: Parameters) => new JumpRSWrapper(modGen)(p), 816 rsGen = (a: RSParams, b: Parameters) => new JumpRS(a)(b), 817 immExtractorGen = (src: Int, width: Int, p: Parameters) => new JumpImmExtractor()(p) 818 ) 819 val loadRSMod = new RSMod( 820 rsWrapperGen = (modGen: RSMod, p: Parameters) => new LoadRSWrapper(modGen)(p), 821 rsGen = (a: RSParams, b: Parameters) => new LoadRS(a)(b), 822 immExtractorGen = (src: Int, width: Int, p: Parameters) => new LoadImmExtractor()(p) 823 ) 824 val mulRSMod = new RSMod( 825 rsWrapperGen = (modGen: RSMod, p: Parameters) => new MulRSWrapper(modGen)(p), 826 rsGen = (a: RSParams, b: Parameters) => new MulRS(a)(b), 827 immExtractorGen = (src: Int, width: Int, p: Parameters) => new MduImmExtractor()(p) 828 ) 829 val staRSMod = new RSMod( 830 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StaRSWrapper(modGen)(p), 831 rsGen = (a: RSParams, b: Parameters) => new StaRS(a)(b), 832 ) 833 val stdRSMod = new RSMod( 834 rsWrapperGen = (modGen: RSMod, p: Parameters) => new StdRSWrapper(modGen)(p), 835 rsGen = (a: RSParams, b: Parameters) => new StdRS(a)(b), 836 ) 837} 838