IFU <info>: add debug info for predecode redirect

Debug mode: various bug fixes (#1412)

* Reduce trigger hit wires that goes into exceptiongen
* Fix frontend triggers rewriting hit wire
* Retrieved some accidentally dropped changes in branch dm-d

Debug mode: various bug fixes (#1412)

* Reduce trigger hit wires that goes into exceptiongen
* Fix frontend triggers rewriting hit wire
* Retrieved some accidentally dropped changes in branch dm-debug (mainly fixes to debug mode)
* Fix dmode in tdata1
* Fix ebreaks not causing exception in debug mode
* Fix dcsr field bugs
* Fix faulty distributed tEnable
* Fix store triggers not using vaddr
* Fix store trigger rewriting hit vector
* Initialize distributed tdata registers in MemBlock and Frontend to zero
* Fix load trigger select bit in mcontrol
* Fix singlestep bit valid in debug mode
* Mask all interrupts in debug mode

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add reset value of distribute trigger csrs at memory and frontend block.

Merge branch 'master' into trigger

Merge branch 'master' into trigger

Trigger: hardwire timing to 1

We have singlestep already so triggers do not need to hit after inst commits

Fix false hit bug after IFU timing optimization (#1367)

* fix invalidTakenFault use wrong seqTarget

* IFU: fix oversize bug

* ctrl: mark all flushes as level.flush for frontend

This commit

Fix false hit bug after IFU timing optimization (#1367)

* fix invalidTakenFault use wrong seqTarget

* IFU: fix oversize bug

* ctrl: mark all flushes as level.flush for frontend

This commit changes how flushes behave for frontend.

When ROB commits an instruction with a flush, we notify the frontend
of the flush without the commit.

Flushes to frontend may be delayed by some cycles and commit before
flush causes errors. Thus, we make all flush reasons to behave the
same as exceptions for frontend, that is, RedirectLevel.flush.

* IFU: exclude lastTaken situation when judging beyond fetch

Co-authored-by: Yinan Xu <[email protected]>

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Optimize IFU and PreDecode timing (#1347)

* ICache: add ReplacePipe for Probe & Release

* remove ProbeUnit

* Probe & Release enter ReplacePipe

* fix bugs when running Linux on MinimalConfi

Optimize IFU and PreDecode timing (#1347)

* ICache: add ReplacePipe for Probe & Release

* remove ProbeUnit

* Probe & Release enter ReplacePipe

* fix bugs when running Linux on MinimalConfig

* TODO: set conflict for ReplacePipe

* ICache: fix ReplacePipe invalid write bug

* chores: code clean up

* IFU: optimize timing

* PreDecode: separate into 2 module for timing optimization

* IBuffer: add enqEnable to replace valid for timing

* IFU/ITLB: optimize timing

* IFU: calculate cut_ptr in f1

* TLB: send req in f1 and wait resp in f2

* ICacheMainPipe: add tlb miss logic in s0

* Optimize IFU timing

* IFU: fix lastHalfRVI bug

* IFU: fix performance bug

* IFU: optimize MMIO commit timing

* IFU: optmize trigger timing and add frontendTrigger

* fix compile error

* IFU: fix mmio stuck bug

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Refactor trigger

ICache: Add tilelink consistency modification (#1228)

* ICache: metaArray & dataArray use bank interleave

* ICache: add bank interleave

* ICache: add parity check for meta and data arrays

*

ICache: Add tilelink consistency modification (#1228)

* ICache: metaArray & dataArray use bank interleave

* ICache: add bank interleave

* ICache: add parity check for meta and data arrays

* IFU: fix bug in secondary miss

* secondary miss doesn't send miss request to miss queue

* ICache: write back cancled miss request

* ICacheMissEntry: add second miss merge

* deal with situations that this entry has been flushed, and the next miss req just
requests the same cachline.

* ICache: add acquireBlock and GrantAck support

* refact: move icache modules to frontend modules

* ICache: add release surport and meta coh

* ICache: change Get to AcquireBlock for A channel

* rebuild: change ICachePara package for other file

* ICache: add tilelogger for L1I

* ICahce: add ProbeQueue and Probe Process Unit

* ICache: add support for ProbeData

* ICahceParameter: change tag code to ECC

* ICahce: fix bugs in connect and ProbeUnit

* metaArray/dataArray responses are not connected

* ProbeUnit use reg so data and req are not synchronized

* RealeaseUnit: write back mata when voluntary

* Add ICache CacheInstruction

* move ICache to xiangshan.frontend.icache._

* ICache: add CacheOpDecoder

* change ICacheMissQueue to ICacheMissUnit

* ProbeUnit: fix meta data not latch bug

* IFU: delete releaseSlot and add missSlot

* IFU: fix bugs in missSlot state machine

* IFU: fix some bugs in miss Slot

* IFU: move out fetch to ICache Array logic

* ReleaseUnit: delete release write logic

* MissUnit: send Release to ReleaseUnit after GAck

* ICacheMainPipe: add mainpipe and stop logic

* when f3_ready is low, stop the pipeline

* IFU: move tlb and array access to mainpipe

* Modify Frontend and ICache top for mainpipe

* ReleaseUnit: add probe merge status register

* ICache: add victim info and release in mainpipe

* ICahche: add set-conflict logic

* Release: do not invalid meta after sending release

* bump Huancun: fix probe problem

* bump huancun for MinimalConfig combinational loop

* ICache: add LICENSE for new files

* Chore: remove debug code and add perf counter

* Bump huancun for bug fix

* Bump HuanCun for alias bug

* ICache: add dirty state for CliendMeta

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Trigger Implementation for Debug Mode (#1170)

* Untested Trigger Implementation

Co-authored-by: William Wang <[email protected]>
Co-authored-by: Lingrui98 <[email protected]>
Co-autho

Trigger Implementation for Debug Mode (#1170)

* Untested Trigger Implementation

Co-authored-by: William Wang <[email protected]>
Co-authored-by: Lingrui98 <[email protected]>
Co-authored-by: rvcoresjw <[email protected]>

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PreDecode: rule out taken when beyond fetch (#1222)

* assuming that beyond fetch => oversize

PreDecode: add beyond fetch condition solution (#1207)

* PreDecode: fix beyond fetch bug

* Fallthrough address === startAddress + 34 Bytes and the 17th 2 Bytes is an RVC instruction, which will b

PreDecode: add beyond fetch condition solution (#1207)

* PreDecode: fix beyond fetch bug

* Fallthrough address === startAddress + 34 Bytes and the 17th 2 Bytes is an RVC instruction, which will be missing when sending to ibuffer

* PreDecode: fix target when beyond fetch happen

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Merge pull request #1198 from OpenXiangShan/fix-crossline-falsehit

PreDecode: fix cross-line false hit condition

Merge pull request #1191 from OpenXiangShan/JWrong-bug-fix

Predecode: Fixed the bug that Predecode did not compare jal offset wh…

PreDecode: fix cross-line false hit condition

Predecode: Fixed the bug that Predecode did not compare jal offset when predicting taken

PreDecode: fix crossPageFault not raise page fault bug (#1190)

Predecoder: fix pagefult condition (#1174)

* pc which is the start of a pagefault cacheline was not treated as page fault

misc: code clean up (#1073)

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

frontend: code clean ups

frontend: remove deprecated code

[WIP] finish ftq logic and fix syntax errors

* Now can pass compiling.

[WIP] comment out-of-date code in frontend

[WIP] move NewFtq to xiangshan.frontend and rename class to Ftq

Ibuffer: update s

[WIP] finish ftq logic and fix syntax errors

* Now can pass compiling.

[WIP] comment out-of-date code in frontend

[WIP] move NewFtq to xiangshan.frontend and rename class to Ftq

Ibuffer: update sigal names for new IFU

[WIP] remove redundant NewFrontend

[WIP] set entry_fetch_status to f_sent once send req to buf

Fix syntax error in IFU

Fix syntax error in IFU/ICache/Ibuffer

[WIP] indent fix in ftq

BPU: Move GlobalHistory define from IFU.scala to BPU.scala

[WIP] fix some compilation errors

BPU: Remove HasIFUConst
and move some bundles from BPU.scala to frontendBundle.scala

[WIP] fix some compilation errors

[WIP] rename ftq-bpu ios

[WIP] recover some const definitions

[WIP] fix some compilation errors

[WIP]connect some IOs in frontend

BPU: fix syntax error

[WIP] fix compilation errors in predecode

BPU: fix RAS syntax error

[WIP] add some simulation perf counters back

BPU: Remove numBr redefine in ubtb and bim

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Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr.
(2) DPI-C is cross-platform (Verilator, VCS, ...)
(3) difftest APIs are splited from emu.cpp to possibly support more backend platforms
(NEMU, Spike, ...)

The performance at this commit is quite slower than the original emu.
Performance issues will be fixed later.

* [WIP] SimTop: try to use 'XSTop' as soc

* CircularQueuePtr: ues F-bounded polymorphis instead implict helper

* Refactor parameters & Clean up code

* difftest: support basic difftest

* Support diffetst in new sim top

* Difftest; convert recode fmt to ieee754 when comparing fp regs

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Debug: add int/exc inst wb to debug queue

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Difftest: fix naive commit num limit

Co-authored-by: Yinan Xu <[email protected]>
Co-authored-by: William Wang <[email protected]>

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