1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.rocket.{RVCDecoder, ExpandedInstruction} 21import chisel3.{util, _} 22import chisel3.util._ 23import utils._ 24import xiangshan._ 25import xiangshan.frontend.icache._ 26import xiangshan.backend.decode.isa.predecode.PreDecodeInst 27 28trait HasPdConst extends HasXSParameter with HasICacheParameters with HasIFUConst{ 29 def isRVC(inst: UInt) = (inst(1,0) =/= 3.U) 30 def isLink(reg:UInt) = reg === 1.U || reg === 5.U 31 def brInfo(instr: UInt) = { 32 val brType::Nil = ListLookup(instr, List(BrType.notCFI), PreDecodeInst.brTable) 33 val rd = Mux(isRVC(instr), instr(12), instr(11,7)) 34 val rs = Mux(isRVC(instr), Mux(brType === BrType.jal, 0.U, instr(11, 7)), instr(19, 15)) 35 val isCall = (brType === BrType.jal && !isRVC(instr) || brType === BrType.jalr) && isLink(rd) // Only for RV64 36 val isRet = brType === BrType.jalr && isLink(rs) && !isCall 37 List(brType, isCall, isRet) 38 } 39 def jal_offset(inst: UInt, rvc: Bool): UInt = { 40 val rvc_offset = Cat(inst(12), inst(8), inst(10, 9), inst(6), inst(7), inst(2), inst(11), inst(5, 3), 0.U(1.W)) 41 val rvi_offset = Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)) 42 val max_width = rvi_offset.getWidth 43 SignExt(Mux(rvc, SignExt(rvc_offset, max_width), SignExt(rvi_offset, max_width)), XLEN) 44 } 45 def br_offset(inst: UInt, rvc: Bool): UInt = { 46 val rvc_offset = Cat(inst(12), inst(6, 5), inst(2), inst(11, 10), inst(4, 3), 0.U(1.W)) 47 val rvi_offset = Cat(inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)) 48 val max_width = rvi_offset.getWidth 49 SignExt(Mux(rvc, SignExt(rvc_offset, max_width), SignExt(rvi_offset, max_width)), XLEN) 50 } 51 52 def NOP = "h4501".U(16.W) 53} 54 55object BrType { 56 def notCFI = "b00".U 57 def branch = "b01".U 58 def jal = "b10".U 59 def jalr = "b11".U 60 def apply() = UInt(2.W) 61} 62 63object ExcType { //TODO:add exctype 64 def notExc = "b000".U 65 def apply() = UInt(3.W) 66} 67 68class PreDecodeInfo extends Bundle { // 8 bit 69 val valid = Bool() 70 val isRVC = Bool() 71 val brType = UInt(2.W) 72 val isCall = Bool() 73 val isRet = Bool() 74 //val excType = UInt(3.W) 75 def isBr = brType === BrType.branch 76 def isJal = brType === BrType.jal 77 def isJalr = brType === BrType.jalr 78 def notCFI = brType === BrType.notCFI 79} 80 81class PreDecodeResp(implicit p: Parameters) extends XSBundle with HasPdConst { 82 val pd = Vec(PredictWidth, new PreDecodeInfo) 83 val hasHalfValid = Vec(PredictWidth, Bool()) 84 val expInstr = Vec(PredictWidth, UInt(32.W)) 85 val jumpOffset = Vec(PredictWidth, UInt(XLEN.W)) 86// val hasLastHalf = Bool() 87 val triggered = Vec(PredictWidth, new TriggerCf) 88} 89 90class PreDecode(implicit p: Parameters) extends XSModule with HasPdConst{ 91 val io = IO(new Bundle() { 92 val in = Input(new IfuToPreDecode) 93 val out = Output(new PreDecodeResp) 94 }) 95 96 val data = io.in.data 97// val lastHalfMatch = io.in.lastHalfMatch 98 val validStart, validEnd = Wire(Vec(PredictWidth, Bool())) 99 val h_validStart, h_validEnd = Wire(Vec(PredictWidth, Bool())) 100 101 val rawInsts = if (HasCExtension) VecInit((0 until PredictWidth).map(i => Cat(data(i+1), data(i)))) 102 else VecInit((0 until PredictWidth).map(i => data(i))) 103 104 // Frontend Triggers 105 val tdata = Reg(Vec(4, new MatchTriggerIO)) 106 when(io.in.frontendTrigger.t.valid) { 107 tdata(io.in.frontendTrigger.t.bits.addr) := io.in.frontendTrigger.t.bits.tdata 108 } 109 io.out.triggered.map{i => i := 0.U.asTypeOf(new TriggerCf)} 110 val triggerEnable = RegInit(VecInit(Seq.fill(4)(false.B))) // From CSR, controlled by priv mode, etc. 111 triggerEnable := io.in.csrTriggerEnable 112 val triggerMapping = Map(0 -> 0, 1 -> 1, 2 -> 6, 3 -> 8) 113 val chainMapping = Map(0 -> 0, 2 -> 3, 3 -> 4) 114 115 for (i <- 0 until PredictWidth) { 116 val inst =WireInit(rawInsts(i)) 117 val expander = Module(new RVCExpander) 118 val currentIsRVC = isRVC(inst) 119 val currentPC = io.in.pc(i) 120 expander.io.in := inst 121 122 val brType::isCall::isRet::Nil = brInfo(inst) 123 val jalOffset = jal_offset(inst, currentIsRVC) 124 val brOffset = br_offset(inst, currentIsRVC) 125 126 //val lastIsValidEnd = if (i == 0) { !lastHalfMatch } else { validEnd(i-1) || !HasCExtension.B } 127 val lastIsValidEnd = if (i == 0) { true.B } else { validEnd(i-1) || !HasCExtension.B } 128 validStart(i) := (lastIsValidEnd || !HasCExtension.B) 129 validEnd(i) := validStart(i) && currentIsRVC || !validStart(i) || !HasCExtension.B 130 131 //prepared for last half match 132 //TODO if HasCExtension 133 val h_lastIsValidEnd = if (i == 0) { false.B } else { h_validEnd(i-1) || !HasCExtension.B } 134 h_validStart(i) := (h_lastIsValidEnd || !HasCExtension.B) 135 h_validEnd(i) := h_validStart(i) && currentIsRVC || !h_validStart(i) || !HasCExtension.B 136 137 io.out.hasHalfValid(i) := h_validStart(i) 138 139 io.out.triggered(i).triggerTiming := DontCare//VecInit(Seq.fill(10)(false.B)) 140 io.out.triggered(i).triggerHitVec := DontCare//VecInit(Seq.fill(10)(false.B)) 141 io.out.triggered(i).triggerChainVec := DontCare//VecInit(Seq.fill(5)(false.B)) 142 for (j <- 0 until 4) { 143 val hit = Mux(tdata(j).select, TriggerCmp(Mux(currentIsRVC, inst(15, 0), inst), tdata(j).tdata2, tdata(j).matchType, triggerEnable(j)), 144 TriggerCmp(currentPC, tdata(j).tdata2, tdata(j).matchType, triggerEnable(j))) 145 io.out.triggered(i).triggerHitVec(triggerMapping(j)) := hit 146 io.out.triggered(i).triggerTiming(triggerMapping(j)) := hit && tdata(j).timing 147 if(chainMapping.contains(j)) io.out.triggered(i).triggerChainVec(chainMapping(j)) := hit && tdata(j).chain 148 } 149 150 io.out.pd(i).valid := validStart(i) 151 io.out.pd(i).isRVC := currentIsRVC 152 io.out.pd(i).brType := brType 153 io.out.pd(i).isCall := isCall 154 io.out.pd(i).isRet := isRet 155 156 io.out.expInstr(i) := expander.io.out.bits 157 io.out.jumpOffset(i) := Mux(io.out.pd(i).isBr, brOffset, jalOffset) 158 } 159 160// io.out.hasLastHalf := !io.out.pd(PredictWidth - 1).isRVC && io.out.pd(PredictWidth - 1).valid 161 162 for (i <- 0 until PredictWidth) { 163 XSDebug(true.B, 164 p"instr ${Hexadecimal(io.out.expInstr(i))}, " + 165 p"validStart ${Binary(validStart(i))}, " + 166 p"validEnd ${Binary(validEnd(i))}, " + 167 p"isRVC ${Binary(io.out.pd(i).isRVC)}, " + 168 p"brType ${Binary(io.out.pd(i).brType)}, " + 169 p"isRet ${Binary(io.out.pd(i).isRet)}, " + 170 p"isCall ${Binary(io.out.pd(i).isCall)}\n" 171 ) 172 } 173} 174 175class RVCExpander(implicit p: Parameters) extends XSModule { 176 val io = IO(new Bundle { 177 val in = Input(UInt(32.W)) 178 val out = Output(new ExpandedInstruction) 179 }) 180 181 if (HasCExtension) { 182 io.out := new RVCDecoder(io.in, XLEN).decode 183 } else { 184 io.out := new RVCDecoder(io.in, XLEN).passthrough 185 } 186} 187 188/* --------------------------------------------------------------------- 189 * Predict result check 190 * 191 * --------------------------------------------------------------------- 192 */ 193 194object FaultType { 195 def noFault = "b000".U 196 def jalFault = "b001".U //not CFI taken or invalid instruction taken 197 def retFault = "b010".U //not CFI taken or invalid instruction taken 198 def targetFault = "b011".U 199 def faulsePred = "b100".U //not CFI taken or invalid instruction taken 200 def apply() = UInt(3.W) 201} 202 203class CheckInfo extends Bundle { // 8 bit 204 val value = UInt(3.W) 205 def isjalFault = value === FaultType.jalFault 206 def isRetFault = value === FaultType.retFault 207 def istargetFault = value === FaultType.targetFault 208 def isfaulsePred = value === FaultType.faulsePred 209} 210 211class PredCheckerResp(implicit p: Parameters) extends XSBundle with HasPdConst { 212 //to Ibuffer write port (timing critical) 213 val fixedRange = Vec(PredictWidth, Bool()) 214 val fixedTaken = Vec(PredictWidth, Bool()) 215 //to Ftq write back port (not timing critical) 216 val fixedTarget = Vec(PredictWidth, UInt(VAddrBits.W)) 217 val fixedMissPred = Vec(PredictWidth, Bool()) 218 val faultType = Vec(PredictWidth, new CheckInfo) 219} 220 221 222class PredChecker(implicit p: Parameters) extends XSModule with HasPdConst { 223 val io = IO( new Bundle{ 224 val in = Input(new IfuToPredChecker) 225 val out = Output(new PredCheckerResp) 226 }) 227 228 val (takenIdx, predTaken) = (io.in.ftqOffset.bits, io.in.ftqOffset.valid) 229 val predTarget = (io.in.target) 230 val (instrRange, instrValid) = (io.in.instrRange, io.in.instrValid) 231 val (pds, pc, jumpOffset) = (io.in.pds, io.in.pc, io.in.jumpOffset) 232 233 val jalFaultVec, retFaultVec, targetFault, notCFITaken, invalidTaken = Wire(Vec(PredictWidth, Bool())) 234 235 /** remask fault may appear together with other faults, but other faults are exclusive 236 * so other f ault mast use fixed mask to keep only one fault would be found and redirect to Ftq 237 * we first detecct remask fault and then use fixedRange to do second check 238 **/ 239 240 /** first check: remask Fault */ 241 jalFaultVec := VecInit(pds.zipWithIndex.map{case(pd, i) => pd.isJal && instrRange(i) && instrValid(i) && (takenIdx > i.U && predTaken || !predTaken) }) 242 retFaultVec := VecInit(pds.zipWithIndex.map{case(pd, i) => pd.isRet && instrRange(i) && instrValid(i) && (takenIdx > i.U && predTaken || !predTaken) }) 243 val remaskFault = VecInit((0 until PredictWidth).map(i => jalFaultVec(i) || retFaultVec(i))) 244 val remaskIdx = ParallelPriorityEncoder(remaskFault.asUInt) 245 val needRemask = ParallelOR(remaskFault) 246 val fixedRange = instrRange.asUInt & (Fill(PredictWidth, !needRemask) | Fill(PredictWidth, 1.U(1.W)) >> ~remaskIdx) 247 248 io.out.fixedRange := fixedRange.asTypeOf((Vec(PredictWidth, Bool()))) 249 250 io.out.fixedTaken := VecInit(pds.zipWithIndex.map{case(pd, i) => instrValid (i) && fixedRange(i) && (pd.isRet || pd.isJal || takenIdx === i.U && predTaken && !pd.notCFI) }) 251 252 /** second check: faulse prediction fault and target fault */ 253 notCFITaken := VecInit(pds.zipWithIndex.map{case(pd, i) => fixedRange(i) && instrValid(i) && i.U === takenIdx && pd.notCFI && predTaken }) 254 invalidTaken := VecInit(pds.zipWithIndex.map{case(pd, i) => fixedRange(i) && !instrValid(i) && i.U === takenIdx && predTaken }) 255 256 /** target calculation */ 257 val jumpTargets = VecInit(pds.zipWithIndex.map{case(pd,i) => pc(i) + jumpOffset(i)}) 258 targetFault := VecInit(pds.zipWithIndex.map{case(pd,i) => fixedRange(i) && instrValid(i) && (pd.isJal || pd.isBr) && takenIdx === i.U && predTaken && (predTarget =/= jumpTargets(i))}) 259 260 val seqTargets = VecInit((0 until PredictWidth).map(i => pc(i) + Mux(pds(i).isRVC || !pds(i).valid, 2.U, 4.U ) )) 261 262 io.out.faultType.zipWithIndex.map{case(faultType, i) => faultType.value := Mux(jalFaultVec(i) , FaultType.jalFault , 263 Mux(retFaultVec(i), FaultType.retFault , 264 Mux(targetFault(i), FaultType.targetFault , 265 Mux(notCFITaken(i) || invalidTaken(i) ,FaultType.faulsePred, FaultType.noFault))))} 266 267 io.out.fixedMissPred.zipWithIndex.map{case(missPred, i ) => missPred := jalFaultVec(i) || retFaultVec(i) || notCFITaken(i) || invalidTaken(i) || targetFault(i)} 268 io.out.fixedTarget.zipWithIndex.map{case(target, i) => target := Mux(jalFaultVec(i) || targetFault(i), jumpTargets(i), seqTargets(i) )} 269 270} 271 272class FrontendTrigger(implicit p: Parameters) extends XSModule { 273 val io = IO(new Bundle(){ 274 val frontendTrigger = Input(new FrontendTdataDistributeIO) 275 val csrTriggerEnable = Input(Vec(4, Bool())) 276 val triggered = Output(Vec(PredictWidth, new TriggerCf)) 277 278 val pds = Input(Vec(PredictWidth, new PreDecodeInfo)) 279 val pc = Input(Vec(PredictWidth, UInt(VAddrBits.W))) 280 val data = if(HasCExtension) Input(Vec(PredictWidth + 1, UInt(16.W))) 281 else Input(Vec(PredictWidth, UInt(32.W))) 282 }) 283 284 val data = io.data 285 286 val rawInsts = if (HasCExtension) VecInit((0 until PredictWidth).map(i => Cat(data(i+1), data(i)))) 287 else VecInit((0 until PredictWidth).map(i => data(i))) 288 289 val tdata = Reg(Vec(4, new MatchTriggerIO)) 290 when(io.frontendTrigger.t.valid) { 291 tdata(io.frontendTrigger.t.bits.addr) := io.frontendTrigger.t.bits.tdata 292 } 293 io.triggered.map{i => i := 0.U.asTypeOf(new TriggerCf)} 294 val triggerEnable = RegInit(VecInit(Seq.fill(4)(false.B))) // From CSR, controlled by priv mode, etc. 295 triggerEnable := io.csrTriggerEnable 296 val triggerMapping = Map(0 -> 0, 1 -> 1, 2 -> 6, 3 -> 8) 297 val chainMapping = Map(0 -> 0, 2 -> 3, 3 -> 4) 298 299 for (i <- 0 until PredictWidth) { 300 val currentPC = io.pc(i) 301 val currentIsRVC = io.pds(i).isRVC 302 val inst = WireInit(rawInsts(i)) 303 304 io.triggered(i).triggerTiming := VecInit(Seq.fill(10)(false.B)) 305 io.triggered(i).triggerHitVec := VecInit(Seq.fill(10)(false.B)) 306 io.triggered(i).triggerChainVec := VecInit(Seq.fill(5)(false.B)) 307 for (j <- 0 until 4) { 308 val hit = Mux(tdata(j).select, TriggerCmp(Mux(currentIsRVC, inst(15, 0), inst), tdata(j).tdata2, tdata(j).matchType, triggerEnable(j)), 309 TriggerCmp(currentPC, tdata(j).tdata2, tdata(j).matchType, triggerEnable(j))) 310 io.triggered(i).triggerHitVec(triggerMapping(j)) := hit 311 io.triggered(i).triggerTiming(triggerMapping(j)) := hit && tdata(j).timing 312 if(chainMapping.contains(j)) io.triggered(i).triggerChainVec(chainMapping(j)) := hit && tdata(j).chain 313 } 314 } 315} 316