1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.rocket.{RVCDecoder, ExpandedInstruction} 21import chisel3.{util, _} 22import chisel3.util._ 23import utils._ 24import xiangshan._ 25import xiangshan.frontend.icache._ 26import xiangshan.backend.decode.isa.predecode.PreDecodeInst 27 28trait HasPdConst extends HasXSParameter with HasICacheParameters with HasIFUConst{ 29 def isRVC(inst: UInt) = (inst(1,0) =/= 3.U) 30 def isLink(reg:UInt) = reg === 1.U || reg === 5.U 31 def brInfo(instr: UInt) = { 32 val brType::Nil = ListLookup(instr, List(BrType.notCFI), PreDecodeInst.brTable) 33 val rd = Mux(isRVC(instr), instr(12), instr(11,7)) 34 val rs = Mux(isRVC(instr), Mux(brType === BrType.jal, 0.U, instr(11, 7)), instr(19, 15)) 35 val isCall = (brType === BrType.jal && !isRVC(instr) || brType === BrType.jalr) && isLink(rd) // Only for RV64 36 val isRet = brType === BrType.jalr && isLink(rs) && !isCall 37 List(brType, isCall, isRet) 38 } 39 def jal_offset(inst: UInt, rvc: Bool): UInt = { 40 val rvc_offset = Cat(inst(12), inst(8), inst(10, 9), inst(6), inst(7), inst(2), inst(11), inst(5, 3), 0.U(1.W)) 41 val rvi_offset = Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)) 42 val max_width = rvi_offset.getWidth 43 SignExt(Mux(rvc, SignExt(rvc_offset, max_width), SignExt(rvi_offset, max_width)), XLEN) 44 } 45 def br_offset(inst: UInt, rvc: Bool): UInt = { 46 val rvc_offset = Cat(inst(12), inst(6, 5), inst(2), inst(11, 10), inst(4, 3), 0.U(1.W)) 47 val rvi_offset = Cat(inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)) 48 val max_width = rvi_offset.getWidth 49 SignExt(Mux(rvc, SignExt(rvc_offset, max_width), SignExt(rvi_offset, max_width)), XLEN) 50 } 51 def getBasicBlockIdx( pc: UInt, start: UInt ): UInt = { 52 val byteOffset = pc - start 53 (byteOffset - instBytes.U)(log2Ceil(PredictWidth),instOffsetBits) 54 } 55 56 def NOP = "h4501".U(16.W) 57} 58 59object BrType { 60 def notCFI = "b00".U 61 def branch = "b01".U 62 def jal = "b10".U 63 def jalr = "b11".U 64 def apply() = UInt(2.W) 65} 66 67object ExcType { //TODO:add exctype 68 def notExc = "b000".U 69 def apply() = UInt(3.W) 70} 71 72class PreDecodeInfo extends Bundle { // 8 bit 73 val valid = Bool() 74 val isRVC = Bool() 75 val brType = UInt(2.W) 76 val isCall = Bool() 77 val isRet = Bool() 78 //val excType = UInt(3.W) 79 def isBr = brType === BrType.branch 80 def isJal = brType === BrType.jal 81 def isJalr = brType === BrType.jalr 82 def notCFI = brType === BrType.notCFI 83} 84 85class PreDecodeResp(implicit p: Parameters) extends XSBundle with HasPdConst { 86 val pc = Vec(PredictWidth, UInt(VAddrBits.W)) 87 val instrs = Vec(PredictWidth, UInt(32.W)) 88 val pd = Vec(PredictWidth, (new PreDecodeInfo)) 89 val takens = Vec(PredictWidth, Bool()) 90 val misOffset = ValidUndirectioned(UInt(log2Ceil(PredictWidth).W)) 91 val cfiOffset = ValidUndirectioned(UInt(log2Ceil(PredictWidth).W)) 92 val target = UInt(VAddrBits.W) 93 val jalTarget = UInt(VAddrBits.W) 94 val hasLastHalf = Bool() 95 val realEndPC = UInt(VAddrBits.W) 96 val instrRange = Vec(PredictWidth, Bool()) 97 val pageFault = Vec(PredictWidth, Bool()) 98 val accessFault = Vec(PredictWidth, Bool()) 99 val crossPageIPF = Vec(PredictWidth, Bool()) 100 val triggered = Vec(PredictWidth, new TriggerCf) 101} 102 103class PreDecode(implicit p: Parameters) extends XSModule with HasPdConst{ 104 val io = IO(new Bundle() { 105 val in = Input(new IfuToPreDecode) 106 val out = Output(new PreDecodeResp) 107 }) 108 109 val instValid = io.in.instValid 110 val data = io.in.data 111 val pcStart = io.in.startAddr 112 val pcEnd = io.in.fallThruAddr 113 val pcEndError = io.in.fallThruError 114 val isDoubleLine = io.in.isDoubleLine 115 val bbOffset = io.in.ftqOffset.bits 116 val bbTaken = io.in.ftqOffset.valid 117 val bbTarget = io.in.target 118 val oversize = io.in.oversize 119 val pageFault = io.in.pageFault 120 val accessFault = io.in.accessFault 121 122 val validStart = Wire(Vec(PredictWidth, Bool())) 123 dontTouch(validStart) 124 val validEnd = Wire(Vec(PredictWidth, Bool())) 125 val targets = Wire(Vec(PredictWidth, UInt(VAddrBits.W))) 126 val misPred = Wire(Vec(PredictWidth, Bool())) 127 val takens = Wire(Vec(PredictWidth, Bool())) 128 val falseHit = Wire(Vec(PredictWidth, Bool())) 129 val instRange = Wire(Vec(PredictWidth, Bool())) 130 //"real" means signals that are genrated by repaired end pc of this basic block using predecode information 131 val realEndPC = Wire(UInt(VAddrBits.W)) 132 val realHasLastHalf = Wire(Vec(PredictWidth, Bool())) 133 val realMissPred = Wire(Vec(PredictWidth, Bool())) 134 val realTakens = Wire(Vec(PredictWidth, Bool())) 135 136 val rawInsts = if (HasCExtension) VecInit((0 until PredictWidth).map(i => Cat(data(i+1), data(i)))) 137 else VecInit((0 until PredictWidth).map(i => data(i))) 138 139 val nextLinePC = addrAlign(pcStart, 64, VAddrBits) + 64.U 140 141 // Frontend Triggers 142 val tdata = Reg(Vec(4, new MatchTriggerIO)) 143 when(io.in.frontendTrigger.t.valid) { 144 tdata(io.in.frontendTrigger.t.bits.addr) := io.in.frontendTrigger.t.bits.tdata 145 } 146 io.out.triggered.map{i => i := 0.U.asTypeOf(new TriggerCf)} 147 val triggerEnable = RegInit(VecInit(Seq.fill(4)(false.B))) // From CSR, controlled by priv mode, etc. 148 triggerEnable := io.in.csrTriggerEnable 149// val triggerMapping = Map(0 -> 0, 1 -> 1, 2 -> 6, 3 -> 8) 150 XSDebug(triggerEnable.asUInt.orR, "Debug Mode: At least one frontend trigger is enabled\n") 151 for (i <- 0 until 4) 152 PrintTriggerInfo(triggerEnable(i), tdata(i)) 153 154 for (i <- 0 until PredictWidth) { 155 //TODO: Terrible timing for pc comparing 156 val isNextLine = (io.out.pc(i) > nextLinePC) 157 val nullInstruction = isNextLine && !isDoubleLine 158 159 val hasPageFault = ((io.out.pc(i) < nextLinePC && pageFault(0)) || ((io.out.pc(i) > nextLinePC || io.out.pc(i) === nextLinePC) && pageFault(1))) 160 val hasAccessFault = ((io.out.pc(i) < nextLinePC && accessFault(0)) || ((io.out.pc(i) > nextLinePC || io.out.pc(i) === nextLinePC) && accessFault(1))) 161 val exception = hasPageFault || hasAccessFault 162 val inst = Mux(exception || nullInstruction , NOP, WireInit(rawInsts(i))) 163 val expander = Module(new RVCExpander) 164 165 val isFirstInBlock = i.U === 0.U 166 val isLastInBlock = (i == PredictWidth - 1).B 167 val currentPC = pcStart + (i << 1).U((log2Ceil(PredictWidth)+1).W) 168 val currentIsRVC = isRVC(inst) && HasCExtension.B 169 170 val lastIsValidEnd = if (i == 0) { !io.in.lastHalfMatch } else { validEnd(i-1) || isFirstInBlock || !HasCExtension.B } 171 172 validStart(i) := (lastIsValidEnd || !HasCExtension.B) 173 validEnd(i) := validStart(i) && currentIsRVC || !validStart(i) || !HasCExtension.B 174 175 val brType::isCall::isRet::Nil = brInfo(inst) 176 val jalOffset = jal_offset(inst, currentIsRVC) 177 val brOffset = br_offset(inst, currentIsRVC) 178 179 io.out.pd(i).valid := (lastIsValidEnd || !HasCExtension.B) 180 io.out.pd(i).isRVC := currentIsRVC 181 io.out.pd(i).brType := brType 182 io.out.pd(i).isCall := isCall 183 io.out.pd(i).isRet := isRet 184 io.out.pc(i) := currentPC 185 io.out.crossPageIPF(i) := (io.out.pc(i) === addrAlign(realEndPC, 64, VAddrBits) - 2.U)&& !pageFault(0) && pageFault(1) && !currentIsRVC 186// io.out.triggered(i) := TriggerCmp(Mux(currentIsRVC, inst(15,0), inst), tInstData, matchType, triggerEnable) && TriggerCmp(currentPC, tPcData, matchType, triggerEnable) 187// io.out.triggered(i).triggerTiming := VecInit(Seq.fill(10)(false.B)) 188// io.out.triggered(i).triggerHitVec := VecInit(Seq.fill(10)(false.B)) 189// io.out.triggered(i).triggerChainVec := VecInit(Seq.fill(5)(false.B)) 190 val triggerHitVec = Wire(Vec(4, Bool())) 191 for (j <- 0 until 4) { 192 val hit = Mux(tdata(j).select, TriggerCmp(Mux(currentIsRVC, inst(15, 0), inst), tdata(j).tdata2, tdata(j).matchType, triggerEnable(j)), 193 TriggerCmp(currentPC, tdata(j).tdata2, tdata(j).matchType, triggerEnable(j))) 194 triggerHitVec(j) := hit 195// io.out.triggered(i).frontendHit(triggerMapping(j)) := hit 196 io.out.triggered(i).frontendTiming(j) := tdata(j).timing 197 } 198 // fix chains this could be moved further into the pipeline 199 io.out.triggered(i).frontendHit := triggerHitVec 200 val enableChain = tdata(0).chain 201 when(enableChain){ 202 io.out.triggered(i).frontendHit(0) := triggerHitVec(0) && triggerHitVec(1) && (tdata(0).timing === tdata(1).timing) 203 io.out.triggered(i).frontendHit(1) := triggerHitVec(0) && triggerHitVec(1) && (tdata(0).timing === tdata(1).timing) 204 } 205 for(j <- 0 until 2) { 206 io.out.triggered(i).backendEn(j) := Mux(tdata(j+2).chain, triggerHitVec(j+2), true.B) 207 io.out.triggered(i).backendConsiderTiming(j) := tdata(j+2).chain 208 io.out.triggered(i).backendChainTiming(j) := tdata(j+2).timing 209 } 210 XSDebug(io.out.triggered(i).getHitFrontend, p"Debug Mode: Predecode Inst No. ${i} has trigger hit vec ${io.out.triggered(i).frontendHit}" + 211 p"with timing ${io.out.triggered(i).frontendTiming} and backend ${io.out.triggered(i).backendEn} + ${io.out.triggered(i).backendConsiderTiming}\n") 212 213 io.out.pageFault(i) := hasPageFault || io.out.crossPageIPF(i) 214 io.out.accessFault(i) := hasAccessFault 215 216 217 expander.io.in := inst 218 io.out.instrs(i) := expander.io.out.bits 219 220 takens(i) := (validStart(i) && (bbTaken && bbOffset === i.U && !io.out.pd(i).notCFI || io.out.pd(i).isJal || io.out.pd(i).isRet)) 221 222 val jumpTarget = io.out.pc(i) + Mux(io.out.pd(i).isBr, brOffset, jalOffset) 223 targets(i) := Mux(takens(i), jumpTarget, pcEnd) 224 //Banch and jal have wrong targets 225 val targetFault = (validStart(i) && i.U === bbOffset && bbTaken && (io.out.pd(i).isBr || io.out.pd(i).isJal) && bbTarget =/= targets(i)) 226 //An not-CFI instruction is predicted taken 227 val notCFIFault = (validStart(i) && i.U === bbOffset && io.out.pd(i).notCFI && bbTaken) 228 //A jal instruction is predicted not taken 229 val jalFault = (validStart(i) && !bbTaken && io.out.pd(i).isJal) || (validStart(i) && bbTaken && i.U < bbOffset && io.out.pd(i).isJal) 230 //A ret instruction is predicted not taken 231 val retFault = (validStart(i) && !bbTaken && io.out.pd(i).isRet) || (validStart(i) && bbTaken && i.U < bbOffset && io.out.pd(i).isRet) 232 //An invalid instruction is predicted taken 233 val invalidInsFault = (!validStart(i) && i.U === bbOffset && bbTaken) 234 235 misPred(i) := targetFault || notCFIFault || jalFault || retFault || invalidInsFault || pcEndError 236 falseHit(i) := invalidInsFault || notCFIFault 237 238 realMissPred(i) := misPred(i) && instRange(i) 239 realHasLastHalf(i) := instValid && currentPC === (realEndPC - 2.U) && validStart(i) && instRange(i) && !currentIsRVC 240 realTakens(i) := takens(i) && instRange(i) 241 } 242 243 //TODO: 244 val beyondFetch = ((pcStart + 34.U === realEndPC) && oversize && validEnd.last && isRVC(data.last)) && HasCExtension.B && !io.out.cfiOffset.valid 245 246 val jumpOH = VecInit(io.out.pd.zipWithIndex.map{ case(inst, i) => inst.isJal && validStart(i) }) //TODO: need jalr? 247 val jumpOffset = PriorityEncoder(jumpOH) 248 val rvcOH = VecInit(io.out.pd.map(inst => inst.isRVC)) 249 val jumpPC = io.out.pc(jumpOffset) 250 val jumpIsRVC = rvcOH(jumpOffset) 251 val jumpNextPC = jumpPC + Mux(jumpIsRVC, 2.U, 4.U) 252 val (hasFalseHit, hasJump) = (ParallelOR(falseHit), ParallelOR(jumpOH)) 253 val endRange = ((Fill(PredictWidth, 1.U(1.W)) >> (~getBasicBlockIdx(realEndPC, pcStart))) | (Fill(PredictWidth, oversize))) 254 val takeRange = Fill(PredictWidth, !ParallelOR(takens)) | Fill(PredictWidth, 1.U(1.W)) >> (~PriorityEncoder(takens)) 255 val fixCross = ((pcStart + (FetchWidth * 4).U) > nextLinePC || (pcStart + (FetchWidth * 4).U) === nextLinePC) && !isDoubleLine 256 val boundPC = Mux(fixCross, nextLinePC - 2.U ,pcStart + (FetchWidth * 4).U) 257 258 instRange := VecInit((0 until PredictWidth).map(i => endRange(i) && takeRange(i))) 259 realEndPC := Mux(hasFalseHit, Mux(hasJump && ((jumpNextPC < boundPC) || (jumpNextPC === boundPC) ), jumpNextPC, boundPC), pcEnd) 260 261 val validLastOffset = Mux(io.out.pd((PredictWidth - 1).U).valid, (PredictWidth - 1).U, (PredictWidth - 2).U) 262 263 io.out.misOffset.valid := ParallelOR(realMissPred) || beyondFetch 264 io.out.misOffset.bits := Mux(beyondFetch, PredictWidth.U, Mux(pcEndError,validLastOffset,PriorityEncoder(realMissPred))) 265 io.out.instrRange.zipWithIndex.map{case (bit,i) => bit := instRange(i).asBool()} 266 267 io.out.cfiOffset.valid := ParallelOR(realTakens) 268 io.out.cfiOffset.bits := PriorityEncoder(realTakens) 269 270 io.out.target := Mux(beyondFetch,io.out.pc.last + 2.U ,Mux(io.out.cfiOffset.valid, targets(io.out.cfiOffset.bits), realEndPC)) 271 io.out.takens := realTakens 272 273 io.out.jalTarget := targets(jumpOffset) 274 275 io.out.hasLastHalf := realHasLastHalf.reduce(_||_) 276 io.out.realEndPC := realEndPC 277 278 for (i <- 0 until PredictWidth) { 279 XSDebug(true.B, 280 p"instr ${Hexadecimal(io.out.instrs(i))}, " + 281 p"validStart ${Binary(validStart(i))}, " + 282 p"validEnd ${Binary(validEnd(i))}, " + 283 p"pc ${Hexadecimal(io.out.pc(i))}, " + 284 p"isRVC ${Binary(io.out.pd(i).isRVC)}, " + 285 p"brType ${Binary(io.out.pd(i).brType)}, " + 286 p"isRet ${Binary(io.out.pd(i).isRet)}, " + 287 p"isCall ${Binary(io.out.pd(i).isCall)}\n" 288 ) 289 } 290} 291 292class RVCExpander(implicit p: Parameters) extends XSModule { 293 val io = IO(new Bundle { 294 val in = Input(UInt(32.W)) 295 val out = Output(new ExpandedInstruction) 296 }) 297 298 if (HasCExtension) { 299 io.out := new RVCDecoder(io.in, XLEN).decode 300 } else { 301 io.out := new RVCDecoder(io.in, XLEN).passthrough 302 } 303} 304