Backend: fix s/shvstvala, updata xtvala when EX_VI

Backend: support Shvstvala and Sstvala extension

zfhmin:add zfhmin extensions

*decode unit adds decoding of zfhmin extension related instructions
*Re exemplified the functional units for scalar fpcvt

rv64v: fix uop split for vfwredsum instructions when lmul==8 (#3430)

Trigger: refactor trigger information in pipeline. (#3403)

LDU, Decode: add support for software prefetch (Zicbop) (#3356)

1. Support RVA23 SoftPrefetch instructions, include prefetch.i ,
prefetch.w and prefetch.r.
2. In DecodeUnit, add decode of SoftPref

LDU, Decode: add support for software prefetch (Zicbop) (#3356)

1. Support RVA23 SoftPrefetch instructions, include prefetch.i ,
prefetch.w and prefetch.r.
2. In DecodeUnit, add decode of SoftPrefetch.
3. prefetch.i ,prefetch.w and prefetch.r will be dispatched into
load-pipe, and then prefetch.w and prefetch.r execute like a load.
4. preftch.i just calculate address in loadUnit, then transfer address
to Frontend.(TODO)
5. All SoftPrefetch instructions return “ldout” signals to Backend in
stage3 wether hit or miss.

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csr: execute inst will raise EX_II when rm is reserved value.

* When 0 <= inst.rm <= 4, execute inst as usual.
* When inst.rm = 5/6, execute inst will raise EX_II.
* When inst.rm = 7, rm

csr: execute inst will raise EX_II when rm is reserved value.

* When 0 <= inst.rm <= 4, execute inst as usual.
* When inst.rm = 5/6, execute inst will raise EX_II.
* When inst.rm = 7, rm = frm.data. if frm.data > 4 will raise EX_II.

* Meanwhile, flush pipe when
* 1. wen frm CSR and wdata > 4
* 2. wen fcsr CSR and wdata(7, 5) > 4
* 3. wen frm/fcsr CSR and frm.rdata is reserved

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rv64v: fix temp vector register index which need to start from 32 (#3358)

Decode: fix assertion's condition of number of uop

* This commit fix the wrong assertion condition which should be `inValid && inUopInfo.numOfUop === 0.U` or `state === s_active && latchedUopInfo.nu

Decode: fix assertion's condition of number of uop

* This commit fix the wrong assertion condition which should be `inValid && inUopInfo.numOfUop === 0.U` or `state === s_active && latchedUopInfo.numOfUop === 0.U`

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fflags: fix a bug that vector float instruction do not write fflags.

Decode: fix bug of numOfUop is 0 when vector instruction is illegalInst

vtype: init vtype's vill to 1 and other fields to 0

vtype: enq spec vtype to vtypebuffer's snapshot (#3284)

rv64v: exception check for vector widening reduction instructions (#3243)

build: purge chisel 3 and add deprecation check (#3250)

NewCSR: Move xstatus.vs check to decodeUnit for csrr vl/vlenb

rv64v: fix fp type generate in exceptionGen and add check for vwsll (#3233)

uopsplit: fix uop num for vfredosum instruction (#3230)

rv64v: raise illegal exception when instruction is in ZVFH extension (#3221)

Decode: isComplex remove uopNum=/=1.U for fix timing (#3227)

New CSR implementation (#3167)

* CSR is splited into 4 major parts: CSR registers, CSR events, Permission Check and Trap Handler.
* Each CSR is seperated module.
* Add IMSIC module.
* Support new

New CSR implementation (#3167)

* CSR is splited into 4 major parts: CSR registers, CSR events, Permission Check and Trap Handler.
* Each CSR is seperated module.
* Add IMSIC module.
* Support new extensions, such as Sstc, Ssovfpmf and Smaia etc.
* Fix lots of bugs in old implementations, such as wrong permission checks and wrong WARL implementations.

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Decode: fix readyCounter timing (#3212)

Decode: flush pipe when vstart changed between zero and not zero by CSR inst

Decode: flush pipe when vstart is not zero

Decode: don't block backward when executing CSRR inst