1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import coupledL2.tl2chi._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.{max, min} 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBits: Int = 48, 72 GPAddrBits: Int = 50, 73 HasFPU: Boolean = true, 74 HasVPU: Boolean = true, 75 HasCustomCSRCacheOp: Boolean = true, 76 FetchWidth: Int = 8, 77 AsidLength: Int = 16, 78 VmidLength: Int = 14, 79 EnableBPU: Boolean = true, 80 EnableBPD: Boolean = true, 81 EnableRAS: Boolean = true, 82 EnableLB: Boolean = false, 83 EnableLoop: Boolean = true, 84 EnableSC: Boolean = true, 85 EnbaleTlbDebug: Boolean = false, 86 EnableClockGate: Boolean = true, 87 EnableJal: Boolean = false, 88 EnableFauFTB: Boolean = true, 89 EnableSv48: Boolean = true, 90 UbtbGHRLength: Int = 4, 91 // HistoryLength: Int = 512, 92 EnableGHistDiff: Boolean = true, 93 EnableCommitGHistDiff: Boolean = true, 94 UbtbSize: Int = 256, 95 FtbSize: Int = 2048, 96 RasSize: Int = 16, 97 RasSpecSize: Int = 32, 98 RasCtrSize: Int = 3, 99 CacheLineSize: Int = 512, 100 FtbWays: Int = 4, 101 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 102 // Sets Hist Tag 103 Seq(( 4096, 8, 8), 104 ( 4096, 13, 8), 105 ( 4096, 32, 8), 106 ( 4096, 119, 8)), 107 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 108 // Sets Hist Tag 109 Seq(( 256, 4, 9), 110 ( 256, 8, 9), 111 ( 512, 13, 9), 112 ( 512, 16, 9), 113 ( 512, 32, 9)), 114 SCNRows: Int = 512, 115 SCNTables: Int = 4, 116 SCCtrBits: Int = 6, 117 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 118 numBr: Int = 2, 119 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 120 (resp_in: BranchPredictionResp, p: Parameters) => { 121 val ftb = Module(new FTB()(p)) 122 val uftb = Module(new FauFTB()(p)) 123 val tage = Module(new Tage_SC()(p)) 124 val ras = Module(new RAS()(p)) 125 val ittage = Module(new ITTage()(p)) 126 val preds = Seq(uftb, tage, ftb, ittage, ras) 127 preds.map(_.io := DontCare) 128 129 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 130 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 131 132 uftb.io.in.bits.resp_in(0) := resp_in 133 tage.io.in.bits.resp_in(0) := uftb.io.out 134 ftb.io.in.bits.resp_in(0) := tage.io.out 135 ittage.io.in.bits.resp_in(0) := ftb.io.out 136 ras.io.in.bits.resp_in(0) := ittage.io.out 137 138 (preds, ras.io.out) 139 }, 140 ICacheForceMetaECCError: Boolean = false, 141 ICacheForceDataECCError: Boolean = false, 142 IBufSize: Int = 48, 143 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 144 DecodeWidth: Int = 6, 145 RenameWidth: Int = 6, 146 CommitWidth: Int = 8, 147 RobCommitWidth: Int = 8, 148 RabCommitWidth: Int = 6, 149 MaxUopSize: Int = 65, 150 EnableRenameSnapshot: Boolean = true, 151 RenameSnapshotNum: Int = 4, 152 FtqSize: Int = 64, 153 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 154 IntLogicRegs: Int = 32, 155 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 156 VecLogicRegs: Int = 32 + 15, // 15: tmp 157 V0LogicRegs: Int = 1, // V0 158 VlLogicRegs: Int = 1, // Vl 159 V0_IDX: Int = 0, 160 Vl_IDX: Int = 0, 161 NRPhyRegs: Int = 192, 162 VirtualLoadQueueSize: Int = 72, 163 LoadQueueRARSize: Int = 72, 164 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 165 RollbackGroupSize: Int = 8, 166 LoadQueueReplaySize: Int = 72, 167 LoadUncacheBufferSize: Int = 20, 168 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 169 StoreQueueSize: Int = 64, 170 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 171 StoreQueueForwardWithMask: Boolean = true, 172 VlsQueueSize: Int = 8, 173 RobSize: Int = 160, 174 RabSize: Int = 256, 175 VTypeBufferSize: Int = 64, // used to reorder vtype 176 IssueQueueSize: Int = 24, 177 IssueQueueCompEntrySize: Int = 16, 178 dpParams: DispatchParameters = DispatchParameters( 179 IntDqSize = 16, 180 FpDqSize = 16, 181 LsDqSize = 18, 182 IntDqDeqWidth = 8, 183 FpDqDeqWidth = 6, 184 VecDqDeqWidth = 6, 185 LsDqDeqWidth = 6, 186 ), 187 intPreg: PregParams = IntPregParams( 188 numEntries = 224, 189 numRead = None, 190 numWrite = None, 191 ), 192 fpPreg: PregParams = FpPregParams( 193 numEntries = 192, 194 numRead = None, 195 numWrite = None, 196 ), 197 vfPreg: VfPregParams = VfPregParams( 198 numEntries = 128, 199 numRead = None, 200 numWrite = None, 201 ), 202 v0Preg: V0PregParams = V0PregParams( 203 numEntries = 22, 204 numRead = None, 205 numWrite = None, 206 ), 207 vlPreg: VlPregParams = VlPregParams( 208 numEntries = 32, 209 numRead = None, 210 numWrite = None, 211 ), 212 IntRegCacheSize: Int = 16, 213 MemRegCacheSize: Int = 12, 214 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 215 IfuRedirectNum: Int = 1, 216 LoadPipelineWidth: Int = 3, 217 StorePipelineWidth: Int = 2, 218 VecLoadPipelineWidth: Int = 2, 219 VecStorePipelineWidth: Int = 2, 220 VecMemSrcInWidth: Int = 2, 221 VecMemInstWbWidth: Int = 1, 222 VecMemDispatchWidth: Int = 1, 223 VecMemDispatchMaxNumber: Int = 16, 224 VecMemUnitStrideMaxFlowNum: Int = 2, 225 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 2, 2, 2, 2, 2), 226 StoreBufferSize: Int = 16, 227 StoreBufferThreshold: Int = 7, 228 EnsbufferWidth: Int = 2, 229 LoadDependencyWidth: Int = 2, 230 // ============ VLSU ============ 231 VlMergeBufferSize: Int = 16, 232 VsMergeBufferSize: Int = 16, 233 UopWritebackWidth: Int = 2, 234 VLUopWritebackWidth: Int = 2, 235 VSUopWritebackWidth: Int = 1, 236 VSegmentBufferSize: Int = 8, 237 // ============================== 238 UncacheBufferSize: Int = 4, 239 EnableLoadToLoadForward: Boolean = false, 240 EnableFastForward: Boolean = true, 241 EnableLdVioCheckAfterReset: Boolean = true, 242 EnableSoftPrefetchAfterReset: Boolean = true, 243 EnableCacheErrorAfterReset: Boolean = true, 244 EnableAccurateLoadError: Boolean = false, 245 EnableUncacheWriteOutstanding: Boolean = false, 246 EnableHardwareStoreMisalign: Boolean = true, 247 EnableHardwareLoadMisalign: Boolean = true, 248 EnableStorePrefetchAtIssue: Boolean = false, 249 EnableStorePrefetchAtCommit: Boolean = false, 250 EnableAtCommitMissTrigger: Boolean = true, 251 EnableStorePrefetchSMS: Boolean = false, 252 EnableStorePrefetchSPB: Boolean = false, 253 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 254 MMUVmidLen: Int = 14, 255 ReSelectLen: Int = 7, // load replay queue replay select counter len 256 iwpuParameters: WPUParameters = WPUParameters( 257 enWPU = false, 258 algoName = "mmru", 259 isICache = true, 260 ), 261 dwpuParameters: WPUParameters = WPUParameters( 262 enWPU = false, 263 algoName = "mmru", 264 enCfPred = false, 265 isICache = false, 266 ), 267 itlbParameters: TLBParameters = TLBParameters( 268 name = "itlb", 269 fetchi = true, 270 useDmode = false, 271 NWays = 48, 272 ), 273 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 274 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 275 ldtlbParameters: TLBParameters = TLBParameters( 276 name = "ldtlb", 277 NWays = 48, 278 outReplace = false, 279 partialStaticPMP = true, 280 outsideRecvFlush = true, 281 saveLevel = false, 282 lgMaxSize = 4 283 ), 284 sttlbParameters: TLBParameters = TLBParameters( 285 name = "sttlb", 286 NWays = 48, 287 outReplace = false, 288 partialStaticPMP = true, 289 outsideRecvFlush = true, 290 saveLevel = false, 291 lgMaxSize = 4 292 ), 293 hytlbParameters: TLBParameters = TLBParameters( 294 name = "hytlb", 295 NWays = 48, 296 outReplace = false, 297 partialStaticPMP = true, 298 outsideRecvFlush = true, 299 saveLevel = false, 300 lgMaxSize = 4 301 ), 302 pftlbParameters: TLBParameters = TLBParameters( 303 name = "pftlb", 304 NWays = 48, 305 outReplace = false, 306 partialStaticPMP = true, 307 outsideRecvFlush = true, 308 saveLevel = false, 309 lgMaxSize = 4 310 ), 311 l2ToL1tlbParameters: TLBParameters = TLBParameters( 312 name = "l2tlb", 313 NWays = 48, 314 outReplace = false, 315 partialStaticPMP = true, 316 outsideRecvFlush = true, 317 saveLevel = false 318 ), 319 refillBothTlb: Boolean = false, 320 btlbParameters: TLBParameters = TLBParameters( 321 name = "btlb", 322 NWays = 48, 323 ), 324 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 325 NumPerfCounters: Int = 16, 326 icacheParameters: ICacheParameters = ICacheParameters( 327 tagECC = Some("parity"), 328 dataECC = Some("parity"), 329 replacer = Some("setplru"), 330 ), 331 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 332 tagECC = Some("secded"), 333 dataECC = Some("secded"), 334 replacer = Some("setplru"), 335 nMissEntries = 16, 336 nProbeEntries = 8, 337 nReleaseEntries = 18, 338 nMaxPrefetchEntry = 6, 339 )), 340 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 341 name = "l2", 342 ways = 8, 343 sets = 1024, // default 512KB L2 344 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 345 coupledL2.prefetch.TPParameters()), 346 )), 347 L2NBanks: Int = 1, 348 usePTWRepeater: Boolean = false, 349 softTLB: Boolean = false, // dpi-c l1tlb debug only 350 softPTW: Boolean = false, // dpi-c l2tlb debug only 351 softPTWDelay: Int = 1 352){ 353 def vlWidth = log2Up(VLEN) + 1 354 355 /** 356 * the minimum element length of vector elements 357 */ 358 val minVecElen: Int = 8 359 360 /** 361 * the maximum number of elements in vector register 362 */ 363 val maxElemPerVreg: Int = VLEN / minVecElen 364 365 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 366 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 367 368 val RegCacheSize = IntRegCacheSize + MemRegCacheSize 369 val RegCacheIdxWidth = log2Up(RegCacheSize) 370 371 val intSchdParams = { 372 implicit val schdType: SchedulerType = IntScheduler() 373 SchdBlockParams(Seq( 374 IssueBlockParams(Seq( 375 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 376 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1))), true, 2), 377 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 378 IssueBlockParams(Seq( 379 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 380 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1))), true, 2), 381 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 382 IssueBlockParams(Seq( 383 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 384 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = 0, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 385 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 386 IssueBlockParams(Seq( 387 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 388 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 389 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 390 ), 391 numPregs = intPreg.numEntries, 392 numDeqOutside = 0, 393 schdType = schdType, 394 rfDataWidth = intPreg.dataCfg.dataWidth, 395 numUopIn = dpParams.IntDqDeqWidth, 396 ) 397 } 398 399 val fpSchdParams = { 400 implicit val schdType: SchedulerType = FpScheduler() 401 SchdBlockParams(Seq( 402 IssueBlockParams(Seq( 403 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 404 ), numEntries = 18, numEnq = 2, numComp = 16), 405 IssueBlockParams(Seq( 406 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 407 ), numEntries = 18, numEnq = 2, numComp = 16), 408 IssueBlockParams(Seq( 409 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 410 ), numEntries = 18, numEnq = 2, numComp = 16), 411 IssueBlockParams(Seq( 412 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 413 ), numEntries = 18, numEnq = 2, numComp = 16), 414 IssueBlockParams(Seq( 415 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 416 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 417 ), numEntries = 18, numEnq = 2, numComp = 16), 418 ), 419 numPregs = fpPreg.numEntries, 420 numDeqOutside = 0, 421 schdType = schdType, 422 rfDataWidth = fpPreg.dataCfg.dataWidth, 423 numUopIn = dpParams.VecDqDeqWidth, 424 ) 425 } 426 427 val vfSchdParams = { 428 implicit val schdType: SchedulerType = VfScheduler() 429 SchdBlockParams(Seq( 430 IssueBlockParams(Seq( 431 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 432 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = 1, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 433 ), numEntries = 16, numEnq = 2, numComp = 14), 434 IssueBlockParams(Seq( 435 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 436 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 437 ), numEntries = 16, numEnq = 2, numComp = 14), 438 IssueBlockParams(Seq( 439 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 440 ), numEntries = 10, numEnq = 2, numComp = 8), 441 ), 442 numPregs = vfPreg.numEntries, 443 numDeqOutside = 0, 444 schdType = schdType, 445 rfDataWidth = vfPreg.dataCfg.dataWidth, 446 numUopIn = dpParams.VecDqDeqWidth, 447 ) 448 } 449 450 val memSchdParams = { 451 implicit val schdType: SchedulerType = MemScheduler() 452 val rfDataWidth = 64 453 454 SchdBlockParams(Seq( 455 IssueBlockParams(Seq( 456 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))), 457 ), numEntries = 16, numEnq = 2, numComp = 14), 458 IssueBlockParams(Seq( 459 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))), 460 ), numEntries = 16, numEnq = 2, numComp = 14), 461 IssueBlockParams(Seq( 462 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(8, 0))), true, 2), 463 ), numEntries = 16, numEnq = 2, numComp = 14), 464 IssueBlockParams(Seq( 465 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(9, 0))), true, 2), 466 ), numEntries = 16, numEnq = 2, numComp = 14), 467 IssueBlockParams(Seq( 468 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(10, 0))), true, 2), 469 ), numEntries = 16, numEnq = 2, numComp = 14), 470 IssueBlockParams(Seq( 471 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 472 ), numEntries = 16, numEnq = 2, numComp = 14), 473 IssueBlockParams(Seq( 474 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 475 ), numEntries = 16, numEnq = 2, numComp = 14), 476 IssueBlockParams(Seq( 477 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(12, 0)))), 478 ), numEntries = 16, numEnq = 2, numComp = 14), 479 IssueBlockParams(Seq( 480 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(13, 0)))), 481 ), numEntries = 16, numEnq = 2, numComp = 14), 482 ), 483 numPregs = intPreg.numEntries max vfPreg.numEntries, 484 numDeqOutside = 0, 485 schdType = schdType, 486 rfDataWidth = rfDataWidth, 487 numUopIn = dpParams.LsDqDeqWidth, 488 ) 489 } 490 491 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 492 493 def iqWakeUpParams = { 494 Seq( 495 WakeUpConfig( 496 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 497 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 498 ), 499 // TODO: add load -> fp slow wakeup 500 WakeUpConfig( 501 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 502 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 503 ), 504 WakeUpConfig( 505 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 506 Seq("STD0", "STD1") 507 ), 508// WakeUpConfig( 509// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 510// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") 511// ), 512 ).flatten 513 } 514 515 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 516 517 val backendParams: BackendParams = backend.BackendParams( 518 Map( 519 IntScheduler() -> intSchdParams, 520 FpScheduler() -> fpSchdParams, 521 VfScheduler() -> vfSchdParams, 522 MemScheduler() -> memSchdParams, 523 ), 524 Seq( 525 intPreg, 526 fpPreg, 527 vfPreg, 528 v0Preg, 529 vlPreg, 530 fakeIntPreg 531 ), 532 iqWakeUpParams, 533 ) 534} 535 536case object DebugOptionsKey extends Field[DebugOptions] 537 538case class DebugOptions 539( 540 FPGAPlatform: Boolean = false, 541 ResetGen: Boolean = false, 542 EnableDifftest: Boolean = false, 543 AlwaysBasicDiff: Boolean = true, 544 EnableDebug: Boolean = false, 545 EnablePerfDebug: Boolean = true, 546 UseDRAMSim: Boolean = false, 547 EnableConstantin: Boolean = false, 548 EnableChiselDB: Boolean = false, 549 AlwaysBasicDB: Boolean = true, 550 EnableRollingDB: Boolean = false 551) 552 553trait HasXSParameter { 554 555 implicit val p: Parameters 556 557 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 558 final val PageOffsetWidth = 12 559 def NodeIDWidth = p(SoCParamsKey).NodeIDWidthList(p(CHIIssue)) // NodeID width among NoC 560 561 def coreParams = p(XSCoreParamsKey) 562 def env = p(DebugOptionsKey) 563 564 def XLEN = coreParams.XLEN 565 def VLEN = coreParams.VLEN 566 def ELEN = coreParams.ELEN 567 def HSXLEN = coreParams.HSXLEN 568 val minFLen = 32 569 val fLen = 64 570 def hartIdLen = p(MaxHartIdBits) 571 val xLen = XLEN 572 573 def HasMExtension = coreParams.HasMExtension 574 def HasCExtension = coreParams.HasCExtension 575 def HasHExtension = coreParams.HasHExtension 576 def EnableSv48 = coreParams.EnableSv48 577 def HasDiv = coreParams.HasDiv 578 def HasIcache = coreParams.HasICache 579 def HasDcache = coreParams.HasDCache 580 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 581 def GPAddrBits = coreParams.GPAddrBits 582 def VAddrBits = { 583 if (HasHExtension) { 584 coreParams.GPAddrBits 585 } else { 586 coreParams.VAddrBits 587 } 588 } // VAddrBits is Virtual Memory addr bits 589 require(PAddrBits == 48 || !EnableSv48) // Paddr bits should be 48 when Sv48 enable 590 591 def VAddrMaxBits = coreParams.VAddrBits max coreParams.GPAddrBits 592 593 def AsidLength = coreParams.AsidLength 594 def VmidLength = coreParams.VmidLength 595 def ReSelectLen = coreParams.ReSelectLen 596 def AddrBytes = AddrBits / 8 // unused 597 def DataBits = XLEN 598 def DataBytes = DataBits / 8 599 def VDataBytes = VLEN / 8 600 def HasFPU = coreParams.HasFPU 601 def HasVPU = coreParams.HasVPU 602 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 603 def FetchWidth = coreParams.FetchWidth 604 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 605 def EnableBPU = coreParams.EnableBPU 606 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 607 def EnableRAS = coreParams.EnableRAS 608 def EnableLB = coreParams.EnableLB 609 def EnableLoop = coreParams.EnableLoop 610 def EnableSC = coreParams.EnableSC 611 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 612 def HistoryLength = coreParams.HistoryLength 613 def EnableGHistDiff = coreParams.EnableGHistDiff 614 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 615 def EnableClockGate = coreParams.EnableClockGate 616 def UbtbGHRLength = coreParams.UbtbGHRLength 617 def UbtbSize = coreParams.UbtbSize 618 def EnableFauFTB = coreParams.EnableFauFTB 619 def FtbSize = coreParams.FtbSize 620 def FtbWays = coreParams.FtbWays 621 def RasSize = coreParams.RasSize 622 def RasSpecSize = coreParams.RasSpecSize 623 def RasCtrSize = coreParams.RasCtrSize 624 625 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 626 coreParams.branchPredictor(resp_in, p) 627 } 628 def numBr = coreParams.numBr 629 def TageTableInfos = coreParams.TageTableInfos 630 def TageBanks = coreParams.numBr 631 def SCNRows = coreParams.SCNRows 632 def SCCtrBits = coreParams.SCCtrBits 633 def SCHistLens = coreParams.SCHistLens 634 def SCNTables = coreParams.SCNTables 635 636 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 637 case ((n, cb), h) => (n, cb, h) 638 } 639 def ITTageTableInfos = coreParams.ITTageTableInfos 640 type FoldedHistoryInfo = Tuple2[Int, Int] 641 def foldedGHistInfos = 642 (TageTableInfos.map{ case (nRows, h, t) => 643 if (h > 0) 644 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 645 else 646 Set[FoldedHistoryInfo]() 647 }.reduce(_++_).toSet ++ 648 SCTableInfos.map{ case (nRows, _, h) => 649 if (h > 0) 650 Set((h, min(log2Ceil(nRows/TageBanks), h))) 651 else 652 Set[FoldedHistoryInfo]() 653 }.reduce(_++_).toSet ++ 654 ITTageTableInfos.map{ case (nRows, h, t) => 655 if (h > 0) 656 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 657 else 658 Set[FoldedHistoryInfo]() 659 }.reduce(_++_) ++ 660 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 661 ).toList 662 663 664 665 def CacheLineSize = coreParams.CacheLineSize 666 def CacheLineHalfWord = CacheLineSize / 16 667 def ExtHistoryLength = HistoryLength + 64 668 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 669 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 670 def IBufSize = coreParams.IBufSize 671 def IBufNBank = coreParams.IBufNBank 672 def backendParams: BackendParams = coreParams.backendParams 673 def DecodeWidth = coreParams.DecodeWidth 674 def RenameWidth = coreParams.RenameWidth 675 def CommitWidth = coreParams.CommitWidth 676 def RobCommitWidth = coreParams.RobCommitWidth 677 def RabCommitWidth = coreParams.RabCommitWidth 678 def MaxUopSize = coreParams.MaxUopSize 679 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 680 def RenameSnapshotNum = coreParams.RenameSnapshotNum 681 def FtqSize = coreParams.FtqSize 682 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 683 def IntLogicRegs = coreParams.IntLogicRegs 684 def FpLogicRegs = coreParams.FpLogicRegs 685 def VecLogicRegs = coreParams.VecLogicRegs 686 def V0LogicRegs = coreParams.V0LogicRegs 687 def VlLogicRegs = coreParams.VlLogicRegs 688 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 689 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 690 def V0_IDX = coreParams.V0_IDX 691 def Vl_IDX = coreParams.Vl_IDX 692 def IntPhyRegs = coreParams.intPreg.numEntries 693 def FpPhyRegs = coreParams.fpPreg.numEntries 694 def VfPhyRegs = coreParams.vfPreg.numEntries 695 def V0PhyRegs = coreParams.v0Preg.numEntries 696 def VlPhyRegs = coreParams.vlPreg.numEntries 697 def MaxPhyPregs = IntPhyRegs max VfPhyRegs 698 def PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(FpPhyRegs) max log2Up(VfPhyRegs) 699 def RobSize = coreParams.RobSize 700 def RabSize = coreParams.RabSize 701 def VTypeBufferSize = coreParams.VTypeBufferSize 702 def IntRegCacheSize = coreParams.IntRegCacheSize 703 def MemRegCacheSize = coreParams.MemRegCacheSize 704 def RegCacheSize = coreParams.RegCacheSize 705 def RegCacheIdxWidth = coreParams.RegCacheIdxWidth 706 /** 707 * the minimum element length of vector elements 708 */ 709 def minVecElen: Int = coreParams.minVecElen 710 711 /** 712 * the maximum number of elements in vector register 713 */ 714 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 715 716 def IntRefCounterWidth = log2Ceil(RobSize) 717 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 718 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 719 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 720 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 721 def LoadQueueRARSize = coreParams.LoadQueueRARSize 722 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 723 def RollbackGroupSize = coreParams.RollbackGroupSize 724 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 725 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 726 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 727 def StoreQueueSize = coreParams.StoreQueueSize 728 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 729 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 730 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 731 def VlsQueueSize = coreParams.VlsQueueSize 732 def dpParams = coreParams.dpParams 733 734 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 735 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 736 737 def NumRedirect = backendParams.numRedirect 738 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 739 def FtqRedirectAheadNum = NumRedirect 740 def IfuRedirectNum = coreParams.IfuRedirectNum 741 def LoadPipelineWidth = coreParams.LoadPipelineWidth 742 def StorePipelineWidth = coreParams.StorePipelineWidth 743 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 744 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 745 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 746 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 747 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 748 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 749 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 750 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 751 def StoreBufferSize = coreParams.StoreBufferSize 752 def StoreBufferThreshold = coreParams.StoreBufferThreshold 753 def EnsbufferWidth = coreParams.EnsbufferWidth 754 def LoadDependencyWidth = coreParams.LoadDependencyWidth 755 def VlMergeBufferSize = coreParams.VlMergeBufferSize 756 def VsMergeBufferSize = coreParams.VsMergeBufferSize 757 def UopWritebackWidth = coreParams.UopWritebackWidth 758 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 759 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 760 def VSegmentBufferSize = coreParams.VSegmentBufferSize 761 def UncacheBufferSize = coreParams.UncacheBufferSize 762 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 763 def EnableFastForward = coreParams.EnableFastForward 764 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 765 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 766 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 767 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 768 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 769 def EnableHardwareStoreMisalign = coreParams.EnableHardwareStoreMisalign 770 def EnableHardwareLoadMisalign = coreParams.EnableHardwareLoadMisalign 771 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 772 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 773 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 774 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 775 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 776 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 777 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 778 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 779 def asidLen = coreParams.MMUAsidLen 780 def vmidLen = coreParams.MMUVmidLen 781 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 782 def refillBothTlb = coreParams.refillBothTlb 783 def iwpuParam = coreParams.iwpuParameters 784 def dwpuParam = coreParams.dwpuParameters 785 def itlbParams = coreParams.itlbParameters 786 def ldtlbParams = coreParams.ldtlbParameters 787 def sttlbParams = coreParams.sttlbParameters 788 def hytlbParams = coreParams.hytlbParameters 789 def pftlbParams = coreParams.pftlbParameters 790 def l2ToL1Params = coreParams.l2ToL1tlbParameters 791 def btlbParams = coreParams.btlbParameters 792 def l2tlbParams = coreParams.l2tlbParameters 793 def NumPerfCounters = coreParams.NumPerfCounters 794 795 def instBytes = if (HasCExtension) 2 else 4 796 def instOffsetBits = log2Ceil(instBytes) 797 798 def icacheParameters = coreParams.icacheParameters 799 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 800 801 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 802 // for constrained LR/SC loop 803 def LRSCCycles = 64 804 // for lr storm 805 def LRSCBackOff = 8 806 807 // cache hierarchy configurations 808 def l1BusDataWidth = 256 809 810 // load violation predict 811 def ResetTimeMax2Pow = 20 //1078576 812 def ResetTimeMin2Pow = 10 //1024 813 // wait table parameters 814 def WaitTableSize = 1024 815 def MemPredPCWidth = log2Up(WaitTableSize) 816 def LWTUse2BitCounter = true 817 // store set parameters 818 def SSITSize = WaitTableSize 819 def LFSTSize = 32 820 def SSIDWidth = log2Up(LFSTSize) 821 def LFSTWidth = 4 822 def StoreSetEnable = true // LWT will be disabled if SS is enabled 823 def LFSTEnable = true 824 825 def PCntIncrStep: Int = 6 826 def numPCntHc: Int = 25 827 def numPCntPtw: Int = 19 828 829 def numCSRPCntFrontend = 8 830 def numCSRPCntCtrl = 8 831 def numCSRPCntLsu = 8 832 def numCSRPCntHc = 5 833 def printEventCoding = true 834 835 // Parameters for Sdtrig extension 836 protected def TriggerNum = 4 837 protected def TriggerChainMaxLength = 2 838} 839