| #
25df626e |
| 04-May-2024 |
good-circle <[email protected]> |
Merge branch 'master' into vlsu-tmp-master
|
| #
d8ceb649 |
| 26-Apr-2024 |
Ziyue Zhang <[email protected]> |
rv64v: fix some corner case when reduction intsurctinos depend on oldvd
|
| #
b6279fc6 |
| 24-Apr-2024 |
Ziyue Zhang <[email protected]> |
rv64v: add ignore oldvd judgement in issue queue
1. when the instruction depend on old vd, we cannot set the srctype to imm
2. when vl = 0, we cannot set the srctype to imm because the vd keep the ol
rv64v: add ignore oldvd judgement in issue queue
1. when the instruction depend on old vd, we cannot set the srctype to imm
2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value
3. when vl = vlmax, we can set srctype to imm when vta is not se
show more ...
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| #
d362dcf0 |
| 14-Apr-2024 |
Anzooooo <[email protected]> |
VLSU: fix width of flowNum
|
| #
6dbb4e08 |
| 28-Mar-2024 |
Xuan Hu <[email protected]> |
Backend: support vector load&store better
* Todo: add more IQs for vector load&store
* Todo: make vector memory inst issue out of order
* Todo: fix bugs
|
| #
26af847e |
| 25-Mar-2024 |
good-circle <[email protected]> |
rv64v: implement lsu & lsq vector datapath
|
| #
f3a9fb05 |
| 27-Mar-2024 |
Anzo <[email protected]> |
rv64v: add support for vlsu continuous 'uop' (#2816)
add LSQ backpressure logic and 'uop' continuous application LSQ entries logic
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| #
3952421b |
| 24-Mar-2024 |
weiding liu <[email protected]> |
rv64v: rewrite VLSU
uop split in V*SplitImp, flow merge in V*MergeBufferImp, uop issued out of order
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| #
ec49b127 |
| 19-Apr-2024 |
sinsanction <[email protected]> |
Backend: reduce the width of LoadDependency to 2 bits
|
| #
3af3539f |
| 18-Apr-2024 |
Ziyue Zhang <[email protected]> |
rv64v: set vs to dirty when running vector instructions (#2892)
|
| #
e25e4d90 |
| 11-Apr-2024 |
Xuan Hu <[email protected]> |
Merge remote-tracking branch 'upstream/master' into tmp-master
TODO: add gpaddr data path from frontend to backend
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| #
49f433de |
| 02-Apr-2024 |
Xuan Hu <[email protected]> |
Backend: use no-split fusion-imm implementation
* The width of immediate number is expand to 32 bits to fit the requirement of long data width.
* Remove the lsrc bundle in DynInst
|
| #
29dbac5a |
| 15-Mar-2024 |
sinsanction <[email protected]> |
Backend: remove unused pcMem read for exu in CtrlBlock (moved to PcTargetMem (OG0))
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| #
0c01a27a |
| 09-Mar-2024 |
Haojin Tang <[email protected]> |
top-down: fix wrong fuType caused by uop split
|
| #
5edcc45f |
| 08-Mar-2024 |
Haojin Tang <[email protected]> |
Parameters: remove write port configs for store
|
| #
c90e3eac |
| 26-Jan-2024 |
Ziyue Zhang <[email protected]> |
rv64v: fix uop spilt and mask generate for vlm
|
| #
66f72636 |
| 17-Jan-2024 |
xiaofeibao-xjtu <[email protected]> |
DataPath: og1 imm extract
|
| #
34ee0dac |
| 17-Jan-2024 |
xiaofeibao-xjtu <[email protected]> |
RFRead: RfReadValidBundle remove srcType
|
| #
691f3cef |
| 05-Jan-2024 |
zhanglyGit <[email protected]> |
DataPath: fix uop_rf_addr index bug
|
| #
a01a12bb |
| 20-Dec-2023 |
Haojin Tang <[email protected]> |
IssueQueue: connect missing wakeup copy signals
|
| #
596af5d2 |
| 20-Dec-2023 |
Haojin Tang <[email protected]> |
Scheduler: implement wakeup from LoadUnit
|
| #
aa2bcc31 |
| 19-Dec-2023 |
zhanglyGit <[email protected]> |
Backend: refactor Entries
|
| #
2aaa83c0 |
| 08-Dec-2023 |
xiaofeibao-xjtu <[email protected]> |
backend: WBArbiter support two out at same time, fast wakeup remove valid
|
| #
4c5a0d77 |
| 06-Dec-2023 |
xiaofeibao-xjtu <[email protected]> |
WakeupQueue: Copy all bits
|
| #
0c7ebb58 |
| 04-Dec-2023 |
xiaofeibao-xjtu <[email protected]> |
WakeupQueue: pdest copy
|