1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, IssueQueueJumpBundle, SchedulerType, EntryDeqRespBundle} 19import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 20import xiangshan.backend.rob.RobPtr 21import xiangshan.frontend._ 22import xiangshan.mem.{LqPtr, SqPtr} 23 24object Bundles { 25 /** 26 * Connect Same Name Port like bundleSource := bundleSinkBudle. 27 * 28 * There is no limit to the number of ports on both sides. 29 * 30 * Don't forget to connect the remaining ports! 31 */ 32 def connectSamePort (bundleSource: Bundle, bundleSink: Bundle):Unit = { 33 bundleSource.elements.foreach { case (name, data) => 34 if (bundleSink.elements.contains(name)) 35 data := bundleSink.elements(name) 36 } 37 } 38 // frontend -> backend 39 class StaticInst(implicit p: Parameters) extends XSBundle { 40 val instr = UInt(32.W) 41 val pc = UInt(VAddrBits.W) 42 val foldpc = UInt(MemPredPCWidth.W) 43 val exceptionVec = ExceptionVec() 44 val trigger = new TriggerCf 45 val preDecodeInfo = new PreDecodeInfo 46 val pred_taken = Bool() 47 val crossPageIPFFix = Bool() 48 val ftqPtr = new FtqPtr 49 val ftqOffset = UInt(log2Up(PredictWidth).W) 50 51 def connectCtrlFlow(source: CtrlFlow): Unit = { 52 this.instr := source.instr 53 this.pc := source.pc 54 this.foldpc := source.foldpc 55 this.exceptionVec := source.exceptionVec 56 this.trigger := source.trigger 57 this.preDecodeInfo := source.pd 58 this.pred_taken := source.pred_taken 59 this.crossPageIPFFix := source.crossPageIPFFix 60 this.ftqPtr := source.ftqPtr 61 this.ftqOffset := source.ftqOffset 62 } 63 } 64 65 // StaticInst --[Decode]--> DecodedInst 66 class DecodedInst(implicit p: Parameters) extends XSBundle { 67 def numSrc = backendParams.numSrc 68 // passed from StaticInst 69 val instr = UInt(32.W) 70 val pc = UInt(VAddrBits.W) 71 val foldpc = UInt(MemPredPCWidth.W) 72 val exceptionVec = ExceptionVec() 73 val trigger = new TriggerCf 74 val preDecodeInfo = new PreDecodeInfo 75 val pred_taken = Bool() 76 val crossPageIPFFix = Bool() 77 val ftqPtr = new FtqPtr 78 val ftqOffset = UInt(log2Up(PredictWidth).W) 79 // decoded 80 val srcType = Vec(numSrc, SrcType()) 81 val lsrc = Vec(numSrc, UInt(6.W)) 82 val ldest = UInt(6.W) 83 val fuType = FuType() 84 val fuOpType = FuOpType() 85 val rfWen = Bool() 86 val fpWen = Bool() 87 val vecWen = Bool() 88 val isXSTrap = Bool() 89 val waitForward = Bool() // no speculate execution 90 val blockBackward = Bool() 91 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 92 val canRobCompress = Bool() 93 val selImm = SelImm() 94 val imm = UInt(ImmUnion.maxLen.W) 95 val fpu = new FPUCtrlSignals 96 val vpu = new VPUCtrlSignals 97 val vlsInstr = Bool() 98 val wfflags = Bool() 99 val isMove = Bool() 100 val uopIdx = UopIdx() 101 val uopSplitType = UopSplitType() 102 val isVset = Bool() 103 val firstUop = Bool() 104 val lastUop = Bool() 105 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 106 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 107 val commitType = CommitType() // Todo: remove it 108 109 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 110 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 111 112 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 113 val decoder: Seq[UInt] = ListLookup( 114 inst, XDecode.decodeDefault.map(bitPatToUInt), 115 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 116 ) 117 allSignals zip decoder foreach { case (s, d) => s := d } 118 this 119 } 120 121 def isSoftPrefetch: Bool = { 122 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 123 } 124 125 def connectStaticInst(source: StaticInst): Unit = { 126 for ((name, data) <- this.elements) { 127 if (source.elements.contains(name)) { 128 data := source.elements(name) 129 } 130 } 131 } 132 } 133 134 // DecodedInst --[Rename]--> DynInst 135 class DynInst(implicit p: Parameters) extends XSBundle { 136 def numSrc = backendParams.numSrc 137 // passed from StaticInst 138 val instr = UInt(32.W) 139 val pc = UInt(VAddrBits.W) 140 val foldpc = UInt(MemPredPCWidth.W) 141 val exceptionVec = ExceptionVec() 142 val trigger = new TriggerCf 143 val preDecodeInfo = new PreDecodeInfo 144 val pred_taken = Bool() 145 val crossPageIPFFix = Bool() 146 val ftqPtr = new FtqPtr 147 val ftqOffset = UInt(log2Up(PredictWidth).W) 148 // passed from DecodedInst 149 val srcType = Vec(numSrc, SrcType()) 150 val lsrc = Vec(numSrc, UInt(6.W)) 151 val ldest = UInt(6.W) 152 val fuType = FuType() 153 val fuOpType = FuOpType() 154 val rfWen = Bool() 155 val fpWen = Bool() 156 val vecWen = Bool() 157 val isXSTrap = Bool() 158 val waitForward = Bool() // no speculate execution 159 val blockBackward = Bool() 160 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 161 val canRobCompress = Bool() 162 val selImm = SelImm() 163 val imm = UInt(32.W) 164 val fpu = new FPUCtrlSignals 165 val vpu = new VPUCtrlSignals 166 val vlsInstr = Bool() 167 val wfflags = Bool() 168 val isMove = Bool() 169 val uopIdx = UopIdx() 170 val isVset = Bool() 171 val firstUop = Bool() 172 val lastUop = Bool() 173 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 174 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 175 val commitType = CommitType() 176 // rename 177 val srcState = Vec(numSrc, SrcState()) 178 val srcLoadDependency = Vec(numSrc, Vec(LoadPipelineWidth, UInt(3.W))) 179 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 180 val pdest = UInt(PhyRegIdxWidth.W) 181 val robIdx = new RobPtr 182 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 183 val dirtyFs = Bool() 184 185 val eliminatedMove = Bool() 186 // Take snapshot at this CFI inst 187 val snapshot = Bool() 188 val debugInfo = new PerfDebugInfo 189 val storeSetHit = Bool() // inst has been allocated an store set 190 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 191 // Load wait is needed 192 // load inst will not be executed until former store (predicted by mdp) addr calcuated 193 val loadWaitBit = Bool() 194 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 195 // load inst will not be executed until ALL former store addr calcuated 196 val loadWaitStrict = Bool() 197 val ssid = UInt(SSIDWidth.W) 198 // Todo 199 val lqIdx = new LqPtr 200 val sqIdx = new SqPtr 201 // debug module 202 val singleStep = Bool() 203 // schedule 204 val replayInst = Bool() 205 206 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 207 def isLUI32: Bool = this.selImm === SelImm.IMM_LUI32 208 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 209 210 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 211 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 212 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 213 214 def srcIsReady: Vec[Bool] = { 215 VecInit(this.srcType.zip(this.srcState).map { 216 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 217 }) 218 } 219 220 def clearExceptions( 221 exceptionBits: Seq[Int] = Seq(), 222 flushPipe : Boolean = false, 223 replayInst : Boolean = false 224 ): DynInst = { 225 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 226 if (!flushPipe) { this.flushPipe := false.B } 227 if (!replayInst) { this.replayInst := false.B } 228 this 229 } 230 231 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen 232 } 233 234 trait BundleSource { 235 var wakeupSource = "undefined" 236 var idx = 0 237 } 238 239 /** 240 * 241 * @param pregIdxWidth index width of preg 242 * @param exuIndices exu indices of wakeup bundle 243 */ 244 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int]) extends Bundle { 245 val rfWen = Bool() 246 val fpWen = Bool() 247 val vecWen = Bool() 248 val pdest = UInt(pregIdxWidth.W) 249 250 /** 251 * @param successor Seq[(psrc, srcType)] 252 * @return Seq[if wakeup psrc] 253 */ 254 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 255 successor.map { case (thatPsrc, srcType) => 256 val pdestMatch = pdest === thatPsrc 257 pdestMatch && ( 258 SrcType.isFp(srcType) && this.fpWen || 259 SrcType.isXp(srcType) && this.rfWen || 260 SrcType.isVp(srcType) && this.vecWen 261 ) && valid 262 } 263 } 264 265 def hasOnlyOneSource: Boolean = exuIndices.size == 1 266 267 def hasMultiSources: Boolean = exuIndices.size > 1 268 269 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 270 271 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 272 273 def exuIdx: Int = { 274 require(hasOnlyOneSource) 275 this.exuIndices.head 276 } 277 } 278 279 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 280 281 } 282 283class IssueQueueIQWakeUpBundle( 284 exuIdx: Int, 285 backendParams: BackendParams, 286 copyPdest: Boolean = false, 287 copyNum: Int = 0 288) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 289 val loadDependency = Vec(backendParams.LduCnt + backendParams.HyuCnt, UInt(3.W)) 290 val is0Lat = Bool() 291 val pdestCopy = if (copyPdest) Some(Vec(copyNum, UInt(this.pdest.getWidth.W))) else None 292 def fromExuInput(exuInput: ExuInput, l2ExuVecs: Vec[UInt]): Unit = { 293 this.rfWen := exuInput.rfWen.getOrElse(false.B) 294 this.fpWen := exuInput.fpWen.getOrElse(false.B) 295 this.vecWen := exuInput.vecWen.getOrElse(false.B) 296 this.pdest := exuInput.pdest 297 } 298 299 def fromExuInput(exuInput: ExuInput): Unit = { 300 this.rfWen := exuInput.rfWen.getOrElse(false.B) 301 this.fpWen := exuInput.fpWen.getOrElse(false.B) 302 this.vecWen := exuInput.vecWen.getOrElse(false.B) 303 this.pdest := exuInput.pdest 304 } 305 } 306 307 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 308 // vtype 309 val vill = Bool() 310 val vma = Bool() // 1: agnostic, 0: undisturbed 311 val vta = Bool() // 1: agnostic, 0: undisturbed 312 val vsew = VSew() 313 val vlmul = VLmul() // 1/8~8 --> -3~3 314 315 val vm = Bool() // 0: need v0.t 316 val vstart = Vl() 317 318 // float rounding mode 319 val frm = Frm() 320 // scalar float instr and vector float reduction 321 val fpu = Fpu() 322 // vector fix int rounding mode 323 val vxrm = Vxrm() 324 // vector uop index, exclude other non-vector uop 325 val vuopIdx = UopIdx() 326 val lastUop = Bool() 327 // maybe used if data dependancy 328 val vmask = UInt(MaskSrcData().dataWidth.W) 329 val vl = Vl() 330 331 // vector load/store 332 val nf = Nf() 333 val veew = VEew() 334 335 val isReverse = Bool() // vrsub, vrdiv 336 val isExt = Bool() 337 val isNarrow = Bool() 338 val isDstMask = Bool() // vvm, vvvm, mmm 339 val isOpMask = Bool() // vmand, vmnand 340 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 341 342 def vtype: VType = { 343 val res = Wire(VType()) 344 res.illegal := this.vill 345 res.vma := this.vma 346 res.vta := this.vta 347 res.vsew := this.vsew 348 res.vlmul := this.vlmul 349 res 350 } 351 352 def vconfig: VConfig = { 353 val res = Wire(VConfig()) 354 res.vtype := this.vtype 355 res.vl := this.vl 356 res 357 } 358 359 def connectVType(source: VType): Unit = { 360 this.vill := source.illegal 361 this.vma := source.vma 362 this.vta := source.vta 363 this.vsew := source.vsew 364 this.vlmul := source.vlmul 365 } 366 } 367 368 // DynInst --[IssueQueue]--> DataPath 369 class IssueQueueIssueBundle( 370 iqParams: IssueBlockParams, 371 val exuParams: ExeUnitParams, 372 )(implicit 373 p: Parameters 374 ) extends Bundle { 375 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 376 // check which set both have fp and vec and remove fp 377 private val rfReadDataCfgSetFilterFp = rfReadDataCfgSet.map((set: Set[DataConfig]) => 378 if (set.contains(FpData()) && set.contains(VecData())) set.filter(_ != FpData()) 379 else set 380 ) 381 382 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 383 rfReadDataCfgSetFilterFp.map((set: Set[DataConfig]) => 384 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 385 ) 386 )) 387 388 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 389 val immType = SelImm() // used to select imm extractor 390 val common = new ExuInput(exuParams) 391 val addrOH = UInt(iqParams.numEntries.W) 392 393 def exuIdx = exuParams.exuIdx 394 def getSource: SchedulerType = exuParams.getWBSource 395 def getIntWbBusyBundle = common.rfWen.toSeq 396 def getVfWbBusyBundle = common.getVfWen.toSeq 397 def getIntRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readInt).toSeq 398 def getVfRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readVf).toSeq 399 400 def getIntRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 401 getIntRfReadBundle.zip(srcType).map { 402 case (rfRd: RfReadPortWithConfig, t: UInt) => 403 makeValid(issueValid && SrcType.isXp(t), rfRd) 404 } 405 } 406 407 def getVfRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 408 getVfRfReadBundle.zip(srcType).map { 409 case (rfRd: RfReadPortWithConfig, t: UInt) => 410 makeValid(issueValid && SrcType.isVfp(t), rfRd) 411 } 412 } 413 414 def getIntRfWriteValidBundle(issueValid: Bool) = { 415 416 } 417 } 418 419 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 420 val issueQueueParams = this.params 421 val og0resp = Valid(new EntryDeqRespBundle) 422 val og1resp = Valid(new EntryDeqRespBundle) 423 } 424 425 class fuBusyRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 426 val respType = RSFeedbackType() // update credit if needs replay 427 val rfWen = Bool() // TODO: use params to identify IntWB/VfWB 428 val fuType = FuType() 429 } 430 431 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 432 private val intCertainLat = params.intLatencyCertain 433 private val vfCertainLat = params.vfLatencyCertain 434 private val intLat = params.intLatencyValMax 435 private val vfLat = params.vfLatencyValMax 436 437 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 438 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 439 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 440 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 441 } 442 443 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 444 private val intCertainLat = params.intLatencyCertain 445 private val vfCertainLat = params.vfLatencyCertain 446 private val intLat = params.intLatencyValMax 447 private val vfLat = params.vfLatencyValMax 448 449 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 450 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 451 } 452 453 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 454 private val intCertainLat = params.intLatencyCertain 455 private val vfCertainLat = params.vfLatencyCertain 456 457 val intConflict = OptionWrapper(intCertainLat, Bool()) 458 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 459 } 460 461 // DataPath --[ExuInput]--> Exu 462 class ExuInput(val params: ExeUnitParams, copyPdest:Boolean = false, copyNum:Int = 0)(implicit p: Parameters) extends XSBundle { 463 val fuType = FuType() 464 val fuOpType = FuOpType() 465 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 466 val imm = UInt(32.W) 467 val robIdx = new RobPtr 468 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 469 val isFirstIssue = Bool() // Only used by store yet 470 val pdest = UInt(params.wbPregIdxWidth.W) 471 val pdestCopy = if (copyPdest) Some(Vec(copyNum, UInt(this.pdest.getWidth.W)))else None 472 val rfWen = if (params.writeIntRf) Some(Bool()) else None 473 val fpWen = if (params.writeFpRf) Some(Bool()) else None 474 val vecWen = if (params.writeVecRf) Some(Bool()) else None 475 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 476 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 477 val flushPipe = if (params.flushPipe) Some(Bool()) else None 478 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 479 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 480 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 481 Some(new FtqPtr) else None 482 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 483 Some(UInt(log2Up(PredictWidth).W)) else None 484 val predictInfo = if (params.needPdInfo) Some(new Bundle { 485 val target = UInt(VAddrData().dataWidth.W) 486 val taken = Bool() 487 }) else None 488 val loadWaitBit = OptionWrapper(params.hasLoadExu, Bool()) 489 val waitForRobIdx = OptionWrapper(params.hasLoadExu, new RobPtr) // store set predicted previous store robIdx 490 val storeSetHit = OptionWrapper(params.hasLoadExu, Bool()) // inst has been allocated an store set 491 val loadWaitStrict = OptionWrapper(params.hasLoadExu, Bool()) // load inst will not be executed until ALL former store addr calcuated 492 val ssid = OptionWrapper(params.hasLoadExu, UInt(SSIDWidth.W)) 493 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 494 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 495 val dataSources = Vec(params.numRegSrc, DataSource()) 496 val l1ExuOH = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuOH())) 497 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 498 val loadDependency = OptionWrapper(params.isIQWakeUpSink, Vec(LoadPipelineWidth, UInt(3.W))) 499 val deqLdExuIdx = OptionWrapper(params.hasLoadFu || params.hasHyldaFu, UInt(log2Ceil(LoadPipelineWidth).W)) 500 501 val perfDebugInfo = new PerfDebugInfo() 502 503 def exuIdx = this.params.exuIdx 504 505 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = { 506 if (params.isIQWakeUpSink) { 507 require( 508 og0CancelOH.getWidth == l1ExuOH.get.head.getWidth, 509 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}" 510 ) 511 val l1Cancel: Bool = l1ExuOH.get.zip(srcTimer.get).map { 512 case(exuOH: UInt, srcTimer: UInt) => 513 (exuOH & og0CancelOH).orR && srcTimer === 1.U 514 }.reduce(_ | _) 515 l1Cancel 516 } else { 517 false.B 518 } 519 } 520 521 def getVfWen = { 522 if (params.writeFpRf) this.fpWen 523 else if(params.writeVecRf) this.vecWen 524 else None 525 } 526 527 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 528 // src is assigned to rfReadData 529 this.fuType := source.common.fuType 530 this.fuOpType := source.common.fuOpType 531 this.imm := source.common.imm 532 this.robIdx := source.common.robIdx 533 this.pdest := source.common.pdest 534 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 535 this.iqIdx := source.common.iqIdx // Only used by mem feedback 536 this.dataSources := source.common.dataSources 537 this.l1ExuOH .foreach(_ := source.common.l1ExuOH.get) 538 this.rfWen .foreach(_ := source.common.rfWen.get) 539 this.fpWen .foreach(_ := source.common.fpWen.get) 540 this.vecWen .foreach(_ := source.common.vecWen.get) 541 this.fpu .foreach(_ := source.common.fpu.get) 542 this.vpu .foreach(_ := source.common.vpu.get) 543 this.flushPipe .foreach(_ := source.common.flushPipe.get) 544 this.pc .foreach(_ := source.common.pc.get) 545 this.preDecode .foreach(_ := source.common.preDecode.get) 546 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 547 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 548 this.predictInfo .foreach(_ := source.common.predictInfo.get) 549 this.loadWaitBit .foreach(_ := source.common.loadWaitBit.get) 550 this.waitForRobIdx .foreach(_ := source.common.waitForRobIdx.get) 551 this.storeSetHit .foreach(_ := source.common.storeSetHit.get) 552 this.loadWaitStrict.foreach(_ := source.common.loadWaitStrict.get) 553 this.ssid .foreach(_ := source.common.ssid.get) 554 this.lqIdx .foreach(_ := source.common.lqIdx.get) 555 this.sqIdx .foreach(_ := source.common.sqIdx.get) 556 this.srcTimer .foreach(_ := source.common.srcTimer.get) 557 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 558 this.deqLdExuIdx .foreach(_ := source.common.deqLdExuIdx.get) 559 } 560 } 561 562 // ExuInput --[FuncUnit]--> ExuOutput 563 class ExuOutput( 564 val params: ExeUnitParams, 565 )(implicit 566 val p: Parameters 567 ) extends Bundle with BundleSource with HasXSParameter { 568 val data = UInt(params.dataBitsMax.W) 569 val pdest = UInt(params.wbPregIdxWidth.W) 570 val robIdx = new RobPtr 571 val intWen = if (params.writeIntRf) Some(Bool()) else None 572 val fpWen = if (params.writeFpRf) Some(Bool()) else None 573 val vecWen = if (params.writeVecRf) Some(Bool()) else None 574 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 575 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 576 val wflags = if (params.writeFflags) Some(Bool()) else None 577 val vxsat = if (params.writeVxsat) Some(Bool()) else None 578 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 579 val flushPipe = if (params.flushPipe) Some(Bool()) else None 580 val replay = if (params.replayInst) Some(Bool()) else None 581 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 582 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 583 Some(new SqPtr()) else None 584 val trigger = if (params.trigger) Some(new TriggerCf) else None 585 // uop info 586 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 587 // vldu used only 588 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 589 val vpu = new VPUCtrlSignals 590 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 591 val vdIdx = UInt(3.W) 592 val vdIdxInField = UInt(3.W) 593 val isIndexed = Bool() 594 }) 595 val debug = new DebugBundle 596 val debugInfo = new PerfDebugInfo 597 } 598 599 // ExuOutput + DynInst --> WriteBackBundle 600 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 601 val rfWen = Bool() 602 val fpWen = Bool() 603 val vecWen = Bool() 604 val pdest = UInt(params.pregIdxWidth(backendParams).W) 605 val data = UInt(params.dataWidth.W) 606 val robIdx = new RobPtr()(p) 607 val flushPipe = Bool() 608 val replayInst = Bool() 609 val redirect = ValidIO(new Redirect) 610 val fflags = UInt(5.W) 611 val vxsat = Bool() 612 val exceptionVec = ExceptionVec() 613 val debug = new DebugBundle 614 val debugInfo = new PerfDebugInfo 615 616 this.wakeupSource = s"WB(${params.toString})" 617 618 def fromExuOutput(source: ExuOutput) = { 619 this.rfWen := source.intWen.getOrElse(false.B) 620 this.fpWen := source.fpWen.getOrElse(false.B) 621 this.vecWen := source.vecWen.getOrElse(false.B) 622 this.pdest := source.pdest 623 this.data := source.data 624 this.robIdx := source.robIdx 625 this.flushPipe := source.flushPipe.getOrElse(false.B) 626 this.replayInst := source.replay.getOrElse(false.B) 627 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 628 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 629 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 630 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 631 this.debug := source.debug 632 this.debugInfo := source.debugInfo 633 } 634 635 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 636 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 637 rfWrite.wen := this.rfWen && fire 638 rfWrite.addr := this.pdest 639 rfWrite.data := this.data 640 rfWrite.intWen := this.rfWen 641 rfWrite.fpWen := false.B 642 rfWrite.vecWen := false.B 643 rfWrite 644 } 645 646 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 647 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 648 rfWrite.wen := (this.fpWen || this.vecWen) && fire 649 rfWrite.addr := this.pdest 650 rfWrite.data := this.data 651 rfWrite.intWen := false.B 652 rfWrite.fpWen := this.fpWen 653 rfWrite.vecWen := this.vecWen 654 rfWrite 655 } 656 } 657 658 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 659 // / 660 // [IssueQueue]--> ExuInput -- 661 class ExuBypassBundle( 662 val params: ExeUnitParams, 663 )(implicit 664 val p: Parameters 665 ) extends Bundle { 666 val data = UInt(params.dataBitsMax.W) 667 val pdest = UInt(params.wbPregIdxWidth.W) 668 } 669 670 class ExceptionInfo(implicit p: Parameters) extends Bundle { 671 val pc = UInt(VAddrData().dataWidth.W) 672 val instr = UInt(32.W) 673 val commitType = CommitType() 674 val exceptionVec = ExceptionVec() 675 val singleStep = Bool() 676 val crossPageIPFFix = Bool() 677 val isInterrupt = Bool() 678 val vls = Bool() 679 val trigger = new TriggerCf 680 } 681 682 object UopIdx { 683 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 684 } 685 686 object FuLatency { 687 def apply(): UInt = UInt(width.W) 688 689 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 690 } 691 692 object ExuOH { 693 def apply(exuNum: Int): UInt = UInt(exuNum.W) 694 695 def apply()(implicit p: Parameters): UInt = UInt(width.W) 696 697 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 698 } 699 700 object ExuVec { 701 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 702 703 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 704 705 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 706 } 707 708 class CancelSignal(implicit p: Parameters) extends XSBundle { 709 val rfWen = Bool() 710 val fpWen = Bool() 711 val vecWen = Bool() 712 val pdest = UInt(PhyRegIdxWidth.W) 713 714 def needCancel(srcType: UInt, psrc: UInt, valid: Bool): Bool = { 715 val pdestMatch = pdest === psrc 716 pdestMatch && ( 717 SrcType.isFp(srcType) && !this.rfWen || 718 SrcType.isXp(srcType) && this.rfWen || 719 SrcType.isVp(srcType) && !this.rfWen 720 ) && valid 721 } 722 } 723 724 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 725 val uop = new DynInst 726 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 727 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 728 val isFirstIssue = Bool() 729 val deqPortIdx = UInt(log2Ceil(LoadPipelineWidth).W) 730 731 def src_rs1 = src(0) 732 def src_stride = src(1) 733 def src_vs3 = src(2) 734 def src_mask = if (isVector) src(3) else 0.U 735 def src_vl = if (isVector) src(4) else 0.U 736 } 737 738 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 739 val uop = new DynInst 740 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 741 val mask = if (isVector) Some(UInt(VLEN.W)) else None 742 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 743 val vdIdxInField = if (isVector) Some(UInt(3.W)) else None 744 val debug = new DebugBundle 745 746 def isVls = FuType.isVls(uop.fuType) 747 } 748 749 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 750 val uop = new DynInst 751 val flag = UInt(1.W) 752 } 753 754 object LoadShouldCancel { 755 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 756 val ld1Cancel = loadDependency.map(deps => 757 deps.zipWithIndex.map { case (dep, ldPortIdx) => 758 ldCancel.map(_.ld1Cancel).map(cancel => cancel.fire && dep(1) && cancel.bits === ldPortIdx.U).reduce(_ || _) 759 }.reduce(_ || _) 760 ) 761 val ld2Cancel = loadDependency.map(deps => 762 deps.zipWithIndex.map { case (dep, ldPortIdx) => 763 ldCancel.map(_.ld2Cancel).map(cancel => cancel.fire && dep(2) && cancel.bits === ldPortIdx.U).reduce(_ || _) 764 }.reduce(_ || _) 765 ) 766 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 767 } 768 } 769} 770