1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, IssueQueueJumpBundle, SchedulerType, EntryDeqRespBundle} 19import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 20import xiangshan.backend.rob.RobPtr 21import xiangshan.frontend._ 22import xiangshan.mem.{LqPtr, SqPtr} 23 24object Bundles { 25 /** 26 * Connect Same Name Port like bundleSource := bundleSinkBudle. 27 * 28 * There is no limit to the number of ports on both sides. 29 * 30 * Don't forget to connect the remaining ports! 31 */ 32 def connectSamePort (bundleSource: Bundle, bundleSink: Bundle):Unit = { 33 bundleSource.elements.foreach { case (name, data) => 34 if (bundleSink.elements.contains(name)) 35 data := bundleSink.elements(name) 36 } 37 } 38 // frontend -> backend 39 class StaticInst(implicit p: Parameters) extends XSBundle { 40 val instr = UInt(32.W) 41 val pc = UInt(VAddrBits.W) 42 val foldpc = UInt(MemPredPCWidth.W) 43 val exceptionVec = ExceptionVec() 44 val trigger = new TriggerCf 45 val preDecodeInfo = new PreDecodeInfo 46 val pred_taken = Bool() 47 val crossPageIPFFix = Bool() 48 val ftqPtr = new FtqPtr 49 val ftqOffset = UInt(log2Up(PredictWidth).W) 50 51 def connectCtrlFlow(source: CtrlFlow): Unit = { 52 this.instr := source.instr 53 this.pc := source.pc 54 this.foldpc := source.foldpc 55 this.exceptionVec := source.exceptionVec 56 this.trigger := source.trigger 57 this.preDecodeInfo := source.pd 58 this.pred_taken := source.pred_taken 59 this.crossPageIPFFix := source.crossPageIPFFix 60 this.ftqPtr := source.ftqPtr 61 this.ftqOffset := source.ftqOffset 62 } 63 } 64 65 // StaticInst --[Decode]--> DecodedInst 66 class DecodedInst(implicit p: Parameters) extends XSBundle { 67 def numSrc = backendParams.numSrc 68 // passed from StaticInst 69 val instr = UInt(32.W) 70 val pc = UInt(VAddrBits.W) 71 val foldpc = UInt(MemPredPCWidth.W) 72 val exceptionVec = ExceptionVec() 73 val trigger = new TriggerCf 74 val preDecodeInfo = new PreDecodeInfo 75 val pred_taken = Bool() 76 val crossPageIPFFix = Bool() 77 val ftqPtr = new FtqPtr 78 val ftqOffset = UInt(log2Up(PredictWidth).W) 79 // decoded 80 val srcType = Vec(numSrc, SrcType()) 81 val lsrc = Vec(numSrc, UInt(6.W)) 82 val ldest = UInt(6.W) 83 val fuType = FuType() 84 val fuOpType = FuOpType() 85 val rfWen = Bool() 86 val fpWen = Bool() 87 val vecWen = Bool() 88 val isXSTrap = Bool() 89 val waitForward = Bool() // no speculate execution 90 val blockBackward = Bool() 91 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 92 val canRobCompress = Bool() 93 val selImm = SelImm() 94 val imm = UInt(ImmUnion.maxLen.W) 95 val fpu = new FPUCtrlSignals 96 val vpu = new VPUCtrlSignals 97 val vlsInstr = Bool() 98 val wfflags = Bool() 99 val isMove = Bool() 100 val uopIdx = UopIdx() 101 val uopSplitType = UopSplitType() 102 val isVset = Bool() 103 val firstUop = Bool() 104 val lastUop = Bool() 105 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 106 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 107 val commitType = CommitType() // Todo: remove it 108 109 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 110 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 111 112 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 113 val decoder: Seq[UInt] = ListLookup( 114 inst, XDecode.decodeDefault.map(bitPatToUInt), 115 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 116 ) 117 allSignals zip decoder foreach { case (s, d) => s := d } 118 this 119 } 120 121 def isSoftPrefetch: Bool = { 122 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 123 } 124 125 def connectStaticInst(source: StaticInst): Unit = { 126 for ((name, data) <- this.elements) { 127 if (source.elements.contains(name)) { 128 data := source.elements(name) 129 } 130 } 131 } 132 } 133 134 // DecodedInst --[Rename]--> DynInst 135 class DynInst(implicit p: Parameters) extends XSBundle { 136 def numSrc = backendParams.numSrc 137 // passed from StaticInst 138 val instr = UInt(32.W) 139 val pc = UInt(VAddrBits.W) 140 val foldpc = UInt(MemPredPCWidth.W) 141 val exceptionVec = ExceptionVec() 142 val trigger = new TriggerCf 143 val preDecodeInfo = new PreDecodeInfo 144 val pred_taken = Bool() 145 val crossPageIPFFix = Bool() 146 val ftqPtr = new FtqPtr 147 val ftqOffset = UInt(log2Up(PredictWidth).W) 148 // passed from DecodedInst 149 val srcType = Vec(numSrc, SrcType()) 150 val lsrc = Vec(numSrc, UInt(6.W)) 151 val ldest = UInt(6.W) 152 val fuType = FuType() 153 val fuOpType = FuOpType() 154 val rfWen = Bool() 155 val fpWen = Bool() 156 val vecWen = Bool() 157 val isXSTrap = Bool() 158 val waitForward = Bool() // no speculate execution 159 val blockBackward = Bool() 160 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 161 val canRobCompress = Bool() 162 val selImm = SelImm() 163 val imm = UInt(32.W) 164 val fpu = new FPUCtrlSignals 165 val vpu = new VPUCtrlSignals 166 val vlsInstr = Bool() 167 val wfflags = Bool() 168 val isMove = Bool() 169 val uopIdx = UopIdx() 170 val isVset = Bool() 171 val firstUop = Bool() 172 val lastUop = Bool() 173 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 174 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 175 val commitType = CommitType() 176 // rename 177 val srcState = Vec(numSrc, SrcState()) 178 val srcLoadDependency = Vec(numSrc, Vec(LoadPipelineWidth, UInt(3.W))) 179 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 180 val pdest = UInt(PhyRegIdxWidth.W) 181 val robIdx = new RobPtr 182 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 183 val dirtyFs = Bool() 184 185 val eliminatedMove = Bool() 186 // Take snapshot at this CFI inst 187 val snapshot = Bool() 188 val debugInfo = new PerfDebugInfo 189 val storeSetHit = Bool() // inst has been allocated an store set 190 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 191 // Load wait is needed 192 // load inst will not be executed until former store (predicted by mdp) addr calcuated 193 val loadWaitBit = Bool() 194 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 195 // load inst will not be executed until ALL former store addr calcuated 196 val loadWaitStrict = Bool() 197 val ssid = UInt(SSIDWidth.W) 198 // Todo 199 val lqIdx = new LqPtr 200 val sqIdx = new SqPtr 201 // debug module 202 val singleStep = Bool() 203 // schedule 204 val replayInst = Bool() 205 206 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 207 def isLUI32: Bool = this.selImm === SelImm.IMM_LUI32 208 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 209 210 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 211 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 212 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 213 214 def srcIsReady: Vec[Bool] = { 215 VecInit(this.srcType.zip(this.srcState).map { 216 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 217 }) 218 } 219 220 def clearExceptions( 221 exceptionBits: Seq[Int] = Seq(), 222 flushPipe : Boolean = false, 223 replayInst : Boolean = false 224 ): DynInst = { 225 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 226 if (!flushPipe) { this.flushPipe := false.B } 227 if (!replayInst) { this.replayInst := false.B } 228 this 229 } 230 231 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen 232 } 233 234 trait BundleSource { 235 var wakeupSource = "undefined" 236 var idx = 0 237 } 238 239 /** 240 * 241 * @param pregIdxWidth index width of preg 242 * @param exuIndices exu indices of wakeup bundle 243 */ 244 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int]) extends Bundle { 245 val rfWen = Bool() 246 val fpWen = Bool() 247 val vecWen = Bool() 248 val pdest = UInt(pregIdxWidth.W) 249 250 /** 251 * @param successor Seq[(psrc, srcType)] 252 * @return Seq[if wakeup psrc] 253 */ 254 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 255 successor.map { case (thatPsrc, srcType) => 256 val pdestMatch = pdest === thatPsrc 257 pdestMatch && ( 258 SrcType.isFp(srcType) && this.fpWen || 259 SrcType.isXp(srcType) && this.rfWen || 260 SrcType.isVp(srcType) && this.vecWen 261 ) && valid 262 } 263 } 264 def wakeUpFromIQ(successor: Seq[(UInt, UInt)]): Seq[Bool] = { 265 successor.map { case (thatPsrc, srcType) => 266 val pdestMatch = pdest === thatPsrc 267 pdestMatch && ( 268 SrcType.isFp(srcType) && this.fpWen || 269 SrcType.isXp(srcType) && this.rfWen || 270 SrcType.isVp(srcType) && this.vecWen 271 ) 272 } 273 } 274 275 def hasOnlyOneSource: Boolean = exuIndices.size == 1 276 277 def hasMultiSources: Boolean = exuIndices.size > 1 278 279 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 280 281 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 282 283 def exuIdx: Int = { 284 require(hasOnlyOneSource) 285 this.exuIndices.head 286 } 287 } 288 289 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 290 291 } 292 293class IssueQueueIQWakeUpBundle( 294 exuIdx: Int, 295 backendParams: BackendParams, 296 copyWakeupOut: Boolean = false, 297 copyNum: Int = 0 298) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 299 val loadDependency = Vec(backendParams.LduCnt + backendParams.HyuCnt, UInt(3.W)) 300 val is0Lat = Bool() 301 val params = backendParams.allExuParams.filter(_.exuIdx == exuIdx).head 302 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 303 val rfWenCopy = OptionWrapper(copyWakeupOut && params.writeIntRf, Vec(copyNum, Bool())) 304 val fpWenCopy = OptionWrapper(copyWakeupOut && params.writeFpRf, Vec(copyNum, Bool())) 305 val vecWenCopy = OptionWrapper(copyWakeupOut && params.writeVecRf, Vec(copyNum, Bool())) 306 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum,Vec(backendParams.LdExuCnt, UInt(3.W)))) 307 def fromExuInput(exuInput: ExuInput, l2ExuVecs: Vec[UInt]): Unit = { 308 this.rfWen := exuInput.rfWen.getOrElse(false.B) 309 this.fpWen := exuInput.fpWen.getOrElse(false.B) 310 this.vecWen := exuInput.vecWen.getOrElse(false.B) 311 this.pdest := exuInput.pdest 312 } 313 314 def fromExuInput(exuInput: ExuInput): Unit = { 315 this.rfWen := exuInput.rfWen.getOrElse(false.B) 316 this.fpWen := exuInput.fpWen.getOrElse(false.B) 317 this.vecWen := exuInput.vecWen.getOrElse(false.B) 318 this.pdest := exuInput.pdest 319 } 320 } 321 322 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 323 // vtype 324 val vill = Bool() 325 val vma = Bool() // 1: agnostic, 0: undisturbed 326 val vta = Bool() // 1: agnostic, 0: undisturbed 327 val vsew = VSew() 328 val vlmul = VLmul() // 1/8~8 --> -3~3 329 330 val vm = Bool() // 0: need v0.t 331 val vstart = Vl() 332 333 // float rounding mode 334 val frm = Frm() 335 // scalar float instr and vector float reduction 336 val fpu = Fpu() 337 // vector fix int rounding mode 338 val vxrm = Vxrm() 339 // vector uop index, exclude other non-vector uop 340 val vuopIdx = UopIdx() 341 val lastUop = Bool() 342 // maybe used if data dependancy 343 val vmask = UInt(MaskSrcData().dataWidth.W) 344 val vl = Vl() 345 346 // vector load/store 347 val nf = Nf() 348 val veew = VEew() 349 350 val isReverse = Bool() // vrsub, vrdiv 351 val isExt = Bool() 352 val isNarrow = Bool() 353 val isDstMask = Bool() // vvm, vvvm, mmm 354 val isOpMask = Bool() // vmand, vmnand 355 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 356 357 def vtype: VType = { 358 val res = Wire(VType()) 359 res.illegal := this.vill 360 res.vma := this.vma 361 res.vta := this.vta 362 res.vsew := this.vsew 363 res.vlmul := this.vlmul 364 res 365 } 366 367 def vconfig: VConfig = { 368 val res = Wire(VConfig()) 369 res.vtype := this.vtype 370 res.vl := this.vl 371 res 372 } 373 374 def connectVType(source: VType): Unit = { 375 this.vill := source.illegal 376 this.vma := source.vma 377 this.vta := source.vta 378 this.vsew := source.vsew 379 this.vlmul := source.vlmul 380 } 381 } 382 383 // DynInst --[IssueQueue]--> DataPath 384 class IssueQueueIssueBundle( 385 iqParams: IssueBlockParams, 386 val exuParams: ExeUnitParams, 387 )(implicit 388 p: Parameters 389 ) extends Bundle { 390 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 391 // check which set both have fp and vec and remove fp 392 private val rfReadDataCfgSetFilterFp = rfReadDataCfgSet.map((set: Set[DataConfig]) => 393 if (set.contains(FpData()) && set.contains(VecData())) set.filter(_ != FpData()) 394 else set 395 ) 396 397 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 398 rfReadDataCfgSetFilterFp.map((set: Set[DataConfig]) => 399 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 400 ) 401 )) 402 403 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 404 val immType = SelImm() // used to select imm extractor 405 val common = new ExuInput(exuParams) 406 val addrOH = UInt(iqParams.numEntries.W) 407 408 def exuIdx = exuParams.exuIdx 409 def getSource: SchedulerType = exuParams.getWBSource 410 def getIntWbBusyBundle = common.rfWen.toSeq 411 def getVfWbBusyBundle = common.getVfWen.toSeq 412 def getIntRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readInt).toSeq 413 def getVfRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readVf).toSeq 414 415 def getIntRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 416 getIntRfReadBundle.zip(srcType).map { 417 case (rfRd: RfReadPortWithConfig, t: UInt) => 418 makeValid(issueValid && SrcType.isXp(t), rfRd) 419 } 420 } 421 422 def getVfRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 423 getVfRfReadBundle.zip(srcType).map { 424 case (rfRd: RfReadPortWithConfig, t: UInt) => 425 makeValid(issueValid && SrcType.isVfp(t), rfRd) 426 } 427 } 428 429 def getIntRfWriteValidBundle(issueValid: Bool) = { 430 431 } 432 } 433 434 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 435 val issueQueueParams = this.params 436 val og0resp = Valid(new EntryDeqRespBundle) 437 val og1resp = Valid(new EntryDeqRespBundle) 438 } 439 440 class fuBusyRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 441 val respType = RSFeedbackType() // update credit if needs replay 442 val rfWen = Bool() // TODO: use params to identify IntWB/VfWB 443 val fuType = FuType() 444 } 445 446 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 447 private val intCertainLat = params.intLatencyCertain 448 private val vfCertainLat = params.vfLatencyCertain 449 private val intLat = params.intLatencyValMax 450 private val vfLat = params.vfLatencyValMax 451 452 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 453 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 454 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 455 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 456 } 457 458 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 459 private val intCertainLat = params.intLatencyCertain 460 private val vfCertainLat = params.vfLatencyCertain 461 private val intLat = params.intLatencyValMax 462 private val vfLat = params.vfLatencyValMax 463 464 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 465 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 466 } 467 468 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 469 private val intCertainLat = params.intLatencyCertain 470 private val vfCertainLat = params.vfLatencyCertain 471 472 val intConflict = OptionWrapper(intCertainLat, Bool()) 473 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 474 } 475 476 // DataPath --[ExuInput]--> Exu 477 class ExuInput(val params: ExeUnitParams, copyWakeupOut:Boolean = false, copyNum:Int = 0)(implicit p: Parameters) extends XSBundle { 478 val fuType = FuType() 479 val fuOpType = FuOpType() 480 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 481 val imm = UInt(32.W) 482 val robIdx = new RobPtr 483 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 484 val isFirstIssue = Bool() // Only used by store yet 485 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 486 val rfWenCopy = OptionWrapper(copyWakeupOut && params.writeIntRf, Vec(copyNum, Bool())) 487 val fpWenCopy = OptionWrapper(copyWakeupOut && params.writeFpRf, Vec(copyNum, Bool())) 488 val vecWenCopy = OptionWrapper(copyWakeupOut && params.writeVecRf, Vec(copyNum, Bool())) 489 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum,Vec(LoadPipelineWidth, UInt(3.W)))) 490 val pdest = UInt(params.wbPregIdxWidth.W) 491 val rfWen = if (params.writeIntRf) Some(Bool()) else None 492 val fpWen = if (params.writeFpRf) Some(Bool()) else None 493 val vecWen = if (params.writeVecRf) Some(Bool()) else None 494 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 495 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 496 val flushPipe = if (params.flushPipe) Some(Bool()) else None 497 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 498 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 499 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 500 Some(new FtqPtr) else None 501 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 502 Some(UInt(log2Up(PredictWidth).W)) else None 503 val predictInfo = if (params.needPdInfo) Some(new Bundle { 504 val target = UInt(VAddrData().dataWidth.W) 505 val taken = Bool() 506 }) else None 507 val loadWaitBit = OptionWrapper(params.hasLoadExu, Bool()) 508 val waitForRobIdx = OptionWrapper(params.hasLoadExu, new RobPtr) // store set predicted previous store robIdx 509 val storeSetHit = OptionWrapper(params.hasLoadExu, Bool()) // inst has been allocated an store set 510 val loadWaitStrict = OptionWrapper(params.hasLoadExu, Bool()) // load inst will not be executed until ALL former store addr calcuated 511 val ssid = OptionWrapper(params.hasLoadExu, UInt(SSIDWidth.W)) 512 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 513 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 514 val dataSources = Vec(params.numRegSrc, DataSource()) 515 val l1ExuOH = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuOH())) 516 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 517 val loadDependency = OptionWrapper(params.isIQWakeUpSink, Vec(LoadPipelineWidth, UInt(3.W))) 518 val deqLdExuIdx = OptionWrapper(params.hasLoadFu || params.hasHyldaFu, UInt(log2Ceil(LoadPipelineWidth).W)) 519 520 val perfDebugInfo = new PerfDebugInfo() 521 522 def exuIdx = this.params.exuIdx 523 524 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = { 525 if (params.isIQWakeUpSink) { 526 require( 527 og0CancelOH.getWidth == l1ExuOH.get.head.getWidth, 528 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}" 529 ) 530 val l1Cancel: Bool = l1ExuOH.get.zip(srcTimer.get).map { 531 case(exuOH: UInt, srcTimer: UInt) => 532 (exuOH & og0CancelOH).orR && srcTimer === 1.U 533 }.reduce(_ | _) 534 l1Cancel 535 } else { 536 false.B 537 } 538 } 539 540 def getVfWen = { 541 if (params.writeFpRf) this.fpWen 542 else if(params.writeVecRf) this.vecWen 543 else None 544 } 545 546 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 547 // src is assigned to rfReadData 548 this.fuType := source.common.fuType 549 this.fuOpType := source.common.fuOpType 550 this.imm := source.common.imm 551 this.robIdx := source.common.robIdx 552 this.pdest := source.common.pdest 553 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 554 this.iqIdx := source.common.iqIdx // Only used by mem feedback 555 this.dataSources := source.common.dataSources 556 this.l1ExuOH .foreach(_ := source.common.l1ExuOH.get) 557 this.rfWen .foreach(_ := source.common.rfWen.get) 558 this.fpWen .foreach(_ := source.common.fpWen.get) 559 this.vecWen .foreach(_ := source.common.vecWen.get) 560 this.fpu .foreach(_ := source.common.fpu.get) 561 this.vpu .foreach(_ := source.common.vpu.get) 562 this.flushPipe .foreach(_ := source.common.flushPipe.get) 563 this.pc .foreach(_ := source.common.pc.get) 564 this.preDecode .foreach(_ := source.common.preDecode.get) 565 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 566 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 567 this.predictInfo .foreach(_ := source.common.predictInfo.get) 568 this.loadWaitBit .foreach(_ := source.common.loadWaitBit.get) 569 this.waitForRobIdx .foreach(_ := source.common.waitForRobIdx.get) 570 this.storeSetHit .foreach(_ := source.common.storeSetHit.get) 571 this.loadWaitStrict.foreach(_ := source.common.loadWaitStrict.get) 572 this.ssid .foreach(_ := source.common.ssid.get) 573 this.lqIdx .foreach(_ := source.common.lqIdx.get) 574 this.sqIdx .foreach(_ := source.common.sqIdx.get) 575 this.srcTimer .foreach(_ := source.common.srcTimer.get) 576 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 577 this.deqLdExuIdx .foreach(_ := source.common.deqLdExuIdx.get) 578 } 579 } 580 581 // ExuInput --[FuncUnit]--> ExuOutput 582 class ExuOutput( 583 val params: ExeUnitParams, 584 )(implicit 585 val p: Parameters 586 ) extends Bundle with BundleSource with HasXSParameter { 587 val data = UInt(params.dataBitsMax.W) 588 val pdest = UInt(params.wbPregIdxWidth.W) 589 val robIdx = new RobPtr 590 val intWen = if (params.writeIntRf) Some(Bool()) else None 591 val fpWen = if (params.writeFpRf) Some(Bool()) else None 592 val vecWen = if (params.writeVecRf) Some(Bool()) else None 593 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 594 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 595 val wflags = if (params.writeFflags) Some(Bool()) else None 596 val vxsat = if (params.writeVxsat) Some(Bool()) else None 597 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 598 val flushPipe = if (params.flushPipe) Some(Bool()) else None 599 val replay = if (params.replayInst) Some(Bool()) else None 600 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 601 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 602 Some(new SqPtr()) else None 603 val trigger = if (params.trigger) Some(new TriggerCf) else None 604 // uop info 605 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 606 // vldu used only 607 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 608 val vpu = new VPUCtrlSignals 609 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 610 val vdIdx = UInt(3.W) 611 val vdIdxInField = UInt(3.W) 612 val isIndexed = Bool() 613 }) 614 val debug = new DebugBundle 615 val debugInfo = new PerfDebugInfo 616 } 617 618 // ExuOutput + DynInst --> WriteBackBundle 619 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 620 val rfWen = Bool() 621 val fpWen = Bool() 622 val vecWen = Bool() 623 val pdest = UInt(params.pregIdxWidth(backendParams).W) 624 val data = UInt(params.dataWidth.W) 625 val robIdx = new RobPtr()(p) 626 val flushPipe = Bool() 627 val replayInst = Bool() 628 val redirect = ValidIO(new Redirect) 629 val fflags = UInt(5.W) 630 val vxsat = Bool() 631 val exceptionVec = ExceptionVec() 632 val debug = new DebugBundle 633 val debugInfo = new PerfDebugInfo 634 635 this.wakeupSource = s"WB(${params.toString})" 636 637 def fromExuOutput(source: ExuOutput) = { 638 this.rfWen := source.intWen.getOrElse(false.B) 639 this.fpWen := source.fpWen.getOrElse(false.B) 640 this.vecWen := source.vecWen.getOrElse(false.B) 641 this.pdest := source.pdest 642 this.data := source.data 643 this.robIdx := source.robIdx 644 this.flushPipe := source.flushPipe.getOrElse(false.B) 645 this.replayInst := source.replay.getOrElse(false.B) 646 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 647 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 648 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 649 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 650 this.debug := source.debug 651 this.debugInfo := source.debugInfo 652 } 653 654 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 655 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 656 rfWrite.wen := this.rfWen && fire 657 rfWrite.addr := this.pdest 658 rfWrite.data := this.data 659 rfWrite.intWen := this.rfWen 660 rfWrite.fpWen := false.B 661 rfWrite.vecWen := false.B 662 rfWrite 663 } 664 665 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 666 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 667 rfWrite.wen := (this.fpWen || this.vecWen) && fire 668 rfWrite.addr := this.pdest 669 rfWrite.data := this.data 670 rfWrite.intWen := false.B 671 rfWrite.fpWen := this.fpWen 672 rfWrite.vecWen := this.vecWen 673 rfWrite 674 } 675 } 676 677 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 678 // / 679 // [IssueQueue]--> ExuInput -- 680 class ExuBypassBundle( 681 val params: ExeUnitParams, 682 )(implicit 683 val p: Parameters 684 ) extends Bundle { 685 val data = UInt(params.dataBitsMax.W) 686 val pdest = UInt(params.wbPregIdxWidth.W) 687 } 688 689 class ExceptionInfo(implicit p: Parameters) extends Bundle { 690 val pc = UInt(VAddrData().dataWidth.W) 691 val instr = UInt(32.W) 692 val commitType = CommitType() 693 val exceptionVec = ExceptionVec() 694 val singleStep = Bool() 695 val crossPageIPFFix = Bool() 696 val isInterrupt = Bool() 697 val vls = Bool() 698 val trigger = new TriggerCf 699 } 700 701 object UopIdx { 702 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 703 } 704 705 object FuLatency { 706 def apply(): UInt = UInt(width.W) 707 708 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 709 } 710 711 object ExuOH { 712 def apply(exuNum: Int): UInt = UInt(exuNum.W) 713 714 def apply()(implicit p: Parameters): UInt = UInt(width.W) 715 716 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 717 } 718 719 object ExuVec { 720 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 721 722 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 723 724 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 725 } 726 727 class CancelSignal(implicit p: Parameters) extends XSBundle { 728 val rfWen = Bool() 729 val fpWen = Bool() 730 val vecWen = Bool() 731 val pdest = UInt(PhyRegIdxWidth.W) 732 733 def needCancel(srcType: UInt, psrc: UInt, valid: Bool): Bool = { 734 val pdestMatch = pdest === psrc 735 pdestMatch && ( 736 SrcType.isFp(srcType) && !this.rfWen || 737 SrcType.isXp(srcType) && this.rfWen || 738 SrcType.isVp(srcType) && !this.rfWen 739 ) && valid 740 } 741 } 742 743 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 744 val uop = new DynInst 745 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 746 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 747 val isFirstIssue = Bool() 748 val deqPortIdx = UInt(log2Ceil(LoadPipelineWidth).W) 749 750 def src_rs1 = src(0) 751 def src_stride = src(1) 752 def src_vs3 = src(2) 753 def src_mask = if (isVector) src(3) else 0.U 754 def src_vl = if (isVector) src(4) else 0.U 755 } 756 757 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 758 val uop = new DynInst 759 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 760 val mask = if (isVector) Some(UInt(VLEN.W)) else None 761 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 762 val vdIdxInField = if (isVector) Some(UInt(3.W)) else None 763 val debug = new DebugBundle 764 765 def isVls = FuType.isVls(uop.fuType) 766 } 767 768 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 769 val uop = new DynInst 770 val flag = UInt(1.W) 771 } 772 773 object LoadShouldCancel { 774 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 775 val ld1Cancel = loadDependency.map(deps => 776 deps.zipWithIndex.map { case (dep, ldPortIdx) => 777 ldCancel.map(_.ld1Cancel).map(cancel => cancel.fire && dep(1) && cancel.bits === ldPortIdx.U).reduce(_ || _) 778 }.reduce(_ || _) 779 ) 780 val ld2Cancel = loadDependency.map(deps => 781 deps.zipWithIndex.map { case (dep, ldPortIdx) => 782 ldCancel.map(_.ld2Cancel).map(cancel => cancel.fire && dep(2) && cancel.bits === ldPortIdx.U).reduce(_ || _) 783 }.reduce(_ || _) 784 ) 785 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 786 } 787 } 788} 789