1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, IssueQueueJumpBundle, SchedulerType} 19import xiangshan.backend.issue.EntryBundles._ 20import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 21import xiangshan.backend.rob.RobPtr 22import xiangshan.frontend._ 23import xiangshan.mem.{LqPtr, SqPtr} 24 25object Bundles { 26 /** 27 * Connect Same Name Port like bundleSource := bundleSinkBudle. 28 * 29 * There is no limit to the number of ports on both sides. 30 * 31 * Don't forget to connect the remaining ports! 32 */ 33 def connectSamePort (bundleSource: Bundle, bundleSink: Bundle):Unit = { 34 bundleSource.elements.foreach { case (name, data) => 35 if (bundleSink.elements.contains(name)) 36 data := bundleSink.elements(name) 37 } 38 } 39 // frontend -> backend 40 class StaticInst(implicit p: Parameters) extends XSBundle { 41 val instr = UInt(32.W) 42 val pc = UInt(VAddrBits.W) 43 val foldpc = UInt(MemPredPCWidth.W) 44 val exceptionVec = ExceptionVec() 45 val trigger = new TriggerCf 46 val preDecodeInfo = new PreDecodeInfo 47 val pred_taken = Bool() 48 val crossPageIPFFix = Bool() 49 val ftqPtr = new FtqPtr 50 val ftqOffset = UInt(log2Up(PredictWidth).W) 51 52 def connectCtrlFlow(source: CtrlFlow): Unit = { 53 this.instr := source.instr 54 this.pc := source.pc 55 this.foldpc := source.foldpc 56 this.exceptionVec := source.exceptionVec 57 this.trigger := source.trigger 58 this.preDecodeInfo := source.pd 59 this.pred_taken := source.pred_taken 60 this.crossPageIPFFix := source.crossPageIPFFix 61 this.ftqPtr := source.ftqPtr 62 this.ftqOffset := source.ftqOffset 63 } 64 } 65 66 // StaticInst --[Decode]--> DecodedInst 67 class DecodedInst(implicit p: Parameters) extends XSBundle { 68 def numSrc = backendParams.numSrc 69 // passed from StaticInst 70 val instr = UInt(32.W) 71 val pc = UInt(VAddrBits.W) 72 val foldpc = UInt(MemPredPCWidth.W) 73 val exceptionVec = ExceptionVec() 74 val trigger = new TriggerCf 75 val preDecodeInfo = new PreDecodeInfo 76 val pred_taken = Bool() 77 val crossPageIPFFix = Bool() 78 val ftqPtr = new FtqPtr 79 val ftqOffset = UInt(log2Up(PredictWidth).W) 80 // decoded 81 val srcType = Vec(numSrc, SrcType()) 82 val lsrc = Vec(numSrc, UInt(6.W)) 83 val ldest = UInt(6.W) 84 val fuType = FuType() 85 val fuOpType = FuOpType() 86 val rfWen = Bool() 87 val fpWen = Bool() 88 val vecWen = Bool() 89 val isXSTrap = Bool() 90 val waitForward = Bool() // no speculate execution 91 val blockBackward = Bool() 92 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 93 val canRobCompress = Bool() 94 val selImm = SelImm() 95 val imm = UInt(ImmUnion.maxLen.W) 96 val fpu = new FPUCtrlSignals 97 val vpu = new VPUCtrlSignals 98 val vlsInstr = Bool() 99 val wfflags = Bool() 100 val isMove = Bool() 101 val uopIdx = UopIdx() 102 val uopSplitType = UopSplitType() 103 val isVset = Bool() 104 val firstUop = Bool() 105 val lastUop = Bool() 106 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 107 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 108 val commitType = CommitType() // Todo: remove it 109 110 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 111 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 112 113 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 114 val decoder: Seq[UInt] = ListLookup( 115 inst, XDecode.decodeDefault.map(bitPatToUInt), 116 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 117 ) 118 allSignals zip decoder foreach { case (s, d) => s := d } 119 this 120 } 121 122 def isSoftPrefetch: Bool = { 123 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 124 } 125 126 def connectStaticInst(source: StaticInst): Unit = { 127 for ((name, data) <- this.elements) { 128 if (source.elements.contains(name)) { 129 data := source.elements(name) 130 } 131 } 132 } 133 } 134 135 // DecodedInst --[Rename]--> DynInst 136 class DynInst(implicit p: Parameters) extends XSBundle { 137 def numSrc = backendParams.numSrc 138 // passed from StaticInst 139 val instr = UInt(32.W) 140 val pc = UInt(VAddrBits.W) 141 val foldpc = UInt(MemPredPCWidth.W) 142 val exceptionVec = ExceptionVec() 143 val trigger = new TriggerCf 144 val preDecodeInfo = new PreDecodeInfo 145 val pred_taken = Bool() 146 val crossPageIPFFix = Bool() 147 val ftqPtr = new FtqPtr 148 val ftqOffset = UInt(log2Up(PredictWidth).W) 149 // passed from DecodedInst 150 val srcType = Vec(numSrc, SrcType()) 151 val lsrc = Vec(numSrc, UInt(6.W)) 152 val ldest = UInt(6.W) 153 val fuType = FuType() 154 val fuOpType = FuOpType() 155 val rfWen = Bool() 156 val fpWen = Bool() 157 val vecWen = Bool() 158 val isXSTrap = Bool() 159 val waitForward = Bool() // no speculate execution 160 val blockBackward = Bool() 161 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 162 val canRobCompress = Bool() 163 val selImm = SelImm() 164 val imm = UInt(32.W) 165 val fpu = new FPUCtrlSignals 166 val vpu = new VPUCtrlSignals 167 val vlsInstr = Bool() 168 val wfflags = Bool() 169 val isMove = Bool() 170 val uopIdx = UopIdx() 171 val isVset = Bool() 172 val firstUop = Bool() 173 val lastUop = Bool() 174 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 175 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 176 val commitType = CommitType() 177 // rename 178 val srcState = Vec(numSrc, SrcState()) 179 val srcLoadDependency = Vec(numSrc, Vec(LoadPipelineWidth, UInt(3.W))) 180 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 181 val pdest = UInt(PhyRegIdxWidth.W) 182 val robIdx = new RobPtr 183 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 184 val dirtyFs = Bool() 185 186 val eliminatedMove = Bool() 187 // Take snapshot at this CFI inst 188 val snapshot = Bool() 189 val debugInfo = new PerfDebugInfo 190 val storeSetHit = Bool() // inst has been allocated an store set 191 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 192 // Load wait is needed 193 // load inst will not be executed until former store (predicted by mdp) addr calcuated 194 val loadWaitBit = Bool() 195 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 196 // load inst will not be executed until ALL former store addr calcuated 197 val loadWaitStrict = Bool() 198 val ssid = UInt(SSIDWidth.W) 199 // Todo 200 val lqIdx = new LqPtr 201 val sqIdx = new SqPtr 202 // debug module 203 val singleStep = Bool() 204 // schedule 205 val replayInst = Bool() 206 207 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 208 def isLUI32: Bool = this.selImm === SelImm.IMM_LUI32 209 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 210 211 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 212 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 213 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 214 215 def srcIsReady: Vec[Bool] = { 216 VecInit(this.srcType.zip(this.srcState).map { 217 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 218 }) 219 } 220 221 def clearExceptions( 222 exceptionBits: Seq[Int] = Seq(), 223 flushPipe : Boolean = false, 224 replayInst : Boolean = false 225 ): DynInst = { 226 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 227 if (!flushPipe) { this.flushPipe := false.B } 228 if (!replayInst) { this.replayInst := false.B } 229 this 230 } 231 232 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen 233 } 234 235 trait BundleSource { 236 var wakeupSource = "undefined" 237 var idx = 0 238 } 239 240 /** 241 * 242 * @param pregIdxWidth index width of preg 243 * @param exuIndices exu indices of wakeup bundle 244 */ 245 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int]) extends Bundle { 246 val rfWen = Bool() 247 val fpWen = Bool() 248 val vecWen = Bool() 249 val pdest = UInt(pregIdxWidth.W) 250 251 /** 252 * @param successor Seq[(psrc, srcType)] 253 * @return Seq[if wakeup psrc] 254 */ 255 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 256 successor.map { case (thatPsrc, srcType) => 257 val pdestMatch = pdest === thatPsrc 258 pdestMatch && ( 259 SrcType.isFp(srcType) && this.fpWen || 260 SrcType.isXp(srcType) && this.rfWen || 261 SrcType.isVp(srcType) && this.vecWen 262 ) && valid 263 } 264 } 265 def wakeUpFromIQ(successor: Seq[(UInt, UInt)]): Seq[Bool] = { 266 successor.map { case (thatPsrc, srcType) => 267 val pdestMatch = pdest === thatPsrc 268 pdestMatch && ( 269 SrcType.isFp(srcType) && this.fpWen || 270 SrcType.isXp(srcType) && this.rfWen || 271 SrcType.isVp(srcType) && this.vecWen 272 ) 273 } 274 } 275 276 def hasOnlyOneSource: Boolean = exuIndices.size == 1 277 278 def hasMultiSources: Boolean = exuIndices.size > 1 279 280 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 281 282 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 283 284 def exuIdx: Int = { 285 require(hasOnlyOneSource) 286 this.exuIndices.head 287 } 288 } 289 290 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 291 292 } 293 294class IssueQueueIQWakeUpBundle( 295 exuIdx: Int, 296 backendParams: BackendParams, 297 copyWakeupOut: Boolean = false, 298 copyNum: Int = 0 299) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 300 val loadDependency = Vec(backendParams.LduCnt + backendParams.HyuCnt, UInt(3.W)) 301 val is0Lat = Bool() 302 val params = backendParams.allExuParams.filter(_.exuIdx == exuIdx).head 303 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 304 val rfWenCopy = OptionWrapper(copyWakeupOut && params.writeIntRf, Vec(copyNum, Bool())) 305 val fpWenCopy = OptionWrapper(copyWakeupOut && params.writeFpRf, Vec(copyNum, Bool())) 306 val vecWenCopy = OptionWrapper(copyWakeupOut && params.writeVecRf, Vec(copyNum, Bool())) 307 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum,Vec(backendParams.LdExuCnt, UInt(3.W)))) 308 def fromExuInput(exuInput: ExuInput, l2ExuVecs: Vec[UInt]): Unit = { 309 this.rfWen := exuInput.rfWen.getOrElse(false.B) 310 this.fpWen := exuInput.fpWen.getOrElse(false.B) 311 this.vecWen := exuInput.vecWen.getOrElse(false.B) 312 this.pdest := exuInput.pdest 313 } 314 315 def fromExuInput(exuInput: ExuInput): Unit = { 316 this.rfWen := exuInput.rfWen.getOrElse(false.B) 317 this.fpWen := exuInput.fpWen.getOrElse(false.B) 318 this.vecWen := exuInput.vecWen.getOrElse(false.B) 319 this.pdest := exuInput.pdest 320 } 321 } 322 323 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 324 // vtype 325 val vill = Bool() 326 val vma = Bool() // 1: agnostic, 0: undisturbed 327 val vta = Bool() // 1: agnostic, 0: undisturbed 328 val vsew = VSew() 329 val vlmul = VLmul() // 1/8~8 --> -3~3 330 331 val vm = Bool() // 0: need v0.t 332 val vstart = Vl() 333 334 // float rounding mode 335 val frm = Frm() 336 // scalar float instr and vector float reduction 337 val fpu = Fpu() 338 // vector fix int rounding mode 339 val vxrm = Vxrm() 340 // vector uop index, exclude other non-vector uop 341 val vuopIdx = UopIdx() 342 val lastUop = Bool() 343 // maybe used if data dependancy 344 val vmask = UInt(MaskSrcData().dataWidth.W) 345 val vl = Vl() 346 347 // vector load/store 348 val nf = Nf() 349 val veew = VEew() 350 351 val isReverse = Bool() // vrsub, vrdiv 352 val isExt = Bool() 353 val isNarrow = Bool() 354 val isDstMask = Bool() // vvm, vvvm, mmm 355 val isOpMask = Bool() // vmand, vmnand 356 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 357 358 def vtype: VType = { 359 val res = Wire(VType()) 360 res.illegal := this.vill 361 res.vma := this.vma 362 res.vta := this.vta 363 res.vsew := this.vsew 364 res.vlmul := this.vlmul 365 res 366 } 367 368 def vconfig: VConfig = { 369 val res = Wire(VConfig()) 370 res.vtype := this.vtype 371 res.vl := this.vl 372 res 373 } 374 375 def connectVType(source: VType): Unit = { 376 this.vill := source.illegal 377 this.vma := source.vma 378 this.vta := source.vta 379 this.vsew := source.vsew 380 this.vlmul := source.vlmul 381 } 382 } 383 384 // DynInst --[IssueQueue]--> DataPath 385 class IssueQueueIssueBundle( 386 iqParams: IssueBlockParams, 387 val exuParams: ExeUnitParams, 388 )(implicit 389 p: Parameters 390 ) extends Bundle { 391 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 392 // check which set both have fp and vec and remove fp 393 private val rfReadDataCfgSetFilterFp = rfReadDataCfgSet.map((set: Set[DataConfig]) => 394 if (set.contains(FpData()) && set.contains(VecData())) set.filter(_ != FpData()) 395 else set 396 ) 397 398 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 399 rfReadDataCfgSetFilterFp.map((set: Set[DataConfig]) => 400 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 401 ) 402 )) 403 404 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 405 val immType = SelImm() // used to select imm extractor 406 val common = new ExuInput(exuParams) 407 val addrOH = UInt(iqParams.numEntries.W) 408 409 def exuIdx = exuParams.exuIdx 410 def getSource: SchedulerType = exuParams.getWBSource 411 def getIntWbBusyBundle = common.rfWen.toSeq 412 def getVfWbBusyBundle = common.getVfWen.toSeq 413 414 def getIntRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 415 rf.zip(srcType).map { 416 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 417 makeValid(issueValid, rfRd.head) 418 }.toSeq 419 } 420 421 def getVfRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 422 rf.zip(srcType).map { 423 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 424 makeValid(issueValid, rfRd.head) 425 }.toSeq 426 } 427 428 def getIntRfWriteValidBundle(issueValid: Bool) = { 429 430 } 431 } 432 433 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 434 val issueQueueParams = this.params 435 val og0resp = Valid(new EntryDeqRespBundle) 436 val og1resp = Valid(new EntryDeqRespBundle) 437 } 438 439 class fuBusyRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 440 val respType = RSFeedbackType() // update credit if needs replay 441 val rfWen = Bool() // TODO: use params to identify IntWB/VfWB 442 val fuType = FuType() 443 } 444 445 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 446 private val intCertainLat = params.intLatencyCertain 447 private val vfCertainLat = params.vfLatencyCertain 448 private val intLat = params.intLatencyValMax 449 private val vfLat = params.vfLatencyValMax 450 451 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 452 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 453 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 454 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 455 } 456 457 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 458 private val intCertainLat = params.intLatencyCertain 459 private val vfCertainLat = params.vfLatencyCertain 460 private val intLat = params.intLatencyValMax 461 private val vfLat = params.vfLatencyValMax 462 463 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 464 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 465 } 466 467 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 468 private val intCertainLat = params.intLatencyCertain 469 private val vfCertainLat = params.vfLatencyCertain 470 471 val intConflict = OptionWrapper(intCertainLat, Bool()) 472 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 473 } 474 475 class ImmInfo extends Bundle { 476 val imm = UInt(32.W) 477 val immType = SelImm() 478 } 479 480 // DataPath --[ExuInput]--> Exu 481 class ExuInput(val params: ExeUnitParams, copyWakeupOut:Boolean = false, copyNum:Int = 0)(implicit p: Parameters) extends XSBundle { 482 val fuType = FuType() 483 val fuOpType = FuOpType() 484 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 485 val imm = UInt(32.W) 486 val robIdx = new RobPtr 487 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 488 val isFirstIssue = Bool() // Only used by store yet 489 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 490 val rfWenCopy = OptionWrapper(copyWakeupOut && params.writeIntRf, Vec(copyNum, Bool())) 491 val fpWenCopy = OptionWrapper(copyWakeupOut && params.writeFpRf, Vec(copyNum, Bool())) 492 val vecWenCopy = OptionWrapper(copyWakeupOut && params.writeVecRf, Vec(copyNum, Bool())) 493 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum,Vec(LoadPipelineWidth, UInt(3.W)))) 494 val pdest = UInt(params.wbPregIdxWidth.W) 495 val rfWen = if (params.writeIntRf) Some(Bool()) else None 496 val fpWen = if (params.writeFpRf) Some(Bool()) else None 497 val vecWen = if (params.writeVecRf) Some(Bool()) else None 498 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 499 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 500 val flushPipe = if (params.flushPipe) Some(Bool()) else None 501 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 502 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 503 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 504 Some(new FtqPtr) else None 505 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 506 Some(UInt(log2Up(PredictWidth).W)) else None 507 val predictInfo = if (params.needPdInfo) Some(new Bundle { 508 val target = UInt(VAddrData().dataWidth.W) 509 val taken = Bool() 510 }) else None 511 val loadWaitBit = OptionWrapper(params.hasLoadExu, Bool()) 512 val waitForRobIdx = OptionWrapper(params.hasLoadExu, new RobPtr) // store set predicted previous store robIdx 513 val storeSetHit = OptionWrapper(params.hasLoadExu, Bool()) // inst has been allocated an store set 514 val loadWaitStrict = OptionWrapper(params.hasLoadExu, Bool()) // load inst will not be executed until ALL former store addr calcuated 515 val ssid = OptionWrapper(params.hasLoadExu, UInt(SSIDWidth.W)) 516 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 517 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 518 val dataSources = Vec(params.numRegSrc, DataSource()) 519 val l1ExuOH = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuOH())) 520 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 521 val loadDependency = OptionWrapper(params.isIQWakeUpSink, Vec(LoadPipelineWidth, UInt(3.W))) 522 523 val perfDebugInfo = new PerfDebugInfo() 524 525 def exuIdx = this.params.exuIdx 526 527 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = { 528 if (params.isIQWakeUpSink) { 529 require( 530 og0CancelOH.getWidth == l1ExuOH.get.head.getWidth, 531 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}" 532 ) 533 val l1Cancel: Bool = l1ExuOH.get.zip(srcTimer.get).map { 534 case(exuOH: UInt, srcTimer: UInt) => 535 (exuOH & og0CancelOH).orR && srcTimer === 1.U 536 }.reduce(_ | _) 537 l1Cancel 538 } else { 539 false.B 540 } 541 } 542 543 def getVfWen = { 544 if (params.writeFpRf) this.fpWen 545 else if(params.writeVecRf) this.vecWen 546 else None 547 } 548 549 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 550 // src is assigned to rfReadData 551 this.fuType := source.common.fuType 552 this.fuOpType := source.common.fuOpType 553 this.imm := source.common.imm 554 this.robIdx := source.common.robIdx 555 this.pdest := source.common.pdest 556 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 557 this.iqIdx := source.common.iqIdx // Only used by mem feedback 558 this.dataSources := source.common.dataSources 559 this.l1ExuOH .foreach(_ := source.common.l1ExuOH.get) 560 this.rfWen .foreach(_ := source.common.rfWen.get) 561 this.fpWen .foreach(_ := source.common.fpWen.get) 562 this.vecWen .foreach(_ := source.common.vecWen.get) 563 this.fpu .foreach(_ := source.common.fpu.get) 564 this.vpu .foreach(_ := source.common.vpu.get) 565 this.flushPipe .foreach(_ := source.common.flushPipe.get) 566 this.pc .foreach(_ := source.common.pc.get) 567 this.preDecode .foreach(_ := source.common.preDecode.get) 568 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 569 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 570 this.predictInfo .foreach(_ := source.common.predictInfo.get) 571 this.loadWaitBit .foreach(_ := source.common.loadWaitBit.get) 572 this.waitForRobIdx .foreach(_ := source.common.waitForRobIdx.get) 573 this.storeSetHit .foreach(_ := source.common.storeSetHit.get) 574 this.loadWaitStrict.foreach(_ := source.common.loadWaitStrict.get) 575 this.ssid .foreach(_ := source.common.ssid.get) 576 this.lqIdx .foreach(_ := source.common.lqIdx.get) 577 this.sqIdx .foreach(_ := source.common.sqIdx.get) 578 this.srcTimer .foreach(_ := source.common.srcTimer.get) 579 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 580 } 581 } 582 583 // ExuInput --[FuncUnit]--> ExuOutput 584 class ExuOutput( 585 val params: ExeUnitParams, 586 )(implicit 587 val p: Parameters 588 ) extends Bundle with BundleSource with HasXSParameter { 589 val data = UInt(params.dataBitsMax.W) 590 val pdest = UInt(params.wbPregIdxWidth.W) 591 val robIdx = new RobPtr 592 val intWen = if (params.writeIntRf) Some(Bool()) else None 593 val fpWen = if (params.writeFpRf) Some(Bool()) else None 594 val vecWen = if (params.writeVecRf) Some(Bool()) else None 595 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 596 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 597 val wflags = if (params.writeFflags) Some(Bool()) else None 598 val vxsat = if (params.writeVxsat) Some(Bool()) else None 599 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 600 val flushPipe = if (params.flushPipe) Some(Bool()) else None 601 val replay = if (params.replayInst) Some(Bool()) else None 602 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 603 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 604 Some(new SqPtr()) else None 605 val trigger = if (params.trigger) Some(new TriggerCf) else None 606 // uop info 607 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 608 // vldu used only 609 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 610 val vpu = new VPUCtrlSignals 611 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 612 val vdIdx = UInt(3.W) 613 val vdIdxInField = UInt(3.W) 614 val isIndexed = Bool() 615 val isMasked = Bool() 616 }) 617 val debug = new DebugBundle 618 val debugInfo = new PerfDebugInfo 619 } 620 621 // ExuOutput + DynInst --> WriteBackBundle 622 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 623 val rfWen = Bool() 624 val fpWen = Bool() 625 val vecWen = Bool() 626 val pdest = UInt(params.pregIdxWidth(backendParams).W) 627 val data = UInt(params.dataWidth.W) 628 val robIdx = new RobPtr()(p) 629 val flushPipe = Bool() 630 val replayInst = Bool() 631 val redirect = ValidIO(new Redirect) 632 val fflags = UInt(5.W) 633 val vxsat = Bool() 634 val exceptionVec = ExceptionVec() 635 val debug = new DebugBundle 636 val debugInfo = new PerfDebugInfo 637 638 this.wakeupSource = s"WB(${params.toString})" 639 640 def fromExuOutput(source: ExuOutput) = { 641 this.rfWen := source.intWen.getOrElse(false.B) 642 this.fpWen := source.fpWen.getOrElse(false.B) 643 this.vecWen := source.vecWen.getOrElse(false.B) 644 this.pdest := source.pdest 645 this.data := source.data 646 this.robIdx := source.robIdx 647 this.flushPipe := source.flushPipe.getOrElse(false.B) 648 this.replayInst := source.replay.getOrElse(false.B) 649 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 650 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 651 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 652 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 653 this.debug := source.debug 654 this.debugInfo := source.debugInfo 655 } 656 657 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 658 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 659 rfWrite.wen := this.rfWen && fire 660 rfWrite.addr := this.pdest 661 rfWrite.data := this.data 662 rfWrite.intWen := this.rfWen 663 rfWrite.fpWen := false.B 664 rfWrite.vecWen := false.B 665 rfWrite 666 } 667 668 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 669 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 670 rfWrite.wen := (this.fpWen || this.vecWen) && fire 671 rfWrite.addr := this.pdest 672 rfWrite.data := this.data 673 rfWrite.intWen := false.B 674 rfWrite.fpWen := this.fpWen 675 rfWrite.vecWen := this.vecWen 676 rfWrite 677 } 678 } 679 680 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 681 // / 682 // [IssueQueue]--> ExuInput -- 683 class ExuBypassBundle( 684 val params: ExeUnitParams, 685 )(implicit 686 val p: Parameters 687 ) extends Bundle { 688 val data = UInt(params.dataBitsMax.W) 689 val pdest = UInt(params.wbPregIdxWidth.W) 690 } 691 692 class ExceptionInfo(implicit p: Parameters) extends Bundle { 693 val pc = UInt(VAddrData().dataWidth.W) 694 val instr = UInt(32.W) 695 val commitType = CommitType() 696 val exceptionVec = ExceptionVec() 697 val singleStep = Bool() 698 val crossPageIPFFix = Bool() 699 val isInterrupt = Bool() 700 val vls = Bool() 701 val trigger = new TriggerCf 702 } 703 704 object UopIdx { 705 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 706 } 707 708 object FuLatency { 709 def apply(): UInt = UInt(width.W) 710 711 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 712 } 713 714 object ExuOH { 715 def apply(exuNum: Int): UInt = UInt(exuNum.W) 716 717 def apply()(implicit p: Parameters): UInt = UInt(width.W) 718 719 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 720 } 721 722 object ExuVec { 723 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 724 725 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 726 727 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 728 } 729 730 class CancelSignal(implicit p: Parameters) extends XSBundle { 731 val rfWen = Bool() 732 val fpWen = Bool() 733 val vecWen = Bool() 734 val pdest = UInt(PhyRegIdxWidth.W) 735 736 def needCancel(srcType: UInt, psrc: UInt, valid: Bool): Bool = { 737 val pdestMatch = pdest === psrc 738 pdestMatch && ( 739 SrcType.isFp(srcType) && !this.rfWen || 740 SrcType.isXp(srcType) && this.rfWen || 741 SrcType.isVp(srcType) && !this.rfWen 742 ) && valid 743 } 744 } 745 746 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 747 val uop = new DynInst 748 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 749 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 750 val isFirstIssue = Bool() 751 752 def src_rs1 = src(0) 753 def src_stride = src(1) 754 def src_vs3 = src(2) 755 def src_mask = if (isVector) src(3) else 0.U 756 def src_vl = if (isVector) src(4) else 0.U 757 } 758 759 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 760 val uop = new DynInst 761 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 762 val mask = if (isVector) Some(UInt(VLEN.W)) else None 763 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 764 val vdIdxInField = if (isVector) Some(UInt(3.W)) else None 765 val debug = new DebugBundle 766 767 def isVls = FuType.isVls(uop.fuType) 768 } 769 770 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 771 val uop = new DynInst 772 val flag = UInt(1.W) 773 } 774 775 object LoadShouldCancel { 776 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 777 val ld1Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld1Cancel)).map { case (dep, cancel) => cancel && dep(1)}.reduce(_ || _)) 778 val ld2Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld2Cancel)).map { case (dep, cancel) => cancel && dep(2)}.reduce(_ || _)) 779 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 780 } 781 } 782} 783