1package xiangshan.backend 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, IssueQueueJumpBundle, SchedulerType} 19import xiangshan.backend.issue.EntryBundles._ 20import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 21import xiangshan.backend.rob.RobPtr 22import xiangshan.frontend._ 23import xiangshan.mem.{LqPtr, SqPtr} 24 25object Bundles { 26 /** 27 * Connect Same Name Port like bundleSource := bundleSinkBudle. 28 * 29 * There is no limit to the number of ports on both sides. 30 * 31 * Don't forget to connect the remaining ports! 32 */ 33 def connectSamePort (bundleSource: Bundle, bundleSink: Bundle):Unit = { 34 bundleSource.elements.foreach { case (name, data) => 35 if (bundleSink.elements.contains(name)) 36 data := bundleSink.elements(name) 37 } 38 } 39 // frontend -> backend 40 class StaticInst(implicit p: Parameters) extends XSBundle { 41 val instr = UInt(32.W) 42 val pc = UInt(VAddrBits.W) 43 val foldpc = UInt(MemPredPCWidth.W) 44 val exceptionVec = ExceptionVec() 45 val trigger = new TriggerCf 46 val preDecodeInfo = new PreDecodeInfo 47 val pred_taken = Bool() 48 val crossPageIPFFix = Bool() 49 val ftqPtr = new FtqPtr 50 val ftqOffset = UInt(log2Up(PredictWidth).W) 51 52 def connectCtrlFlow(source: CtrlFlow): Unit = { 53 this.instr := source.instr 54 this.pc := source.pc 55 this.foldpc := source.foldpc 56 this.exceptionVec := source.exceptionVec 57 this.trigger := source.trigger 58 this.preDecodeInfo := source.pd 59 this.pred_taken := source.pred_taken 60 this.crossPageIPFFix := source.crossPageIPFFix 61 this.ftqPtr := source.ftqPtr 62 this.ftqOffset := source.ftqOffset 63 } 64 } 65 66 // StaticInst --[Decode]--> DecodedInst 67 class DecodedInst(implicit p: Parameters) extends XSBundle { 68 def numSrc = backendParams.numSrc 69 // passed from StaticInst 70 val instr = UInt(32.W) 71 val pc = UInt(VAddrBits.W) 72 val foldpc = UInt(MemPredPCWidth.W) 73 val exceptionVec = ExceptionVec() 74 val trigger = new TriggerCf 75 val preDecodeInfo = new PreDecodeInfo 76 val pred_taken = Bool() 77 val crossPageIPFFix = Bool() 78 val ftqPtr = new FtqPtr 79 val ftqOffset = UInt(log2Up(PredictWidth).W) 80 // decoded 81 val srcType = Vec(numSrc, SrcType()) 82 val lsrc = Vec(numSrc, UInt(6.W)) 83 val ldest = UInt(6.W) 84 val fuType = FuType() 85 val fuOpType = FuOpType() 86 val rfWen = Bool() 87 val fpWen = Bool() 88 val vecWen = Bool() 89 val isXSTrap = Bool() 90 val waitForward = Bool() // no speculate execution 91 val blockBackward = Bool() 92 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 93 val canRobCompress = Bool() 94 val selImm = SelImm() 95 val imm = UInt(ImmUnion.maxLen.W) 96 val fpu = new FPUCtrlSignals 97 val vpu = new VPUCtrlSignals 98 val vlsInstr = Bool() 99 val wfflags = Bool() 100 val isMove = Bool() 101 val uopIdx = UopIdx() 102 val uopSplitType = UopSplitType() 103 val isVset = Bool() 104 val firstUop = Bool() 105 val lastUop = Bool() 106 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 107 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 108 val commitType = CommitType() // Todo: remove it 109 110 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 111 112 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 113 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 114 115 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 116 val decoder: Seq[UInt] = ListLookup( 117 inst, XDecode.decodeDefault.map(bitPatToUInt), 118 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 119 ) 120 allSignals zip decoder foreach { case (s, d) => s := d } 121 debug_fuType.foreach(_ := fuType) 122 this 123 } 124 125 def isSoftPrefetch: Bool = { 126 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 127 } 128 129 def connectStaticInst(source: StaticInst): Unit = { 130 for ((name, data) <- this.elements) { 131 if (source.elements.contains(name)) { 132 data := source.elements(name) 133 } 134 } 135 } 136 } 137 138 // DecodedInst --[Rename]--> DynInst 139 class DynInst(implicit p: Parameters) extends XSBundle { 140 def numSrc = backendParams.numSrc 141 // passed from StaticInst 142 val instr = UInt(32.W) 143 val pc = UInt(VAddrBits.W) 144 val foldpc = UInt(MemPredPCWidth.W) 145 val exceptionVec = ExceptionVec() 146 val trigger = new TriggerCf 147 val preDecodeInfo = new PreDecodeInfo 148 val pred_taken = Bool() 149 val crossPageIPFFix = Bool() 150 val ftqPtr = new FtqPtr 151 val ftqOffset = UInt(log2Up(PredictWidth).W) 152 // passed from DecodedInst 153 val srcType = Vec(numSrc, SrcType()) 154 val lsrc = Vec(numSrc, UInt(6.W)) 155 val ldest = UInt(6.W) 156 val fuType = FuType() 157 val fuOpType = FuOpType() 158 val rfWen = Bool() 159 val fpWen = Bool() 160 val vecWen = Bool() 161 val isXSTrap = Bool() 162 val waitForward = Bool() // no speculate execution 163 val blockBackward = Bool() 164 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 165 val canRobCompress = Bool() 166 val selImm = SelImm() 167 val imm = UInt(32.W) 168 val fpu = new FPUCtrlSignals 169 val vpu = new VPUCtrlSignals 170 val vlsInstr = Bool() 171 val wfflags = Bool() 172 val isMove = Bool() 173 val uopIdx = UopIdx() 174 val isVset = Bool() 175 val firstUop = Bool() 176 val lastUop = Bool() 177 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 178 val numWB = UInt(log2Up(MaxUopSize).W) // rob need this 179 val commitType = CommitType() 180 // rename 181 val srcState = Vec(numSrc, SrcState()) 182 val srcLoadDependency = Vec(numSrc, Vec(LoadPipelineWidth, UInt(3.W))) 183 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 184 val pdest = UInt(PhyRegIdxWidth.W) 185 val robIdx = new RobPtr 186 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 187 val dirtyFs = Bool() 188 189 val eliminatedMove = Bool() 190 // Take snapshot at this CFI inst 191 val snapshot = Bool() 192 val debugInfo = new PerfDebugInfo 193 val storeSetHit = Bool() // inst has been allocated an store set 194 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 195 // Load wait is needed 196 // load inst will not be executed until former store (predicted by mdp) addr calcuated 197 val loadWaitBit = Bool() 198 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 199 // load inst will not be executed until ALL former store addr calcuated 200 val loadWaitStrict = Bool() 201 val ssid = UInt(SSIDWidth.W) 202 // Todo 203 val lqIdx = new LqPtr 204 val sqIdx = new SqPtr 205 // debug module 206 val singleStep = Bool() 207 // schedule 208 val replayInst = Bool() 209 210 val debug_fuType = OptionWrapper(backendParams.debugEn, FuType()) 211 212 def getDebugFuType: UInt = debug_fuType.getOrElse(fuType) 213 214 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 215 def isLUI32: Bool = this.selImm === SelImm.IMM_LUI32 216 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 217 218 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 219 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 220 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 221 222 def srcIsReady: Vec[Bool] = { 223 VecInit(this.srcType.zip(this.srcState).map { 224 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 225 }) 226 } 227 228 def clearExceptions( 229 exceptionBits: Seq[Int] = Seq(), 230 flushPipe : Boolean = false, 231 replayInst : Boolean = false 232 ): DynInst = { 233 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 234 if (!flushPipe) { this.flushPipe := false.B } 235 if (!replayInst) { this.replayInst := false.B } 236 this 237 } 238 239 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen 240 } 241 242 trait BundleSource { 243 var wakeupSource = "undefined" 244 var idx = 0 245 } 246 247 /** 248 * 249 * @param pregIdxWidth index width of preg 250 * @param exuIndices exu indices of wakeup bundle 251 */ 252 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int]) extends Bundle { 253 val rfWen = Bool() 254 val fpWen = Bool() 255 val vecWen = Bool() 256 val pdest = UInt(pregIdxWidth.W) 257 258 /** 259 * @param successor Seq[(psrc, srcType)] 260 * @return Seq[if wakeup psrc] 261 */ 262 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 263 successor.map { case (thatPsrc, srcType) => 264 val pdestMatch = pdest === thatPsrc 265 pdestMatch && ( 266 SrcType.isFp(srcType) && this.fpWen || 267 SrcType.isXp(srcType) && this.rfWen || 268 SrcType.isVp(srcType) && this.vecWen 269 ) && valid 270 } 271 } 272 def wakeUpFromIQ(successor: Seq[(UInt, UInt)]): Seq[Bool] = { 273 successor.map { case (thatPsrc, srcType) => 274 val pdestMatch = pdest === thatPsrc 275 pdestMatch && ( 276 SrcType.isFp(srcType) && this.fpWen || 277 SrcType.isXp(srcType) && this.rfWen || 278 SrcType.isVp(srcType) && this.vecWen 279 ) 280 } 281 } 282 283 def hasOnlyOneSource: Boolean = exuIndices.size == 1 284 285 def hasMultiSources: Boolean = exuIndices.size > 1 286 287 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 288 289 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 290 291 def exuIdx: Int = { 292 require(hasOnlyOneSource) 293 this.exuIndices.head 294 } 295 } 296 297 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 298 299 } 300 301class IssueQueueIQWakeUpBundle( 302 exuIdx: Int, 303 backendParams: BackendParams, 304 copyWakeupOut: Boolean = false, 305 copyNum: Int = 0 306) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 307 val loadDependency = Vec(backendParams.LduCnt + backendParams.HyuCnt, UInt(3.W)) 308 val is0Lat = Bool() 309 val params = backendParams.allExuParams.filter(_.exuIdx == exuIdx).head 310 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 311 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 312 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 313 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 314 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum,Vec(backendParams.LdExuCnt, UInt(3.W)))) 315 def fromExuInput(exuInput: ExuInput, l2ExuVecs: Vec[UInt]): Unit = { 316 this.rfWen := exuInput.rfWen.getOrElse(false.B) 317 this.fpWen := exuInput.fpWen.getOrElse(false.B) 318 this.vecWen := exuInput.vecWen.getOrElse(false.B) 319 this.pdest := exuInput.pdest 320 } 321 322 def fromExuInput(exuInput: ExuInput): Unit = { 323 this.rfWen := exuInput.rfWen.getOrElse(false.B) 324 this.fpWen := exuInput.fpWen.getOrElse(false.B) 325 this.vecWen := exuInput.vecWen.getOrElse(false.B) 326 this.pdest := exuInput.pdest 327 } 328 } 329 330 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 331 // vtype 332 val vill = Bool() 333 val vma = Bool() // 1: agnostic, 0: undisturbed 334 val vta = Bool() // 1: agnostic, 0: undisturbed 335 val vsew = VSew() 336 val vlmul = VLmul() // 1/8~8 --> -3~3 337 338 val vm = Bool() // 0: need v0.t 339 val vstart = Vl() 340 341 // float rounding mode 342 val frm = Frm() 343 // scalar float instr and vector float reduction 344 val fpu = Fpu() 345 // vector fix int rounding mode 346 val vxrm = Vxrm() 347 // vector uop index, exclude other non-vector uop 348 val vuopIdx = UopIdx() 349 val lastUop = Bool() 350 // maybe used if data dependancy 351 val vmask = UInt(MaskSrcData().dataWidth.W) 352 val vl = Vl() 353 354 // vector load/store 355 val nf = Nf() 356 val veew = VEew() 357 358 val isReverse = Bool() // vrsub, vrdiv 359 val isExt = Bool() 360 val isNarrow = Bool() 361 val isDstMask = Bool() // vvm, vvvm, mmm 362 val isOpMask = Bool() // vmand, vmnand 363 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 364 365 def vtype: VType = { 366 val res = Wire(VType()) 367 res.illegal := this.vill 368 res.vma := this.vma 369 res.vta := this.vta 370 res.vsew := this.vsew 371 res.vlmul := this.vlmul 372 res 373 } 374 375 def vconfig: VConfig = { 376 val res = Wire(VConfig()) 377 res.vtype := this.vtype 378 res.vl := this.vl 379 res 380 } 381 382 def connectVType(source: VType): Unit = { 383 this.vill := source.illegal 384 this.vma := source.vma 385 this.vta := source.vta 386 this.vsew := source.vsew 387 this.vlmul := source.vlmul 388 } 389 } 390 391 // DynInst --[IssueQueue]--> DataPath 392 class IssueQueueIssueBundle( 393 iqParams: IssueBlockParams, 394 val exuParams: ExeUnitParams, 395 )(implicit 396 p: Parameters 397 ) extends Bundle { 398 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 399 // check which set both have fp and vec and remove fp 400 private val rfReadDataCfgSetFilterFp = rfReadDataCfgSet.map((set: Set[DataConfig]) => 401 if (set.contains(FpData()) && set.contains(VecData())) set.filter(_ != FpData()) 402 else set 403 ) 404 405 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 406 rfReadDataCfgSetFilterFp.map((set: Set[DataConfig]) => 407 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 408 ) 409 )) 410 411 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 412 val immType = SelImm() // used to select imm extractor 413 val common = new ExuInput(exuParams) 414 val addrOH = UInt(iqParams.numEntries.W) 415 416 def exuIdx = exuParams.exuIdx 417 def getSource: SchedulerType = exuParams.getWBSource 418 def getIntWbBusyBundle = common.rfWen.toSeq 419 def getVfWbBusyBundle = common.getVfWen.toSeq 420 421 def getIntRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 422 rf.zip(srcType).map { 423 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 424 makeValid(issueValid, rfRd.head) 425 }.toSeq 426 } 427 428 def getVfRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 429 rf.zip(srcType).map { 430 case (rfRd: MixedVec[RfReadPortWithConfig], t: UInt) => 431 makeValid(issueValid, rfRd.head) 432 }.toSeq 433 } 434 435 def getIntRfWriteValidBundle(issueValid: Bool) = { 436 437 } 438 } 439 440 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 441 val issueQueueParams = this.params 442 val og0resp = Valid(new EntryDeqRespBundle) 443 val og1resp = Valid(new EntryDeqRespBundle) 444 } 445 446 class fuBusyRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 447 val respType = RSFeedbackType() // update credit if needs replay 448 val rfWen = Bool() // TODO: use params to identify IntWB/VfWB 449 val fuType = FuType() 450 } 451 452 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 453 private val intCertainLat = params.intLatencyCertain 454 private val vfCertainLat = params.vfLatencyCertain 455 private val intLat = params.intLatencyValMax 456 private val vfLat = params.vfLatencyValMax 457 458 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 459 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 460 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 461 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 462 } 463 464 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 465 private val intCertainLat = params.intLatencyCertain 466 private val vfCertainLat = params.vfLatencyCertain 467 private val intLat = params.intLatencyValMax 468 private val vfLat = params.vfLatencyValMax 469 470 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 471 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 472 } 473 474 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 475 private val intCertainLat = params.intLatencyCertain 476 private val vfCertainLat = params.vfLatencyCertain 477 478 val intConflict = OptionWrapper(intCertainLat, Bool()) 479 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 480 } 481 482 class ImmInfo extends Bundle { 483 val imm = UInt(32.W) 484 val immType = SelImm() 485 } 486 487 // DataPath --[ExuInput]--> Exu 488 class ExuInput(val params: ExeUnitParams, copyWakeupOut:Boolean = false, copyNum:Int = 0)(implicit p: Parameters) extends XSBundle { 489 val fuType = FuType() 490 val fuOpType = FuOpType() 491 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 492 val imm = UInt(32.W) 493 val robIdx = new RobPtr 494 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 495 val isFirstIssue = Bool() // Only used by store yet 496 val pdestCopy = OptionWrapper(copyWakeupOut, Vec(copyNum, UInt(params.wbPregIdxWidth.W))) 497 val rfWenCopy = OptionWrapper(copyWakeupOut && params.needIntWen, Vec(copyNum, Bool())) 498 val fpWenCopy = OptionWrapper(copyWakeupOut && params.needFpWen, Vec(copyNum, Bool())) 499 val vecWenCopy = OptionWrapper(copyWakeupOut && params.needVecWen, Vec(copyNum, Bool())) 500 val loadDependencyCopy = OptionWrapper(copyWakeupOut && params.isIQWakeUpSink, Vec(copyNum,Vec(LoadPipelineWidth, UInt(3.W)))) 501 val pdest = UInt(params.wbPregIdxWidth.W) 502 val rfWen = if (params.needIntWen) Some(Bool()) else None 503 val fpWen = if (params.needFpWen) Some(Bool()) else None 504 val vecWen = if (params.needVecWen) Some(Bool()) else None 505 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 506 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 507 val flushPipe = if (params.flushPipe) Some(Bool()) else None 508 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 509 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 510 val ftqIdx = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 511 Some(new FtqPtr) else None 512 val ftqOffset = if (params.needPc || params.replayInst || params.hasStoreAddrFu) 513 Some(UInt(log2Up(PredictWidth).W)) else None 514 val predictInfo = if (params.needPdInfo) Some(new Bundle { 515 val target = UInt(VAddrData().dataWidth.W) 516 val taken = Bool() 517 }) else None 518 val loadWaitBit = OptionWrapper(params.hasLoadExu, Bool()) 519 val waitForRobIdx = OptionWrapper(params.hasLoadExu, new RobPtr) // store set predicted previous store robIdx 520 val storeSetHit = OptionWrapper(params.hasLoadExu, Bool()) // inst has been allocated an store set 521 val loadWaitStrict = OptionWrapper(params.hasLoadExu, Bool()) // load inst will not be executed until ALL former store addr calcuated 522 val ssid = OptionWrapper(params.hasLoadExu, UInt(SSIDWidth.W)) 523 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 524 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 525 val dataSources = Vec(params.numRegSrc, DataSource()) 526 val l1ExuOH = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuOH())) 527 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 528 val loadDependency = OptionWrapper(params.isIQWakeUpSink, Vec(LoadPipelineWidth, UInt(3.W))) 529 530 val perfDebugInfo = new PerfDebugInfo() 531 532 def exuIdx = this.params.exuIdx 533 534 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = { 535 if (params.isIQWakeUpSink) { 536 require( 537 og0CancelOH.getWidth == l1ExuOH.get.head.getWidth, 538 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}" 539 ) 540 val l1Cancel: Bool = l1ExuOH.get.zip(srcTimer.get).map { 541 case(exuOH: UInt, srcTimer: UInt) => 542 (exuOH & og0CancelOH).orR && srcTimer === 1.U 543 }.reduce(_ | _) 544 l1Cancel 545 } else { 546 false.B 547 } 548 } 549 550 def getVfWen = { 551 if (params.writeFpRf) this.fpWen 552 else if(params.writeVecRf) this.vecWen 553 else None 554 } 555 556 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 557 // src is assigned to rfReadData 558 this.fuType := source.common.fuType 559 this.fuOpType := source.common.fuOpType 560 this.imm := source.common.imm 561 this.robIdx := source.common.robIdx 562 this.pdest := source.common.pdest 563 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 564 this.iqIdx := source.common.iqIdx // Only used by mem feedback 565 this.dataSources := source.common.dataSources 566 this.l1ExuOH .foreach(_ := source.common.l1ExuOH.get) 567 this.rfWen .foreach(_ := source.common.rfWen.get) 568 this.fpWen .foreach(_ := source.common.fpWen.get) 569 this.vecWen .foreach(_ := source.common.vecWen.get) 570 this.fpu .foreach(_ := source.common.fpu.get) 571 this.vpu .foreach(_ := source.common.vpu.get) 572 this.flushPipe .foreach(_ := source.common.flushPipe.get) 573 this.pc .foreach(_ := source.common.pc.get) 574 this.preDecode .foreach(_ := source.common.preDecode.get) 575 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 576 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 577 this.predictInfo .foreach(_ := source.common.predictInfo.get) 578 this.loadWaitBit .foreach(_ := source.common.loadWaitBit.get) 579 this.waitForRobIdx .foreach(_ := source.common.waitForRobIdx.get) 580 this.storeSetHit .foreach(_ := source.common.storeSetHit.get) 581 this.loadWaitStrict.foreach(_ := source.common.loadWaitStrict.get) 582 this.ssid .foreach(_ := source.common.ssid.get) 583 this.lqIdx .foreach(_ := source.common.lqIdx.get) 584 this.sqIdx .foreach(_ := source.common.sqIdx.get) 585 this.srcTimer .foreach(_ := source.common.srcTimer.get) 586 this.loadDependency.foreach(_ := source.common.loadDependency.get.map(_ << 1)) 587 } 588 } 589 590 // ExuInput --[FuncUnit]--> ExuOutput 591 class ExuOutput( 592 val params: ExeUnitParams, 593 )(implicit 594 val p: Parameters 595 ) extends Bundle with BundleSource with HasXSParameter { 596 val data = UInt(params.dataBitsMax.W) 597 val pdest = UInt(params.wbPregIdxWidth.W) 598 val robIdx = new RobPtr 599 val intWen = if (params.needIntWen) Some(Bool()) else None 600 val fpWen = if (params.needFpWen) Some(Bool()) else None 601 val vecWen = if (params.needVecWen) Some(Bool()) else None 602 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 603 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 604 val wflags = if (params.writeFflags) Some(Bool()) else None 605 val vxsat = if (params.writeVxsat) Some(Bool()) else None 606 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 607 val flushPipe = if (params.flushPipe) Some(Bool()) else None 608 val replay = if (params.replayInst) Some(Bool()) else None 609 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 610 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 611 Some(new SqPtr()) else None 612 val trigger = if (params.trigger) Some(new TriggerCf) else None 613 // uop info 614 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 615 // vldu used only 616 val vls = OptionWrapper(params.hasVLoadFu, new Bundle { 617 val vpu = new VPUCtrlSignals 618 val oldVdPsrc = UInt(PhyRegIdxWidth.W) 619 val vdIdx = UInt(3.W) 620 val vdIdxInField = UInt(3.W) 621 val isIndexed = Bool() 622 val isMasked = Bool() 623 }) 624 val debug = new DebugBundle 625 val debugInfo = new PerfDebugInfo 626 } 627 628 // ExuOutput + DynInst --> WriteBackBundle 629 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 630 val rfWen = Bool() 631 val fpWen = Bool() 632 val vecWen = Bool() 633 val pdest = UInt(params.pregIdxWidth(backendParams).W) 634 val data = UInt(params.dataWidth.W) 635 val robIdx = new RobPtr()(p) 636 val flushPipe = Bool() 637 val replayInst = Bool() 638 val redirect = ValidIO(new Redirect) 639 val fflags = UInt(5.W) 640 val vxsat = Bool() 641 val exceptionVec = ExceptionVec() 642 val debug = new DebugBundle 643 val debugInfo = new PerfDebugInfo 644 645 this.wakeupSource = s"WB(${params.toString})" 646 647 def fromExuOutput(source: ExuOutput) = { 648 this.rfWen := source.intWen.getOrElse(false.B) 649 this.fpWen := source.fpWen.getOrElse(false.B) 650 this.vecWen := source.vecWen.getOrElse(false.B) 651 this.pdest := source.pdest 652 this.data := source.data 653 this.robIdx := source.robIdx 654 this.flushPipe := source.flushPipe.getOrElse(false.B) 655 this.replayInst := source.replay.getOrElse(false.B) 656 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 657 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 658 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 659 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 660 this.debug := source.debug 661 this.debugInfo := source.debugInfo 662 } 663 664 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 665 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 666 rfWrite.wen := this.rfWen && fire 667 rfWrite.addr := this.pdest 668 rfWrite.data := this.data 669 rfWrite.intWen := this.rfWen 670 rfWrite.fpWen := false.B 671 rfWrite.vecWen := false.B 672 rfWrite 673 } 674 675 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 676 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 677 rfWrite.wen := (this.fpWen || this.vecWen) && fire 678 rfWrite.addr := this.pdest 679 rfWrite.data := this.data 680 rfWrite.intWen := false.B 681 rfWrite.fpWen := this.fpWen 682 rfWrite.vecWen := this.vecWen 683 rfWrite 684 } 685 } 686 687 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 688 // / 689 // [IssueQueue]--> ExuInput -- 690 class ExuBypassBundle( 691 val params: ExeUnitParams, 692 )(implicit 693 val p: Parameters 694 ) extends Bundle { 695 val data = UInt(params.dataBitsMax.W) 696 val pdest = UInt(params.wbPregIdxWidth.W) 697 } 698 699 class ExceptionInfo(implicit p: Parameters) extends Bundle { 700 val pc = UInt(VAddrData().dataWidth.W) 701 val instr = UInt(32.W) 702 val commitType = CommitType() 703 val exceptionVec = ExceptionVec() 704 val singleStep = Bool() 705 val crossPageIPFFix = Bool() 706 val isInterrupt = Bool() 707 val vls = Bool() 708 val trigger = new TriggerCf 709 } 710 711 object UopIdx { 712 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 713 } 714 715 object FuLatency { 716 def apply(): UInt = UInt(width.W) 717 718 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 719 } 720 721 object ExuOH { 722 def apply(exuNum: Int): UInt = UInt(exuNum.W) 723 724 def apply()(implicit p: Parameters): UInt = UInt(width.W) 725 726 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 727 } 728 729 object ExuVec { 730 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 731 732 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 733 734 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 735 } 736 737 class CancelSignal(implicit p: Parameters) extends XSBundle { 738 val rfWen = Bool() 739 val fpWen = Bool() 740 val vecWen = Bool() 741 val pdest = UInt(PhyRegIdxWidth.W) 742 743 def needCancel(srcType: UInt, psrc: UInt, valid: Bool): Bool = { 744 val pdestMatch = pdest === psrc 745 pdestMatch && ( 746 SrcType.isFp(srcType) && !this.rfWen || 747 SrcType.isXp(srcType) && this.rfWen || 748 SrcType.isVp(srcType) && !this.rfWen 749 ) && valid 750 } 751 } 752 753 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 754 val uop = new DynInst 755 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 756 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 757 val isFirstIssue = Bool() 758 759 def src_rs1 = src(0) 760 def src_stride = src(1) 761 def src_vs3 = src(2) 762 def src_mask = if (isVector) src(3) else 0.U 763 def src_vl = if (isVector) src(4) else 0.U 764 } 765 766 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 767 val uop = new DynInst 768 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 769 val mask = if (isVector) Some(UInt(VLEN.W)) else None 770 val vdIdx = if (isVector) Some(UInt(3.W)) else None // TODO: parameterize width 771 val vdIdxInField = if (isVector) Some(UInt(3.W)) else None 772 val debug = new DebugBundle 773 774 def isVls = FuType.isVls(uop.fuType) 775 } 776 777 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 778 val uop = new DynInst 779 val flag = UInt(1.W) 780 } 781 782 object LoadShouldCancel { 783 def apply(loadDependency: Option[Seq[UInt]], ldCancel: Seq[LoadCancelIO]): Bool = { 784 val ld1Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld1Cancel)).map { case (dep, cancel) => cancel && dep(1)}.reduce(_ || _)) 785 val ld2Cancel = loadDependency.map(_.zip(ldCancel.map(_.ld2Cancel)).map { case (dep, cancel) => cancel && dep(2)}.reduce(_ || _)) 786 ld1Cancel.map(_ || ld2Cancel.get).getOrElse(false.B) 787 } 788 } 789} 790