| #
a428082b |
| 04-Aug-2020 |
LinJiawei <[email protected]> |
Merge master into dev-fronend
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| #
fb019544 |
| 31-Jul-2020 |
LinJiawei <[email protected]> |
Backend: add tlbFeedback
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| #
afd79d56 |
| 31-Jul-2020 |
William Wang <[email protected]> |
Mem: fix redirect logic
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| #
7f8272c4 |
| 31-Jul-2020 |
Yinan Xu <[email protected]> |
dispatch2: add dispatch2fp
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| #
6b8d1ed8 |
| 30-Jul-2020 |
LinJiawei <[email protected]> |
Merge branch 'temp-lsu-test' of https://github.com/RISCVERS/XiangShan into temp-lsu-test
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| #
59e12078 |
| 30-Jul-2020 |
LinJiawei <[email protected]> |
IssueQueue: support bypass
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| #
cafc71ed |
| 30-Jul-2020 |
LinJiawei <[email protected]> |
Wbu: update arbiter
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| #
518d8658 |
| 29-Jul-2020 |
Yinan Xu <[email protected]> |
dispatch queue: support replay and commit
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| #
bb411583 |
| 29-Jul-2020 |
Yinan Xu <[email protected]> |
Merge remote-tracking branch 'origin/temp-lsu-test' into dev-new-dispatch
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| #
5712beea |
| 29-Jul-2020 |
LinJiawei <[email protected]> |
IssueQueue: update issue queue io, add 'tlbHit'
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| #
5a84dde5 |
| 29-Jul-2020 |
LinJiawei <[email protected]> |
mem: add replay
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| #
6e962ad0 |
| 29-Jul-2020 |
LinJiawei <[email protected]> |
Merge refactor-redirect into temp-lsu-test
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| #
250b716d |
| 29-Jul-2020 |
Yinan Xu <[email protected]> |
dispatch2: refactor logic
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| #
b2e6921e |
| 28-Jul-2020 |
LinJiawei <[email protected]> |
Refactor redirect, cputest pass, microbench fail
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| #
5d4fa790 |
| 28-Jul-2020 |
LinJiawei <[email protected]> |
Dispatch,IssueQueue: update regfile read logic
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| #
c4459445 |
| 27-Jul-2020 |
LinJiawei <[email protected]> |
Backend: connect fp regfile into pipeline
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| #
6624015f |
| 27-Jul-2020 |
LinJiawei <[email protected]> |
New arch to support out-of-order load/store
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| #
6e3ea132 |
| 26-Jul-2020 |
LinJiawei <[email protected]> |
Merge master into temp-lsu-test; turn off Lsroq
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| #
f66e611a |
| 26-Jul-2020 |
LinJiawei <[email protected]> |
Revert "Mem: connect mem pipeline into backend"
This reverts commit 3fedfe355fef96d0a36f91c9b2c0bb1b787678fc.
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| #
1eeb0919 |
| 21-Jul-2020 |
LinJiawei <[email protected]> |
Brq: send in-order-redirect to update bpu
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| #
09881190 |
| 21-Jul-2020 |
LinJiawei <[email protected]> |
Brq: a branch instr can only dequeue when roq commit it
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| #
3fedfe35 |
| 21-Jul-2020 |
LinJiawei <[email protected]> |
Mem: connect mem pipeline into backend
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| #
93cb6b10 |
| 20-Jul-2020 |
William Wang <[email protected]> |
Mem: link lsroq with dispatch
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| #
390ce3d2 |
| 19-Jul-2020 |
William Wang <[email protected]> |
Mem: link Memend to NutShell dcache/dtlb
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| #
11915f69 |
| 19-Jul-2020 |
William Wang <[email protected]> |
Mem: rename scommit to mcommit
* mcommit represents that a mem inst is retired,
lsu can write dcache / move lsroq tailptr
* mcommit uses the same datapath as scommit
|