1package xiangshan.backend 2 3import bus.simplebus.SimpleBusUC 4import chisel3._ 5import chisel3.util._ 6import chisel3.util.experimental.BoringUtils 7import noop.MemMMUIO 8import xiangshan._ 9import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 10import xiangshan.backend.rename.Rename 11import xiangshan.backend.brq.Brq 12import xiangshan.backend.dispatch.Dispatch 13import xiangshan.backend.exu._ 14import xiangshan.backend.fu.FunctionUnit 15import xiangshan.backend.issue.IssueQueue 16import xiangshan.backend.regfile.{Regfile, RfWritePort} 17import xiangshan.backend.roq.Roq 18import xiangshan.mem._ 19 20 21/** Backend Pipeline: 22 * Decode -> Rename -> Dispatch-1 -> Dispatch-2 -> Issue -> Exe 23 */ 24class Backend(implicit val p: XSConfig) extends XSModule 25 with NeedImpl { 26 val io = IO(new Bundle { 27 // val dmem = new SimpleBusUC(addrBits = VAddrBits) 28 val memMMU = Flipped(new MemMMUIO) 29 val frontend = Flipped(new FrontendToBackendIO) 30 val mem = Flipped(new MemToBackendIO) 31 }) 32 33 34 val aluExeUnits = Array.tabulate(exuParameters.AluCnt)(_ => Module(new AluExeUnit)) 35 val jmpExeUnit = Module(new JmpExeUnit) 36 val mulExeUnits = Array.tabulate(exuParameters.MulCnt)(_ => Module(new MulExeUnit)) 37 val mduExeUnits = Array.tabulate(exuParameters.MduCnt)(_ => Module(new MulDivExeUnit)) 38 // val fmacExeUnits = Array.tabulate(exuParameters.FmacCnt)(_ => Module(new Fmac)) 39 // val fmiscExeUnits = Array.tabulate(exuParameters.FmiscCnt)(_ => Module(new Fmisc)) 40 // val fmiscDivSqrtExeUnits = Array.tabulate(exuParameters.FmiscDivSqrtCnt)(_ => Module(new FmiscDivSqrt)) 41 val lsuExeUnits = Array.tabulate(exuParameters.StuCnt)(_ => Module(new LsExeUnit)) 42 val exeUnits = jmpExeUnit +: (aluExeUnits ++ mulExeUnits ++ mduExeUnits ++ lsuExeUnits) 43 exeUnits.foreach(_.io.dmem := DontCare) 44 exeUnits.foreach(_.io.mcommit := DontCare) 45 46 val decode = Module(new DecodeStage) 47 val brq = Module(new Brq) 48 val decBuf = Module(new DecodeBuffer) 49 val rename = Module(new Rename) 50 val dispatch = Module(new Dispatch(exeUnits.map(_.config))) 51 val roq = Module(new Roq) 52 val intRf = Module(new Regfile( 53 numReadPorts = NRReadPorts, 54 numWirtePorts = NRWritePorts, 55 hasZero = true 56 )) 57 val fpRf = Module(new Regfile( 58 numReadPorts = NRReadPorts, 59 numWirtePorts = NRWritePorts, 60 hasZero = false 61 )) 62 63 // backend redirect, flush pipeline 64 val redirect = Mux(roq.io.redirect.valid, roq.io.redirect, brq.io.redirect) 65 66 val redirectInfo = Wire(new RedirectInfo) 67 // exception or misprediction 68 redirectInfo.valid := roq.io.redirect.valid || brq.io.out.valid 69 redirectInfo.misPred := !roq.io.redirect.valid && brq.io.redirect.valid 70 redirectInfo.redirect := redirect.bits 71 72 var iqInfo = new StringBuilder 73 val issueQueues = exeUnits.zipWithIndex.map({ case (eu, i) => 74 def needBypass(cfg: ExuConfig): Boolean = cfg.enableBypass 75 76 val bypassCnt = exeUnits.map(_.config).count(needBypass) 77 def needWakeup(cfg: ExuConfig): Boolean = 78 (cfg.readIntRf && cfg.writeIntRf) || (cfg.readFpRf && cfg.writeFpRf) 79 80 val wakeupCnt = exeUnits.map(_.config).count(needWakeup) 81 assert(!(needBypass(eu.config) && !needWakeup(eu.config))) // needBypass but dont needWakeup is not allowed 82 val iq = Module(new IssueQueue( 83 eu.config, 84 wakeupCnt, 85 bypassCnt, 86 eu.config.enableBypass, 87 fifo = eu.config.supportedFuncUnits.contains(FunctionUnit.lsuCfg) 88 )) 89 iq.io.redirect <> redirect 90 iq.io.numExist <> dispatch.io.numExist(i) 91 iq.io.enqCtrl <> dispatch.io.enqIQCtrl(i) 92 iq.io.enqData <> dispatch.io.enqIQData(i) 93 for( 94 (wakeUpPort, exuOut) <- 95 iq.io.wakeUpPorts.zip(exeUnits.filter(e => needWakeup(e.config)).map(_.io.out)) 96 ){ 97 wakeUpPort.bits := exuOut.bits 98 wakeUpPort.valid := exuOut.valid 99 } 100 iqInfo ++= { 101 s"[$i] ${eu.name} Queue wakeupCnt:$wakeupCnt bypassCnt:$bypassCnt" + 102 s" Supported Function:[" + 103 s"${ 104 eu.config.supportedFuncUnits.map( 105 fu => FuType.functionNameMap(fu.fuType.litValue())).mkString(", " 106 ) 107 }]\n" 108 } 109 eu.io.in <> iq.io.deq 110 eu.io.redirect <> redirect 111 iq 112 }) 113 114 val bypassQueues = issueQueues.filter(_.enableBypass) 115 val bypassUnits = exeUnits.filter(_.config.enableBypass) 116 issueQueues.foreach(iq => { 117 for (i <- iq.io.bypassUops.indices) { 118 iq.io.bypassData(i).bits := bypassUnits(i).io.out.bits 119 iq.io.bypassData(i).valid := bypassUnits(i).io.out.valid 120 } 121 iq.io.bypassUops <> bypassQueues.map(_.io.selectedUop) 122 }) 123 124 lsuExeUnits.foreach(_.io.dmem <> DontCare) // TODO 125 lsuExeUnits.foreach(_.io.mcommit <> roq.io.mcommit) 126 io.mem.mcommit := roq.io.mcommit 127 io.mem.ldin := DontCare // TODO 128 io.mem.stin := DontCare // TODO 129 130 io.frontend.redirectInfo <> redirectInfo 131 io.frontend.commits <> roq.io.commits 132 133 decode.io.in <> io.frontend.cfVec 134 brq.io.roqRedirect <> roq.io.redirect 135 brq.io.enqReqs <> decode.io.toBrq 136 for ((x, y) <- brq.io.exuRedirect.zip(exeUnits.filter(_.config.hasRedirect))) { 137 x.bits := y.io.out.bits 138 x.valid := y.io.out.fire() && y.io.out.bits.redirectValid 139 } 140 decode.io.brTags <> brq.io.brTags 141 decBuf.io.redirect <> redirect 142 decBuf.io.in <> decode.io.out 143 144 rename.io.redirect <> redirect 145 rename.io.roqCommits <> roq.io.commits 146 rename.io.in <> decBuf.io.out 147 rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) 148 rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) 149 rename.io.intPregRdy <> dispatch.io.intPregRdy 150 rename.io.fpPregRdy <> dispatch.io.fpPregRdy 151 152 dispatch.io.redirect <> redirect 153 dispatch.io.fromRename <> rename.io.out 154 155 roq.io.brqRedirect <> brq.io.redirect 156 roq.io.dp1Req <> dispatch.io.toRoq 157 dispatch.io.roqIdxs <> roq.io.roqIdxs 158 io.mem.dp1Req <> dispatch.io.toMoq 159 dispatch.io.moqIdxs <> io.mem.moqIdxs 160 161 intRf.io.readPorts <> dispatch.io.readIntRf 162 fpRf.io.readPorts <> dispatch.io.readFpRf 163 164 val exeWbReqs = exeUnits.map(_.io.out) 165 166 val wbIntIdx = exeUnits.zipWithIndex.filter(_._1.config.writeIntRf).map(_._2) 167 val wbFpIdx = exeUnits.zipWithIndex.filter(_._1.config.writeFpRf).map(_._2) 168 169 val wbu = Module(new Wbu(wbIntIdx, wbFpIdx)) 170 wbu.io.in <> exeWbReqs 171 172 val wbIntResults = wbu.io.toIntRf 173 val wbFpResults = wbu.io.toFpRf 174 175 def exuOutToRfWrite(x: Valid[ExuOutput]): RfWritePort = { 176 val rfWrite = Wire(new RfWritePort) 177 rfWrite.wen := x.valid 178 rfWrite.addr := x.bits.uop.pdest 179 rfWrite.data := x.bits.data 180 rfWrite 181 } 182 183 intRf.io.writePorts <> wbIntResults.map(exuOutToRfWrite) 184 fpRf.io.writePorts <> wbFpResults.map(exuOutToRfWrite) 185 186 rename.io.wbIntResults <> wbIntResults 187 rename.io.wbFpResults <> wbFpResults 188 189 roq.io.exeWbResults.take(exeWbReqs.length).zip(wbu.io.toRoq).foreach(x => x._1 := x._2) 190 roq.io.exeWbResults.last := brq.io.out 191 192 193 // TODO: Remove sink and source 194 val tmp = WireInit(0.U) 195 val sinks = Array[String]( 196 "DTLBFINISH", 197 "DTLBPF", 198 "DTLBENABLE", 199 "perfCntCondMdcacheLoss", 200 "perfCntCondMl2cacheLoss", 201 "perfCntCondMdcacheHit", 202 "lsuMMIO", 203 "perfCntCondMl2cacheHit", 204 "perfCntCondMl2cacheReq", 205 "mtip", 206 "perfCntCondMdcacheReq", 207 "meip" 208 ) 209 for (s <- sinks) { 210 BoringUtils.addSink(tmp, s) 211 } 212 213 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 214 BoringUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG") 215 BoringUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG") 216 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 217 if (!p.FPGAPlatform) { 218 BoringUtils.addSource(debugArchReg, "difftestRegs") 219 } 220 221 print(iqInfo) 222 223} 224