xref: /XiangShan/src/main/scala/xiangshan/backend/Backend.scala (revision 390ce3d2ae920ecb086040a1fd8b7be357ecbffb) 
1package xiangshan.backend
2
3import bus.simplebus.SimpleBusUC
4import chisel3._
5import chisel3.util._
6import chisel3.util.experimental.BoringUtils
7import noop.MemMMUIO
8import xiangshan._
9import xiangshan.backend.decode.{DecodeBuffer, DecodeStage}
10import xiangshan.backend.rename.Rename
11import xiangshan.backend.brq.Brq
12import xiangshan.backend.dispatch.Dispatch
13import xiangshan.backend.exu._
14import xiangshan.backend.fu.FunctionUnit
15import xiangshan.backend.issue.IssueQueue
16import xiangshan.backend.regfile.{Regfile, RfWritePort}
17import xiangshan.backend.roq.Roq
18import xiangshan.mem._
19
20
21/** Backend Pipeline:
22  * Decode -> Rename -> Dispatch-1 -> Dispatch-2 -> Issue -> Exe
23  */
24class Backend(implicit val p: XSConfig) extends XSModule
25  with NeedImpl {
26  val io = IO(new Bundle {
27    // val dmem = new SimpleBusUC(addrBits = VAddrBits)
28    val memMMU = Flipped(new MemMMUIO)
29    val frontend = Flipped(new FrontendToBackendIO)
30    val mem = Flipped(new MemToBackendIO)
31  })
32
33
34  val aluExeUnits = Array.tabulate(exuParameters.AluCnt)(_ => Module(new AluExeUnit))
35  val jmpExeUnit = Module(new JmpExeUnit)
36  val mulExeUnits = Array.tabulate(exuParameters.MulCnt)(_ => Module(new MulExeUnit))
37  val mduExeUnits = Array.tabulate(exuParameters.MduCnt)(_ => Module(new MulDivExeUnit))
38  //  val fmacExeUnits = Array.tabulate(exuParameters.FmacCnt)(_ => Module(new Fmac))
39  //  val fmiscExeUnits = Array.tabulate(exuParameters.FmiscCnt)(_ => Module(new Fmisc))
40  //  val fmiscDivSqrtExeUnits = Array.tabulate(exuParameters.FmiscDivSqrtCnt)(_ => Module(new FmiscDivSqrt))
41  val lsuExeUnits = Array.tabulate(exuParameters.StuCnt)(_ => Module(new LsExeUnit))
42  val exeUnits = jmpExeUnit +: (aluExeUnits ++ mulExeUnits ++ mduExeUnits ++ lsuExeUnits)
43  exeUnits.foreach(_.io.dmem := DontCare)
44  exeUnits.foreach(_.io.mcommit := DontCare)
45
46  val decode = Module(new DecodeStage)
47  val brq = Module(new Brq)
48  val decBuf = Module(new DecodeBuffer)
49  val rename = Module(new Rename)
50  val dispatch = Module(new Dispatch(exeUnits.map(_.config)))
51  val roq = Module(new Roq)
52  val intRf = Module(new Regfile(
53    numReadPorts = NRReadPorts,
54    numWirtePorts = NRWritePorts,
55    hasZero = true
56  ))
57  val fpRf = Module(new Regfile(
58    numReadPorts = NRReadPorts,
59    numWirtePorts = NRWritePorts,
60    hasZero = false
61  ))
62
63  // backend redirect, flush pipeline
64  val redirect = Mux(roq.io.redirect.valid, roq.io.redirect, brq.io.redirect)
65
66  val redirectInfo = Wire(new RedirectInfo)
67  // exception or misprediction
68  redirectInfo.valid := roq.io.redirect.valid || brq.io.out.valid
69  redirectInfo.misPred := !roq.io.redirect.valid && brq.io.redirect.valid
70  redirectInfo.redirect := redirect.bits
71
72  var iqInfo = new StringBuilder
73  val issueQueues = exeUnits.zipWithIndex.map({ case (eu, i) =>
74    def needBypass(cfg: ExuConfig): Boolean = cfg.enableBypass
75
76    val bypassCnt = exeUnits.map(_.config).count(needBypass)
77    def needWakeup(cfg: ExuConfig): Boolean =
78      (cfg.readIntRf && cfg.writeIntRf) || (cfg.readFpRf && cfg.writeFpRf)
79
80    val wakeupCnt = exeUnits.map(_.config).count(needWakeup)
81    assert(!(needBypass(eu.config) && !needWakeup(eu.config))) // needBypass but dont needWakeup is not allowed
82    val iq = Module(new IssueQueue(
83      eu.config,
84      wakeupCnt,
85      bypassCnt,
86      eu.config.enableBypass,
87      fifo = eu.config.supportedFuncUnits.contains(FunctionUnit.lsuCfg)
88    ))
89    iq.io.redirect <> redirect
90    iq.io.numExist <> dispatch.io.numExist(i)
91    iq.io.enqCtrl <> dispatch.io.enqIQCtrl(i)
92    iq.io.enqData <> dispatch.io.enqIQData(i)
93    for(
94      (wakeUpPort, exuOut) <-
95      iq.io.wakeUpPorts.zip(exeUnits.filter(e => needWakeup(e.config)).map(_.io.out))
96    ){
97      wakeUpPort.bits := exuOut.bits
98      wakeUpPort.valid := exuOut.valid
99    }
100    iqInfo ++= {
101      s"[$i] ${eu.name} Queue wakeupCnt:$wakeupCnt bypassCnt:$bypassCnt" +
102        s" Supported Function:[" +
103        s"${
104          eu.config.supportedFuncUnits.map(
105            fu => FuType.functionNameMap(fu.fuType.litValue())).mkString(", "
106          )
107        }]\n"
108    }
109    eu.io.in <> iq.io.deq
110    eu.io.redirect <> redirect
111    iq
112  })
113
114  val bypassQueues = issueQueues.filter(_.enableBypass)
115  val bypassUnits = exeUnits.filter(_.config.enableBypass)
116  issueQueues.foreach(iq => {
117    for (i <- iq.io.bypassUops.indices) {
118      iq.io.bypassData(i).bits := bypassUnits(i).io.out.bits
119      iq.io.bypassData(i).valid := bypassUnits(i).io.out.valid
120    }
121    iq.io.bypassUops <> bypassQueues.map(_.io.selectedUop)
122  })
123
124  lsuExeUnits.foreach(_.io.dmem <> DontCare) // TODO
125  lsuExeUnits.foreach(_.io.mcommit <> roq.io.mcommit)
126
127  io.frontend.redirectInfo <> redirectInfo
128  io.frontend.commits <> roq.io.commits
129
130  decode.io.in <> io.frontend.cfVec
131  brq.io.roqRedirect <> roq.io.redirect
132  brq.io.enqReqs <> decode.io.toBrq
133  for ((x, y) <- brq.io.exuRedirect.zip(exeUnits.filter(_.config.hasRedirect))) {
134    x.bits := y.io.out.bits
135    x.valid := y.io.out.fire() && y.io.out.bits.redirectValid
136  }
137  decode.io.brTags <> brq.io.brTags
138  decBuf.io.redirect <> redirect
139  decBuf.io.in <> decode.io.out
140
141  rename.io.redirect <> redirect
142  rename.io.roqCommits <> roq.io.commits
143  rename.io.in <> decBuf.io.out
144  rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr)
145  rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr)
146  rename.io.intPregRdy <> dispatch.io.intPregRdy
147  rename.io.fpPregRdy <> dispatch.io.fpPregRdy
148
149  dispatch.io.redirect <> redirect
150  dispatch.io.fromRename <> rename.io.out
151
152  roq.io.brqRedirect <> brq.io.redirect
153  roq.io.dp1Req <> dispatch.io.toRoq
154  dispatch.io.roqIdxs <> roq.io.roqIdxs
155
156  intRf.io.readPorts <> dispatch.io.readIntRf
157  fpRf.io.readPorts <> dispatch.io.readFpRf
158
159  val exeWbReqs = exeUnits.map(_.io.out)
160
161  val wbIntIdx = exeUnits.zipWithIndex.filter(_._1.config.writeIntRf).map(_._2)
162  val wbFpIdx = exeUnits.zipWithIndex.filter(_._1.config.writeFpRf).map(_._2)
163
164  val wbu = Module(new Wbu(wbIntIdx, wbFpIdx))
165  wbu.io.in <> exeWbReqs
166
167  val wbIntResults = wbu.io.toIntRf
168  val wbFpResults = wbu.io.toFpRf
169
170  def exuOutToRfWrite(x: Valid[ExuOutput]): RfWritePort = {
171    val rfWrite = Wire(new RfWritePort)
172    rfWrite.wen := x.valid
173    rfWrite.addr := x.bits.uop.pdest
174    rfWrite.data := x.bits.data
175    rfWrite
176  }
177
178  intRf.io.writePorts <> wbIntResults.map(exuOutToRfWrite)
179  fpRf.io.writePorts <> wbFpResults.map(exuOutToRfWrite)
180
181  rename.io.wbIntResults <> wbIntResults
182  rename.io.wbFpResults <> wbFpResults
183
184  roq.io.exeWbResults.take(exeWbReqs.length).zip(wbu.io.toRoq).foreach(x => x._1 := x._2)
185  roq.io.exeWbResults.last := brq.io.out
186
187
188  // TODO: Remove sink and source
189  val tmp = WireInit(0.U)
190  val sinks = Array[String](
191    "DTLBFINISH",
192    "DTLBPF",
193    "DTLBENABLE",
194    "perfCntCondMdcacheLoss",
195    "perfCntCondMl2cacheLoss",
196    "perfCntCondMdcacheHit",
197    "lsuMMIO",
198    "perfCntCondMl2cacheHit",
199    "perfCntCondMl2cacheReq",
200    "mtip",
201    "perfCntCondMdcacheReq",
202    "meip"
203  )
204  for (s <- sinks) {
205    BoringUtils.addSink(tmp, s)
206  }
207
208  val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
209  BoringUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG")
210  BoringUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG")
211  val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
212  if (!p.FPGAPlatform) {
213    BoringUtils.addSource(debugArchReg, "difftestRegs")
214  }
215
216  print(iqInfo)
217
218}
219