| #
d61cd5ee |
| 06-Sep-2023 |
peixiaokun <[email protected]> |
RVH: fix some syntax problems
|
| #
d0de7e4a |
| 26-Aug-2023 |
peixiaokun <[email protected]> |
RVH: finish the desigh of H extention
|
| #
f57f7f2a |
| 10-Apr-2024 |
Yangyu Chen <[email protected]> |
Configs: correct MaxHartIdBits (#2838)
Currently, many different lengths of HartId in Xiangshan, making it hard to
configure it to scale more than 16 cores since we have set 4bits somewhere.
This
Configs: correct MaxHartIdBits (#2838)
Currently, many different lengths of HartId in Xiangshan, making it hard to
configure it to scale more than 16 cores since we have set 4bits somewhere.
This commit corrects MaxHartIdBits in config and uses MaxHartIDBits where
it needs to get this solved.
Signed-off-by: Yangyu Chen <[email protected]>
show more ...
|
| #
00e6f2e2 |
| 27-Feb-2024 |
weiding liu <[email protected]> |
rv64v: add suport of 128-bit vector elements load/store
|
| #
1d260098 |
| 18-Mar-2024 |
Xuan Hu <[email protected]> |
fix merge error
|
| #
b9ef0a42 |
| 18-Mar-2024 |
Xuan Hu <[email protected]> |
Merge remote-tracking branch 'upstream/master' into tmp-backend-merge-fixtiming
|
| #
fc605fcf |
| 20-Mar-2024 |
sinsanction <[email protected]> |
Parameters: fix the count of vector read ports
|
| #
34f9ccd0 |
| 18-Mar-2024 |
Ziyue Zhang <[email protected]> |
float: use VCVT module for all fcvt instructions
Co-authored-by: chengguanghui <[email protected]>
|
| #
f5446151 |
| 15-Mar-2024 |
sinsanction <[email protected]> |
Parameters: refactor vfSchdParams
|
| #
918d87f2 |
| 15-Mar-2024 |
sinceforYy <[email protected]> |
Parameter: add Fu EnableClockGate
|
| #
6ccce570 |
| 14-Mar-2024 |
zhanglyGit <[email protected]> |
Backend: rm one brh fu and modify Dispatch to adpot to it
|
| #
7556e9bd |
| 09-Mar-2024 |
xiaofeibao-xjtu <[email protected]> |
IssueQueue: Alu,Mul,Bku in same exeUnit for wakeup others
|
| #
2142592b |
| 08-Mar-2024 |
xiaofeibao-xjtu <[email protected]> |
MemBlock: 3ld2st
|
| #
5edcc45f |
| 08-Mar-2024 |
Haojin Tang <[email protected]> |
Parameters: remove write port configs for store
|
| #
983f9a4c |
| 08-Mar-2024 |
Ziyue Zhang <[email protected]> |
rv64v: add i2vcfg
|
| #
202674ae |
| 04-Mar-2024 |
Haojin Tang <[email protected]> |
MemBlock: support 3ld3st
|
| #
0438e8f4 |
| 04-Mar-2024 |
Haojin Tang <[email protected]> |
MemBlock: support 3ld2st
|
| #
3aa87019 |
| 01-Mar-2024 |
zhanglyGit <[email protected]> |
Parameters: HYU use read port 14
|
| #
6c7f64dc |
| 23-Feb-2024 |
zhanglyGit <[email protected]> |
Backend: fix the wrong order of LDU and HYU's wakeup and ldcancel from MemBlock
|
| #
47c01b71 |
| 11-Jan-2024 |
xiaofeibao-xjtu <[email protected]> |
ctrlblock: timing optimize of wb counter to rob
|
| #
6fa1007b |
| 10-Jan-2024 |
xiaofeibao-xjtu <[email protected]> |
wakeup: add mul wakeup
|
| #
c1e19666 |
| 04-Jan-2024 |
xiaofeibao-xjtu <[email protected]> |
backend: implement uncertain latency exeUnit WbArbiter
|
| #
9c890e56 |
| 18-Feb-2024 |
Xuan Hu <[email protected]> |
Backend: fix the wbconfig check
* There is no need to limit the WB priority of certain latency exu.
|
| #
ff3fcdf1 |
| 15-Dec-2023 |
xiaofeibao-xjtu <[email protected]> |
Dispatch: split int dispatch to two regions
|
| #
28607074 |
| 26-Dec-2023 |
sinsanction <[email protected]> |
IssueQueue: add Simple to Complex transfer policy & support all Complex/Simple entry config
|