1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams, FakeIntPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.min 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HasMExtension: Boolean = true, 63 HasCExtension: Boolean = true, 64 HasDiv: Boolean = true, 65 HasICache: Boolean = true, 66 HasDCache: Boolean = true, 67 AddrBits: Int = 64, 68 VAddrBits: Int = 39, 69 HasFPU: Boolean = true, 70 HasVPU: Boolean = true, 71 HasCustomCSRCacheOp: Boolean = true, 72 FetchWidth: Int = 8, 73 AsidLength: Int = 16, 74 EnableBPU: Boolean = true, 75 EnableBPD: Boolean = true, 76 EnableRAS: Boolean = true, 77 EnableLB: Boolean = false, 78 EnableLoop: Boolean = true, 79 EnableSC: Boolean = true, 80 EnbaleTlbDebug: Boolean = false, 81 EnableClockGate: Boolean = true, 82 EnableJal: Boolean = false, 83 EnableFauFTB: Boolean = true, 84 UbtbGHRLength: Int = 4, 85 // HistoryLength: Int = 512, 86 EnableGHistDiff: Boolean = true, 87 EnableCommitGHistDiff: Boolean = true, 88 UbtbSize: Int = 256, 89 FtbSize: Int = 2048, 90 RasSize: Int = 16, 91 RasSpecSize: Int = 32, 92 RasCtrSize: Int = 3, 93 CacheLineSize: Int = 512, 94 FtbWays: Int = 4, 95 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 96 // Sets Hist Tag 97 // Seq(( 2048, 2, 8), 98 // ( 2048, 9, 8), 99 // ( 2048, 13, 8), 100 // ( 2048, 20, 8), 101 // ( 2048, 26, 8), 102 // ( 2048, 44, 8), 103 // ( 2048, 73, 8), 104 // ( 2048, 256, 8)), 105 Seq(( 4096, 8, 8), 106 ( 4096, 13, 8), 107 ( 4096, 32, 8), 108 ( 4096, 119, 8)), 109 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 110 // Sets Hist Tag 111 Seq(( 256, 4, 9), 112 ( 256, 8, 9), 113 ( 512, 13, 9), 114 ( 512, 16, 9), 115 ( 512, 32, 9)), 116 SCNRows: Int = 512, 117 SCNTables: Int = 4, 118 SCCtrBits: Int = 6, 119 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 120 numBr: Int = 2, 121 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 122 ((resp_in: BranchPredictionResp, p: Parameters) => { 123 val ftb = Module(new FTB()(p)) 124 val ubtb =Module(new FauFTB()(p)) 125 // val bim = Module(new BIM()(p)) 126 val tage = Module(new Tage_SC()(p)) 127 val ras = Module(new RAS()(p)) 128 val ittage = Module(new ITTage()(p)) 129 val preds = Seq(ubtb, tage, ftb, ittage, ras) 130 preds.map(_.io := DontCare) 131 132 // ubtb.io.resp_in(0) := resp_in 133 // bim.io.resp_in(0) := ubtb.io.resp 134 // btb.io.resp_in(0) := bim.io.resp 135 // tage.io.resp_in(0) := btb.io.resp 136 // loop.io.resp_in(0) := tage.io.resp 137 ubtb.io.in.bits.resp_in(0) := resp_in 138 tage.io.in.bits.resp_in(0) := ubtb.io.out 139 ftb.io.in.bits.resp_in(0) := tage.io.out 140 ittage.io.in.bits.resp_in(0) := ftb.io.out 141 ras.io.in.bits.resp_in(0) := ittage.io.out 142 143 (preds, ras.io.out) 144 }), 145 ICacheECCForceError: Boolean = false, 146 IBufSize: Int = 48, 147 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 148 DecodeWidth: Int = 6, 149 RenameWidth: Int = 6, 150 CommitWidth: Int = 6, 151 MaxUopSize: Int = 65, 152 EnableRenameSnapshot: Boolean = true, 153 RenameSnapshotNum: Int = 4, 154 FtqSize: Int = 64, 155 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 156 IntLogicRegs: Int = 32, 157 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 158 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 159 VCONFIG_IDX: Int = 32, 160 NRPhyRegs: Int = 192, 161 VirtualLoadQueueSize: Int = 72, 162 LoadQueueRARSize: Int = 72, 163 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 164 RollbackGroupSize: Int = 8, 165 LoadQueueReplaySize: Int = 72, 166 LoadUncacheBufferSize: Int = 20, 167 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 168 StoreQueueSize: Int = 64, 169 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 170 StoreQueueForwardWithMask: Boolean = true, 171 VlsQueueSize: Int = 8, 172 RobSize: Int = 160, 173 RabSize: Int = 256, 174 VTypeBufferSize: Int = 64, // used to reorder vtype 175 IssueQueueSize: Int = 24, 176 IssueQueueCompEntrySize: Int = 16, 177 dpParams: DispatchParameters = DispatchParameters( 178 IntDqSize = 16, 179 FpDqSize = 16, 180 LsDqSize = 18, 181 IntDqDeqWidth = 8, 182 FpDqDeqWidth = 6, 183 LsDqDeqWidth = 6, 184 ), 185 intPreg: PregParams = IntPregParams( 186 numEntries = 224, 187 numRead = None, 188 numWrite = None, 189 ), 190 vfPreg: VfPregParams = VfPregParams( 191 numEntries = 192, 192 numRead = Some(14), 193 numWrite = None, 194 ), 195 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 196 LoadPipelineWidth: Int = 3, 197 StorePipelineWidth: Int = 2, 198 VecLoadPipelineWidth: Int = 2, 199 VecStorePipelineWidth: Int = 2, 200 VecMemSrcInWidth: Int = 2, 201 VecMemInstWbWidth: Int = 1, 202 VecMemDispatchWidth: Int = 1, 203 StoreBufferSize: Int = 16, 204 StoreBufferThreshold: Int = 7, 205 EnsbufferWidth: Int = 2, 206 // ============ VLSU ============ 207 UsQueueSize: Int = 8, 208 VlFlowSize: Int = 32, 209 VlUopSize: Int = 32, 210 VsFlowL1Size: Int = 128, 211 VsFlowL2Size: Int = 32, 212 VsUopSize: Int = 32, 213 // ============================== 214 UncacheBufferSize: Int = 4, 215 EnableLoadToLoadForward: Boolean = false, 216 EnableFastForward: Boolean = true, 217 EnableLdVioCheckAfterReset: Boolean = true, 218 EnableSoftPrefetchAfterReset: Boolean = true, 219 EnableCacheErrorAfterReset: Boolean = true, 220 EnableAccurateLoadError: Boolean = true, 221 EnableUncacheWriteOutstanding: Boolean = false, 222 EnableStorePrefetchAtIssue: Boolean = false, 223 EnableStorePrefetchAtCommit: Boolean = false, 224 EnableAtCommitMissTrigger: Boolean = true, 225 EnableStorePrefetchSMS: Boolean = false, 226 EnableStorePrefetchSPB: Boolean = false, 227 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 228 ReSelectLen: Int = 7, // load replay queue replay select counter len 229 iwpuParameters: WPUParameters = WPUParameters( 230 enWPU = false, 231 algoName = "mmru", 232 isICache = true, 233 ), 234 dwpuParameters: WPUParameters = WPUParameters( 235 enWPU = false, 236 algoName = "mmru", 237 enCfPred = false, 238 isICache = false, 239 ), 240 itlbParameters: TLBParameters = TLBParameters( 241 name = "itlb", 242 fetchi = true, 243 useDmode = false, 244 NWays = 48, 245 ), 246 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 247 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 248 ldtlbParameters: TLBParameters = TLBParameters( 249 name = "ldtlb", 250 NWays = 48, 251 outReplace = false, 252 partialStaticPMP = true, 253 outsideRecvFlush = true, 254 saveLevel = true 255 ), 256 sttlbParameters: TLBParameters = TLBParameters( 257 name = "sttlb", 258 NWays = 48, 259 outReplace = false, 260 partialStaticPMP = true, 261 outsideRecvFlush = true, 262 saveLevel = true 263 ), 264 hytlbParameters: TLBParameters = TLBParameters( 265 name = "hytlb", 266 NWays = 48, 267 outReplace = false, 268 partialStaticPMP = true, 269 outsideRecvFlush = true, 270 saveLevel = true 271 ), 272 pftlbParameters: TLBParameters = TLBParameters( 273 name = "pftlb", 274 NWays = 48, 275 outReplace = false, 276 partialStaticPMP = true, 277 outsideRecvFlush = true, 278 saveLevel = true 279 ), 280 refillBothTlb: Boolean = false, 281 btlbParameters: TLBParameters = TLBParameters( 282 name = "btlb", 283 NWays = 48, 284 ), 285 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 286 NumPerfCounters: Int = 16, 287 icacheParameters: ICacheParameters = ICacheParameters( 288 tagECC = Some("parity"), 289 dataECC = Some("parity"), 290 replacer = Some("setplru"), 291 nMissEntries = 2, 292 nProbeEntries = 2, 293 nPrefetchEntries = 12, 294 nPrefBufferEntries = 32, 295 ), 296 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 297 tagECC = Some("secded"), 298 dataECC = Some("secded"), 299 replacer = Some("setplru"), 300 nMissEntries = 16, 301 nProbeEntries = 8, 302 nReleaseEntries = 18, 303 nMaxPrefetchEntry = 6, 304 )), 305 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 306 name = "l2", 307 ways = 8, 308 sets = 1024, // default 512KB L2 309 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 310 )), 311 L2NBanks: Int = 1, 312 usePTWRepeater: Boolean = false, 313 softTLB: Boolean = false, // dpi-c l1tlb debug only 314 softPTW: Boolean = false, // dpi-c l2tlb debug only 315 softPTWDelay: Int = 1 316){ 317 def vlWidth = log2Up(VLEN) + 1 318 319 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 320 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 321 322 val intSchdParams = { 323 implicit val schdType: SchedulerType = IntScheduler() 324 SchdBlockParams(Seq( 325 IssueBlockParams(Seq( 326 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 327 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(7, 1))), true, 2), 328 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 329 IssueBlockParams(Seq( 330 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 331 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 2, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(5, 1))), true, 2), 332 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 333 IssueBlockParams(Seq( 334 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 335 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 3, 1), VfWB(4, 0)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(3, 1)))), 336 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 337 IssueBlockParams(Seq( 338 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 339 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(1, 1)))), 340 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 341 ), 342 numPregs = intPreg.numEntries, 343 numDeqOutside = 0, 344 schdType = schdType, 345 rfDataWidth = intPreg.dataCfg.dataWidth, 346 numUopIn = dpParams.IntDqDeqWidth, 347 ) 348 } 349 val vfSchdParams = { 350 implicit val schdType: SchedulerType = VfScheduler() 351 SchdBlockParams(Seq( 352 IssueBlockParams(Seq( 353 ExeUnitParams("VFEX0", Seq(VfaluCfg, VfmaCfg, VialuCfg, VppuCfg, F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 0), IntWB(port = 0, 1)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 354 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 355 IssueBlockParams(Seq( 356 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfmaCfg, VimacCfg, VipuCfg, F2vCfg, VfcvtCfg), Seq(VfWB(port = 1, 0), IntWB(port = 1, 1)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 357 ExeUnitParams("VFEX2", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 2, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 358 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 359 ), 360 numPregs = vfPreg.numEntries, 361 numDeqOutside = 0, 362 schdType = schdType, 363 rfDataWidth = vfPreg.dataCfg.dataWidth, 364 numUopIn = dpParams.FpDqDeqWidth, 365 ) 366 } 367 368 val memSchdParams = { 369 implicit val schdType: SchedulerType = MemScheduler() 370 val rfDataWidth = 64 371 372 SchdBlockParams(Seq( 373 IssueBlockParams(Seq( 374 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(15, 0)))), 375 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 376 IssueBlockParams(Seq( 377 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(13, 1)))), 378 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 379 IssueBlockParams(Seq( 380 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), VfWB(5, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 381 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 382 IssueBlockParams(Seq( 383 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(6, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 384 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 385 IssueBlockParams(Seq( 386 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(7, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 387 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 388 IssueBlockParams(Seq( 389 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(3, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 390 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 391 IssueBlockParams(Seq( 392 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(12, 1), VfRD(6, 0)))), 393 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 394 IssueBlockParams(Seq( 395 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(14, 1), VfRD(10, Int.MaxValue)))), 396 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 397 ), 398 numPregs = intPreg.numEntries max vfPreg.numEntries, 399 numDeqOutside = 0, 400 schdType = schdType, 401 rfDataWidth = rfDataWidth, 402 numUopIn = dpParams.LsDqDeqWidth, 403 ) 404 } 405 406 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 407 408 def iqWakeUpParams = { 409 Seq( 410 WakeUpConfig( 411 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 412 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 413 ), 414 ).flatten 415 } 416 417 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 418 419 val backendParams: BackendParams = backend.BackendParams( 420 Map( 421 IntScheduler() -> intSchdParams, 422 VfScheduler() -> vfSchdParams, 423 MemScheduler() -> memSchdParams, 424 ), 425 Seq( 426 intPreg, 427 vfPreg, 428 fakeIntPreg 429 ), 430 iqWakeUpParams, 431 ) 432} 433 434case object DebugOptionsKey extends Field[DebugOptions] 435 436case class DebugOptions 437( 438 FPGAPlatform: Boolean = false, 439 EnableDifftest: Boolean = false, 440 AlwaysBasicDiff: Boolean = true, 441 EnableDebug: Boolean = false, 442 EnablePerfDebug: Boolean = true, 443 UseDRAMSim: Boolean = false, 444 EnableConstantin: Boolean = false, 445 EnableChiselDB: Boolean = false, 446 AlwaysBasicDB: Boolean = true, 447 EnableTopDown: Boolean = false, 448 EnableRollingDB: Boolean = false 449) 450 451trait HasXSParameter { 452 453 implicit val p: Parameters 454 455 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 456 457 val coreParams = p(XSCoreParamsKey) 458 val env = p(DebugOptionsKey) 459 460 val XLEN = coreParams.XLEN 461 val VLEN = coreParams.VLEN 462 val ELEN = coreParams.ELEN 463 val minFLen = 32 464 val fLen = 64 465 def xLen = XLEN 466 467 val HasMExtension = coreParams.HasMExtension 468 val HasCExtension = coreParams.HasCExtension 469 val HasDiv = coreParams.HasDiv 470 val HasIcache = coreParams.HasICache 471 val HasDcache = coreParams.HasDCache 472 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 473 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 474 val AsidLength = coreParams.AsidLength 475 val ReSelectLen = coreParams.ReSelectLen 476 val AddrBytes = AddrBits / 8 // unused 477 val DataBits = XLEN 478 val DataBytes = DataBits / 8 479 val VDataBytes = VLEN / 8 480 val HasFPU = coreParams.HasFPU 481 val HasVPU = coreParams.HasVPU 482 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 483 val FetchWidth = coreParams.FetchWidth 484 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 485 val EnableBPU = coreParams.EnableBPU 486 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 487 val EnableRAS = coreParams.EnableRAS 488 val EnableLB = coreParams.EnableLB 489 val EnableLoop = coreParams.EnableLoop 490 val EnableSC = coreParams.EnableSC 491 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 492 val HistoryLength = coreParams.HistoryLength 493 val EnableGHistDiff = coreParams.EnableGHistDiff 494 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 495 val EnableClockGate = coreParams.EnableClockGate 496 val UbtbGHRLength = coreParams.UbtbGHRLength 497 val UbtbSize = coreParams.UbtbSize 498 val EnableFauFTB = coreParams.EnableFauFTB 499 val FtbSize = coreParams.FtbSize 500 val FtbWays = coreParams.FtbWays 501 val RasSize = coreParams.RasSize 502 val RasSpecSize = coreParams.RasSpecSize 503 val RasCtrSize = coreParams.RasCtrSize 504 505 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 506 coreParams.branchPredictor(resp_in, p) 507 } 508 val numBr = coreParams.numBr 509 val TageTableInfos = coreParams.TageTableInfos 510 val TageBanks = coreParams.numBr 511 val SCNRows = coreParams.SCNRows 512 val SCCtrBits = coreParams.SCCtrBits 513 val SCHistLens = coreParams.SCHistLens 514 val SCNTables = coreParams.SCNTables 515 516 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 517 case ((n, cb), h) => (n, cb, h) 518 } 519 val ITTageTableInfos = coreParams.ITTageTableInfos 520 type FoldedHistoryInfo = Tuple2[Int, Int] 521 val foldedGHistInfos = 522 (TageTableInfos.map{ case (nRows, h, t) => 523 if (h > 0) 524 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 525 else 526 Set[FoldedHistoryInfo]() 527 }.reduce(_++_).toSet ++ 528 SCTableInfos.map{ case (nRows, _, h) => 529 if (h > 0) 530 Set((h, min(log2Ceil(nRows/TageBanks), h))) 531 else 532 Set[FoldedHistoryInfo]() 533 }.reduce(_++_).toSet ++ 534 ITTageTableInfos.map{ case (nRows, h, t) => 535 if (h > 0) 536 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 537 else 538 Set[FoldedHistoryInfo]() 539 }.reduce(_++_) ++ 540 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 541 ).toList 542 543 544 545 val CacheLineSize = coreParams.CacheLineSize 546 val CacheLineHalfWord = CacheLineSize / 16 547 val ExtHistoryLength = HistoryLength + 64 548 val ICacheECCForceError = coreParams.ICacheECCForceError 549 val IBufSize = coreParams.IBufSize 550 val IBufNBank = coreParams.IBufNBank 551 val backendParams: BackendParams = coreParams.backendParams 552 val DecodeWidth = coreParams.DecodeWidth 553 val RenameWidth = coreParams.RenameWidth 554 val CommitWidth = coreParams.CommitWidth 555 val MaxUopSize = coreParams.MaxUopSize 556 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 557 val RenameSnapshotNum = coreParams.RenameSnapshotNum 558 val FtqSize = coreParams.FtqSize 559 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 560 val IntLogicRegs = coreParams.IntLogicRegs 561 val FpLogicRegs = coreParams.FpLogicRegs 562 val VecLogicRegs = coreParams.VecLogicRegs 563 val VCONFIG_IDX = coreParams.VCONFIG_IDX 564 val IntPhyRegs = coreParams.intPreg.numEntries 565 val VfPhyRegs = coreParams.vfPreg.numEntries 566 val MaxPhyPregs = IntPhyRegs max VfPhyRegs 567 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 568 val RobSize = coreParams.RobSize 569 val RabSize = coreParams.RabSize 570 val VTypeBufferSize = coreParams.VTypeBufferSize 571 val IntRefCounterWidth = log2Ceil(RobSize) 572 val LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 573 val LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 574 val LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 575 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 576 val LoadQueueRARSize = coreParams.LoadQueueRARSize 577 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 578 val RollbackGroupSize = coreParams.RollbackGroupSize 579 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 580 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 581 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 582 val StoreQueueSize = coreParams.StoreQueueSize 583 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 584 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 585 val VlsQueueSize = coreParams.VlsQueueSize 586 val dpParams = coreParams.dpParams 587 588 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 589 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 590 591 val NumRedirect = backendParams.numRedirect 592 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 593 val FtqRedirectAheadNum = NumRedirect 594 val LoadPipelineWidth = coreParams.LoadPipelineWidth 595 val StorePipelineWidth = coreParams.StorePipelineWidth 596 val VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 597 val VecStorePipelineWidth = coreParams.VecStorePipelineWidth 598 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 599 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 600 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 601 val StoreBufferSize = coreParams.StoreBufferSize 602 val StoreBufferThreshold = coreParams.StoreBufferThreshold 603 val EnsbufferWidth = coreParams.EnsbufferWidth 604 val UsQueueSize = coreParams.UsQueueSize 605 val VlFlowSize = coreParams.VlFlowSize 606 val VlUopSize = coreParams.VlUopSize 607 val VsFlowL1Size = coreParams.VsFlowL1Size 608 val VsFlowL2Size = coreParams.VsFlowL2Size 609 val VsUopSize = coreParams.VsUopSize 610 val UncacheBufferSize = coreParams.UncacheBufferSize 611 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 612 val EnableFastForward = coreParams.EnableFastForward 613 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 614 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 615 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 616 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 617 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 618 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 619 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 620 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 621 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 622 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 623 val asidLen = coreParams.MMUAsidLen 624 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 625 val refillBothTlb = coreParams.refillBothTlb 626 val iwpuParam = coreParams.iwpuParameters 627 val dwpuParam = coreParams.dwpuParameters 628 val itlbParams = coreParams.itlbParameters 629 val ldtlbParams = coreParams.ldtlbParameters 630 val sttlbParams = coreParams.sttlbParameters 631 val hytlbParams = coreParams.hytlbParameters 632 val pftlbParams = coreParams.pftlbParameters 633 val btlbParams = coreParams.btlbParameters 634 val l2tlbParams = coreParams.l2tlbParameters 635 val NumPerfCounters = coreParams.NumPerfCounters 636 637 val instBytes = if (HasCExtension) 2 else 4 638 val instOffsetBits = log2Ceil(instBytes) 639 640 val icacheParameters = coreParams.icacheParameters 641 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 642 643 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 644 // for constrained LR/SC loop 645 val LRSCCycles = 64 646 // for lr storm 647 val LRSCBackOff = 8 648 649 // cache hierarchy configurations 650 val l1BusDataWidth = 256 651 652 // load violation predict 653 val ResetTimeMax2Pow = 20 //1078576 654 val ResetTimeMin2Pow = 10 //1024 655 // wait table parameters 656 val WaitTableSize = 1024 657 val MemPredPCWidth = log2Up(WaitTableSize) 658 val LWTUse2BitCounter = true 659 // store set parameters 660 val SSITSize = WaitTableSize 661 val LFSTSize = 32 662 val SSIDWidth = log2Up(LFSTSize) 663 val LFSTWidth = 4 664 val StoreSetEnable = true // LWT will be disabled if SS is enabled 665 val LFSTEnable = true 666 667 val PCntIncrStep: Int = 6 668 val numPCntHc: Int = 25 669 val numPCntPtw: Int = 19 670 671 val numCSRPCntFrontend = 8 672 val numCSRPCntCtrl = 8 673 val numCSRPCntLsu = 8 674 val numCSRPCntHc = 5 675 val printEventCoding = true 676 677 // Parameters for Sdtrig extension 678 protected val TriggerNum = 4 679 protected val TriggerChainMaxLength = 2 680} 681