1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.min 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HasMExtension: Boolean = true, 63 HasCExtension: Boolean = true, 64 HasDiv: Boolean = true, 65 HasICache: Boolean = true, 66 HasDCache: Boolean = true, 67 AddrBits: Int = 64, 68 VAddrBits: Int = 39, 69 HasFPU: Boolean = true, 70 HasVPU: Boolean = true, 71 HasCustomCSRCacheOp: Boolean = true, 72 FetchWidth: Int = 8, 73 AsidLength: Int = 16, 74 EnableBPU: Boolean = true, 75 EnableBPD: Boolean = true, 76 EnableRAS: Boolean = true, 77 EnableLB: Boolean = false, 78 EnableLoop: Boolean = true, 79 EnableSC: Boolean = true, 80 EnbaleTlbDebug: Boolean = false, 81 EnableJal: Boolean = false, 82 EnableFauFTB: Boolean = true, 83 UbtbGHRLength: Int = 4, 84 // HistoryLength: Int = 512, 85 EnableGHistDiff: Boolean = true, 86 EnableCommitGHistDiff: Boolean = true, 87 UbtbSize: Int = 256, 88 FtbSize: Int = 2048, 89 RasSize: Int = 16, 90 RasSpecSize: Int = 32, 91 RasCtrSize: Int = 3, 92 CacheLineSize: Int = 512, 93 FtbWays: Int = 4, 94 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 95 // Sets Hist Tag 96 // Seq(( 2048, 2, 8), 97 // ( 2048, 9, 8), 98 // ( 2048, 13, 8), 99 // ( 2048, 20, 8), 100 // ( 2048, 26, 8), 101 // ( 2048, 44, 8), 102 // ( 2048, 73, 8), 103 // ( 2048, 256, 8)), 104 Seq(( 4096, 8, 8), 105 ( 4096, 13, 8), 106 ( 4096, 32, 8), 107 ( 4096, 119, 8)), 108 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 109 // Sets Hist Tag 110 Seq(( 256, 4, 9), 111 ( 256, 8, 9), 112 ( 512, 13, 9), 113 ( 512, 16, 9), 114 ( 512, 32, 9)), 115 SCNRows: Int = 512, 116 SCNTables: Int = 4, 117 SCCtrBits: Int = 6, 118 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 119 numBr: Int = 2, 120 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 121 ((resp_in: BranchPredictionResp, p: Parameters) => { 122 val ftb = Module(new FTB()(p)) 123 val ubtb =Module(new FauFTB()(p)) 124 // val bim = Module(new BIM()(p)) 125 val tage = Module(new Tage_SC()(p)) 126 val ras = Module(new RAS()(p)) 127 val ittage = Module(new ITTage()(p)) 128 val preds = Seq(ubtb, tage, ftb, ittage, ras) 129 preds.map(_.io := DontCare) 130 131 // ubtb.io.resp_in(0) := resp_in 132 // bim.io.resp_in(0) := ubtb.io.resp 133 // btb.io.resp_in(0) := bim.io.resp 134 // tage.io.resp_in(0) := btb.io.resp 135 // loop.io.resp_in(0) := tage.io.resp 136 ubtb.io.in.bits.resp_in(0) := resp_in 137 tage.io.in.bits.resp_in(0) := ubtb.io.out 138 ftb.io.in.bits.resp_in(0) := tage.io.out 139 ittage.io.in.bits.resp_in(0) := ftb.io.out 140 ras.io.in.bits.resp_in(0) := ittage.io.out 141 142 (preds, ras.io.out) 143 }), 144 ICacheECCForceError: Boolean = false, 145 IBufSize: Int = 48, 146 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 147 DecodeWidth: Int = 6, 148 RenameWidth: Int = 6, 149 CommitWidth: Int = 6, 150 MaxUopSize: Int = 65, 151 EnableRenameSnapshot: Boolean = true, 152 RenameSnapshotNum: Int = 4, 153 FtqSize: Int = 64, 154 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 155 IntLogicRegs: Int = 32, 156 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 157 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 158 VCONFIG_IDX: Int = 32, 159 NRPhyRegs: Int = 192, 160 VirtualLoadQueueSize: Int = 72, 161 LoadQueueRARSize: Int = 72, 162 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 163 RollbackGroupSize: Int = 8, 164 LoadQueueReplaySize: Int = 72, 165 LoadUncacheBufferSize: Int = 20, 166 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 167 StoreQueueSize: Int = 64, 168 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 169 StoreQueueForwardWithMask: Boolean = true, 170 VlsQueueSize: Int = 8, 171 RobSize: Int = 160, 172 RabSize: Int = 256, 173 VTypeBufferSize: Int = 64, // used to reorder vtype 174 IssueQueueSize: Int = 24, 175 IssueQueueCompEntrySize: Int = 16, 176 dpParams: DispatchParameters = DispatchParameters( 177 IntDqSize = 16, 178 FpDqSize = 16, 179 LsDqSize = 18, 180 IntDqDeqWidth = 6, 181 FpDqDeqWidth = 6, 182 LsDqDeqWidth = 6, 183 ), 184 intPreg: PregParams = IntPregParams( 185 numEntries = 224, 186 numRead = None, 187 numWrite = None, 188 ), 189 vfPreg: VfPregParams = VfPregParams( 190 numEntries = 192, 191 numRead = Some(14), 192 numWrite = None, 193 ), 194 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 195 LoadPipelineWidth: Int = 3, 196 StorePipelineWidth: Int = 2, 197 VecLoadPipelineWidth: Int = 2, 198 VecStorePipelineWidth: Int = 2, 199 VecMemSrcInWidth: Int = 2, 200 VecMemInstWbWidth: Int = 1, 201 VecMemDispatchWidth: Int = 1, 202 StoreBufferSize: Int = 16, 203 StoreBufferThreshold: Int = 7, 204 EnsbufferWidth: Int = 2, 205 // ============ VLSU ============ 206 UsQueueSize: Int = 8, 207 VlFlowSize: Int = 32, 208 VlUopSize: Int = 32, 209 VsFlowL1Size: Int = 128, 210 VsFlowL2Size: Int = 32, 211 VsUopSize: Int = 32, 212 // ============================== 213 UncacheBufferSize: Int = 4, 214 EnableLoadToLoadForward: Boolean = false, 215 EnableFastForward: Boolean = true, 216 EnableLdVioCheckAfterReset: Boolean = true, 217 EnableSoftPrefetchAfterReset: Boolean = true, 218 EnableCacheErrorAfterReset: Boolean = true, 219 EnableAccurateLoadError: Boolean = true, 220 EnableUncacheWriteOutstanding: Boolean = false, 221 EnableStorePrefetchAtIssue: Boolean = false, 222 EnableStorePrefetchAtCommit: Boolean = false, 223 EnableAtCommitMissTrigger: Boolean = true, 224 EnableStorePrefetchSMS: Boolean = false, 225 EnableStorePrefetchSPB: Boolean = false, 226 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 227 ReSelectLen: Int = 7, // load replay queue replay select counter len 228 iwpuParameters: WPUParameters = WPUParameters( 229 enWPU = false, 230 algoName = "mmru", 231 isICache = true, 232 ), 233 dwpuParameters: WPUParameters = WPUParameters( 234 enWPU = false, 235 algoName = "mmru", 236 enCfPred = false, 237 isICache = false, 238 ), 239 itlbParameters: TLBParameters = TLBParameters( 240 name = "itlb", 241 fetchi = true, 242 useDmode = false, 243 NWays = 48, 244 ), 245 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 246 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 247 ldtlbParameters: TLBParameters = TLBParameters( 248 name = "ldtlb", 249 NWays = 48, 250 outReplace = false, 251 partialStaticPMP = true, 252 outsideRecvFlush = true, 253 saveLevel = true 254 ), 255 sttlbParameters: TLBParameters = TLBParameters( 256 name = "sttlb", 257 NWays = 48, 258 outReplace = false, 259 partialStaticPMP = true, 260 outsideRecvFlush = true, 261 saveLevel = true 262 ), 263 hytlbParameters: TLBParameters = TLBParameters( 264 name = "hytlb", 265 NWays = 48, 266 outReplace = false, 267 partialStaticPMP = true, 268 outsideRecvFlush = true, 269 saveLevel = true 270 ), 271 pftlbParameters: TLBParameters = TLBParameters( 272 name = "pftlb", 273 NWays = 48, 274 outReplace = false, 275 partialStaticPMP = true, 276 outsideRecvFlush = true, 277 saveLevel = true 278 ), 279 refillBothTlb: Boolean = false, 280 btlbParameters: TLBParameters = TLBParameters( 281 name = "btlb", 282 NWays = 48, 283 ), 284 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 285 NumPerfCounters: Int = 16, 286 icacheParameters: ICacheParameters = ICacheParameters( 287 tagECC = Some("parity"), 288 dataECC = Some("parity"), 289 replacer = Some("setplru"), 290 nMissEntries = 2, 291 nProbeEntries = 2, 292 nPrefetchEntries = 12, 293 nPrefBufferEntries = 32, 294 ), 295 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 296 tagECC = Some("secded"), 297 dataECC = Some("secded"), 298 replacer = Some("setplru"), 299 nMissEntries = 16, 300 nProbeEntries = 8, 301 nReleaseEntries = 18, 302 nMaxPrefetchEntry = 6, 303 )), 304 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 305 name = "l2", 306 ways = 8, 307 sets = 1024, // default 512KB L2 308 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 309 )), 310 L2NBanks: Int = 1, 311 usePTWRepeater: Boolean = false, 312 softTLB: Boolean = false, // dpi-c l1tlb debug only 313 softPTW: Boolean = false, // dpi-c l2tlb debug only 314 softPTWDelay: Int = 1 315){ 316 def vlWidth = log2Up(VLEN) + 1 317 318 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 319 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 320 321 val intSchdParams = { 322 implicit val schdType: SchedulerType = IntScheduler() 323 SchdBlockParams(Seq( 324 IssueBlockParams(Seq( 325 ExeUnitParams("ALU0", Seq(AluCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 1), 326 ExeUnitParams("ALU1", Seq(AluCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 1), 327 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 328 IssueBlockParams(Seq( 329 ExeUnitParams("MUL0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 1), 330 ExeUnitParams("MUL1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 1), 331 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 332 IssueBlockParams(Seq( 333 ExeUnitParams("BJU0", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(8, 0)), Seq(IntRD(9, 0)))), 334 ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(10, 0)), Seq(IntRD(12, 1)))), 335 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 336 IssueBlockParams(Seq( 337 ExeUnitParams("BJU2", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(11, 0)), Seq(IntRD(7, 1)))), 338 ), numEntries = IssueQueueSize / 2, numEnq = 1, numComp = IssueQueueCompEntrySize / 2), 339 IssueBlockParams(Seq( 340 ExeUnitParams("IMISC0", Seq(VSetRiWiCfg, I2fCfg, I2vCfg, VSetRiWvfCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 1), VfWB(4, 1)), Seq(Seq(IntRD(5, 1)), Seq(IntRD(3, 1)))), 341 ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 7, 1)), Seq(Seq(IntRD(1, Int.MaxValue)), Seq(IntRD(9, Int.MaxValue)))), 342 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 343 ), 344 numPregs = intPreg.numEntries, 345 numDeqOutside = 0, 346 schdType = schdType, 347 rfDataWidth = intPreg.dataCfg.dataWidth, 348 numUopIn = dpParams.IntDqDeqWidth, 349 ) 350 } 351 val vfSchdParams = { 352 implicit val schdType: SchedulerType = VfScheduler() 353 SchdBlockParams(Seq( 354 IssueBlockParams(Seq( 355 ExeUnitParams("VFEX0", Seq(VfaluCfg, VfmaCfg, VialuCfg, VppuCfg, F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 0), IntWB(port = 0, 1)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 356 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 357 IssueBlockParams(Seq( 358 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfmaCfg, VimacCfg, VipuCfg, F2vCfg, VfcvtCfg), Seq(VfWB(port = 1, 0), IntWB(port = 8, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 359 ExeUnitParams("VFEX2", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 2, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 360 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 361 ), 362 numPregs = vfPreg.numEntries, 363 numDeqOutside = 0, 364 schdType = schdType, 365 rfDataWidth = vfPreg.dataCfg.dataWidth, 366 numUopIn = dpParams.FpDqDeqWidth, 367 ) 368 } 369 370 val memSchdParams = { 371 implicit val schdType: SchedulerType = MemScheduler() 372 val rfDataWidth = 64 373 374 SchdBlockParams(Seq( 375 IssueBlockParams(Seq( 376 ExeUnitParams("STA0", Seq(StaCfg), Seq(), Seq(Seq(IntRD(3, 1)))), 377 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 378 IssueBlockParams(Seq( 379 ExeUnitParams("HYU0", Seq(HyldaCfg, HystaCfg, MouCfg), Seq(IntWB(5, 0), VfWB(5, 0)), Seq(Seq(IntRD(6, 0)))), 380 ExeUnitParams("HYU1", Seq(FakeHystaCfg), Seq(), Seq()), // fake unit, used to create a new writeback port 381 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 382 IssueBlockParams(Seq( 383 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(6, 0)), Seq(Seq(IntRD(12, 0))), true, 1), 384 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 385 IssueBlockParams(Seq( 386 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(7, 0)), Seq(Seq(IntRD(13, 0))), true, 1), 387 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 388 IssueBlockParams(Seq( 389 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(3, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 390 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 391 IssueBlockParams(Seq( 392 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(13, 1), VfRD(6, 0)))), 393 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 394 IssueBlockParams(Seq( 395 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 1), VfRD(10, Int.MaxValue)))), 396 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 397 ), 398 numPregs = intPreg.numEntries max vfPreg.numEntries, 399 numDeqOutside = 0, 400 schdType = schdType, 401 rfDataWidth = rfDataWidth, 402 numUopIn = dpParams.LsDqDeqWidth, 403 ) 404 } 405 406 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 407 408 def iqWakeUpParams = { 409 Seq( 410 WakeUpConfig( 411 Seq("ALU0", "ALU1", "MUL0", "MUL1", "LDU0", "LDU1", "HYU0") -> 412 Seq("ALU0", "ALU1", "MUL0", "MUL1", "BJU0", "BJU1", "BJU2", "LDU0", "LDU1", "STA0", "STD0", "STD1", "HYU0") 413 ), 414 WakeUpConfig(Seq("IMISC0") -> Seq("VFEX0","VFEX1")), 415 ).flatten 416 } 417 418 val backendParams: BackendParams = backend.BackendParams( 419 Map( 420 IntScheduler() -> intSchdParams, 421 VfScheduler() -> vfSchdParams, 422 MemScheduler() -> memSchdParams, 423 ), 424 Seq( 425 intPreg, 426 vfPreg, 427 ), 428 iqWakeUpParams, 429 ) 430} 431 432case object DebugOptionsKey extends Field[DebugOptions] 433 434case class DebugOptions 435( 436 FPGAPlatform: Boolean = false, 437 EnableDifftest: Boolean = false, 438 AlwaysBasicDiff: Boolean = true, 439 EnableDebug: Boolean = false, 440 EnablePerfDebug: Boolean = true, 441 UseDRAMSim: Boolean = false, 442 EnableConstantin: Boolean = false, 443 EnableChiselDB: Boolean = false, 444 AlwaysBasicDB: Boolean = true, 445 EnableTopDown: Boolean = false, 446 EnableRollingDB: Boolean = false 447) 448 449trait HasXSParameter { 450 451 implicit val p: Parameters 452 453 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 454 455 val coreParams = p(XSCoreParamsKey) 456 val env = p(DebugOptionsKey) 457 458 val XLEN = coreParams.XLEN 459 val VLEN = coreParams.VLEN 460 val ELEN = coreParams.ELEN 461 val minFLen = 32 462 val fLen = 64 463 def xLen = XLEN 464 465 val HasMExtension = coreParams.HasMExtension 466 val HasCExtension = coreParams.HasCExtension 467 val HasDiv = coreParams.HasDiv 468 val HasIcache = coreParams.HasICache 469 val HasDcache = coreParams.HasDCache 470 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 471 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 472 val AsidLength = coreParams.AsidLength 473 val ReSelectLen = coreParams.ReSelectLen 474 val AddrBytes = AddrBits / 8 // unused 475 val DataBits = XLEN 476 val DataBytes = DataBits / 8 477 val VDataBytes = VLEN / 8 478 val HasFPU = coreParams.HasFPU 479 val HasVPU = coreParams.HasVPU 480 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 481 val FetchWidth = coreParams.FetchWidth 482 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 483 val EnableBPU = coreParams.EnableBPU 484 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 485 val EnableRAS = coreParams.EnableRAS 486 val EnableLB = coreParams.EnableLB 487 val EnableLoop = coreParams.EnableLoop 488 val EnableSC = coreParams.EnableSC 489 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 490 val HistoryLength = coreParams.HistoryLength 491 val EnableGHistDiff = coreParams.EnableGHistDiff 492 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 493 val UbtbGHRLength = coreParams.UbtbGHRLength 494 val UbtbSize = coreParams.UbtbSize 495 val EnableFauFTB = coreParams.EnableFauFTB 496 val FtbSize = coreParams.FtbSize 497 val FtbWays = coreParams.FtbWays 498 val RasSize = coreParams.RasSize 499 val RasSpecSize = coreParams.RasSpecSize 500 val RasCtrSize = coreParams.RasCtrSize 501 502 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 503 coreParams.branchPredictor(resp_in, p) 504 } 505 val numBr = coreParams.numBr 506 val TageTableInfos = coreParams.TageTableInfos 507 val TageBanks = coreParams.numBr 508 val SCNRows = coreParams.SCNRows 509 val SCCtrBits = coreParams.SCCtrBits 510 val SCHistLens = coreParams.SCHistLens 511 val SCNTables = coreParams.SCNTables 512 513 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 514 case ((n, cb), h) => (n, cb, h) 515 } 516 val ITTageTableInfos = coreParams.ITTageTableInfos 517 type FoldedHistoryInfo = Tuple2[Int, Int] 518 val foldedGHistInfos = 519 (TageTableInfos.map{ case (nRows, h, t) => 520 if (h > 0) 521 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 522 else 523 Set[FoldedHistoryInfo]() 524 }.reduce(_++_).toSet ++ 525 SCTableInfos.map{ case (nRows, _, h) => 526 if (h > 0) 527 Set((h, min(log2Ceil(nRows/TageBanks), h))) 528 else 529 Set[FoldedHistoryInfo]() 530 }.reduce(_++_).toSet ++ 531 ITTageTableInfos.map{ case (nRows, h, t) => 532 if (h > 0) 533 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 534 else 535 Set[FoldedHistoryInfo]() 536 }.reduce(_++_) ++ 537 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 538 ).toList 539 540 541 542 val CacheLineSize = coreParams.CacheLineSize 543 val CacheLineHalfWord = CacheLineSize / 16 544 val ExtHistoryLength = HistoryLength + 64 545 val ICacheECCForceError = coreParams.ICacheECCForceError 546 val IBufSize = coreParams.IBufSize 547 val IBufNBank = coreParams.IBufNBank 548 val backendParams: BackendParams = coreParams.backendParams 549 val DecodeWidth = coreParams.DecodeWidth 550 val RenameWidth = coreParams.RenameWidth 551 val CommitWidth = coreParams.CommitWidth 552 val MaxUopSize = coreParams.MaxUopSize 553 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 554 val RenameSnapshotNum = coreParams.RenameSnapshotNum 555 val FtqSize = coreParams.FtqSize 556 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 557 val IntLogicRegs = coreParams.IntLogicRegs 558 val FpLogicRegs = coreParams.FpLogicRegs 559 val VecLogicRegs = coreParams.VecLogicRegs 560 val VCONFIG_IDX = coreParams.VCONFIG_IDX 561 val IntPhyRegs = coreParams.intPreg.numEntries 562 val VfPhyRegs = coreParams.vfPreg.numEntries 563 val MaxPhyPregs = IntPhyRegs max VfPhyRegs 564 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 565 val RobSize = coreParams.RobSize 566 val RabSize = coreParams.RabSize 567 val VTypeBufferSize = coreParams.VTypeBufferSize 568 val IntRefCounterWidth = log2Ceil(RobSize) 569 val LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 570 val LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 571 val LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 572 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 573 val LoadQueueRARSize = coreParams.LoadQueueRARSize 574 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 575 val RollbackGroupSize = coreParams.RollbackGroupSize 576 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 577 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 578 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 579 val StoreQueueSize = coreParams.StoreQueueSize 580 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 581 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 582 val VlsQueueSize = coreParams.VlsQueueSize 583 val dpParams = coreParams.dpParams 584 585 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 586 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 587 588 val NumRedirect = backendParams.numRedirect 589 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 590 val FtqRedirectAheadNum = NumRedirect 591 val LoadPipelineWidth = coreParams.LoadPipelineWidth 592 val StorePipelineWidth = coreParams.StorePipelineWidth 593 val VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 594 val VecStorePipelineWidth = coreParams.VecStorePipelineWidth 595 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 596 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 597 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 598 val StoreBufferSize = coreParams.StoreBufferSize 599 val StoreBufferThreshold = coreParams.StoreBufferThreshold 600 val EnsbufferWidth = coreParams.EnsbufferWidth 601 val UsQueueSize = coreParams.UsQueueSize 602 val VlFlowSize = coreParams.VlFlowSize 603 val VlUopSize = coreParams.VlUopSize 604 val VsFlowL1Size = coreParams.VsFlowL1Size 605 val VsFlowL2Size = coreParams.VsFlowL2Size 606 val VsUopSize = coreParams.VsUopSize 607 val UncacheBufferSize = coreParams.UncacheBufferSize 608 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 609 val EnableFastForward = coreParams.EnableFastForward 610 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 611 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 612 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 613 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 614 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 615 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 616 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 617 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 618 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 619 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 620 val asidLen = coreParams.MMUAsidLen 621 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 622 val refillBothTlb = coreParams.refillBothTlb 623 val iwpuParam = coreParams.iwpuParameters 624 val dwpuParam = coreParams.dwpuParameters 625 val itlbParams = coreParams.itlbParameters 626 val ldtlbParams = coreParams.ldtlbParameters 627 val sttlbParams = coreParams.sttlbParameters 628 val hytlbParams = coreParams.hytlbParameters 629 val pftlbParams = coreParams.pftlbParameters 630 val btlbParams = coreParams.btlbParameters 631 val l2tlbParams = coreParams.l2tlbParameters 632 val NumPerfCounters = coreParams.NumPerfCounters 633 634 val instBytes = if (HasCExtension) 2 else 4 635 val instOffsetBits = log2Ceil(instBytes) 636 637 val icacheParameters = coreParams.icacheParameters 638 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 639 640 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 641 // for constrained LR/SC loop 642 val LRSCCycles = 64 643 // for lr storm 644 val LRSCBackOff = 8 645 646 // cache hierarchy configurations 647 val l1BusDataWidth = 256 648 649 // load violation predict 650 val ResetTimeMax2Pow = 20 //1078576 651 val ResetTimeMin2Pow = 10 //1024 652 // wait table parameters 653 val WaitTableSize = 1024 654 val MemPredPCWidth = log2Up(WaitTableSize) 655 val LWTUse2BitCounter = true 656 // store set parameters 657 val SSITSize = WaitTableSize 658 val LFSTSize = 32 659 val SSIDWidth = log2Up(LFSTSize) 660 val LFSTWidth = 4 661 val StoreSetEnable = true // LWT will be disabled if SS is enabled 662 val LFSTEnable = true 663 664 val PCntIncrStep: Int = 6 665 val numPCntHc: Int = 25 666 val numPCntPtw: Int = 19 667 668 val numCSRPCntFrontend = 8 669 val numCSRPCntCtrl = 8 670 val numCSRPCntLsu = 8 671 val numCSRPCntHc = 5 672 val printEventCoding = true 673 674 // Parameters for Sdtrig extension 675 protected val TriggerNum = 4 676 protected val TriggerChainMaxLength = 2 677} 678